WO2004105274A1 - Appareil de reprise de compensation de retard de concatenation virtuelle - Google Patents

Appareil de reprise de compensation de retard de concatenation virtuelle Download PDF

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Publication number
WO2004105274A1
WO2004105274A1 PCT/CN2004/000518 CN2004000518W WO2004105274A1 WO 2004105274 A1 WO2004105274 A1 WO 2004105274A1 CN 2004000518 W CN2004000518 W CN 2004000518W WO 2004105274 A1 WO2004105274 A1 WO 2004105274A1
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Prior art keywords
cascade
container
sequence number
multiframe
circuit
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PCT/CN2004/000518
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English (en)
French (fr)
Inventor
Fuchuan Zhao
Zhengqi Li
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Zte Corporation
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Publication date
Application filed by Zte Corporation filed Critical Zte Corporation
Priority to EP04738167.8A priority Critical patent/EP1638223B1/en
Publication of WO2004105274A1 publication Critical patent/WO2004105274A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0057—Operations, administration and maintenance [OAM]
    • H04J2203/006—Fault tolerance and recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0094—Virtual Concatenation

Definitions

  • the present invention relates to a synchronous digital system SDH transmission network, and in particular, to a device for compensating and recovering a delay caused by data transmission using a virtual concatenation technology.
  • SDH stipulates a series of mapping methods and mapping structures, so that PDH signals can be transmitted on the SDH network.
  • the point-to-point transmission method of the time division multiplexing method is adopted, and several different fixed transmission rates are specified.
  • the traditional telecommunications business has entered a period of slow growth, and the profit margin has been declining, but the data business has developed rapidly.
  • cascading refers to combining multiple containers of the same type to transfer rate services between two SDH standard containers.
  • virtual cascading refers to a logical cascading relationship with specific levels. The transport paths of linked containers are irrelevant.
  • Figure 1, Figure 2, Figure 3, and Figure 4 show the virtual cascading diagrams of several types of containers.
  • X indicates the number of cascade group content containers.
  • the virtual concatenated transmission introduced by SDH4 is a mechanism that logically bundles multiple containers of the same type to deliver services. Physically, the transmission method of these containers is not different from the original. In actual operation, the logically bound containers are sent out at the sending end at the same time, but because the transmission paths are inconsistent, different delays are generated. Therefore, the receiving end needs to use a delay compensation method to make the business The receiver can recover normally.
  • the SDH network does not always work in synchronization, that is, the working clock reference of the sender and receiver is not the same. This will cause the SDH pointer to be adjusted, so that the receiver reaches the receiver. The phase shift of the container at the end may cause the delay recovery circuit to work abnormally. Secondly, various abnormalities may occur during the operation of the SDH transmission network.
  • the technical problem to be solved by the present invention is to provide a virtual cascading delay compensation recovery device, which realizes the automatic recovery of reliable cascade services and achieves the delay output as small as possible.
  • the virtual cascade delay compensation recovery device of the present invention includes a cascade multiframe detection circuit, a cascade sequence automatic adjustment circuit, a buffer area, a write control circuit, a read control relocation and adaptive circuit, and a read control circuit;
  • the cascade multiframe detection circuit is configured to perform lock detection on the cascade multiframe sequence number of the SDH frame and detect the cascade sequence number of the container;
  • the cascade sequence automatic adjustment circuit is used to The cascade sequence number of the container, adjust the order of the container to be consistent with the sequence of the sending end;
  • the buffer area is partitioned according to the serial number of the cascaded multiframe of the container and the SDH frame, and is used to buffer the data frame that arrives first in the cascaded SDH frame.
  • the written control circuit is used to according to the current level of the SDK frame in each container. Combining the multi-frame sequence numbers, writing the SDH frames in the adjusted container into the buffer area; the read control relocation and adaptive circuit for adjusting the frequency and phase of the container; the read control circuit, It is configured to read out the SDH frame from the buffer area according to the signal output by the read control relocation and adaptive circuit, and complete the cascading recovery.
  • the cascade multiframe detection circuit detects whether the cascade multiframe sequence numbers of the SDH frames in each container in the cascade group are continuous, and if continuous, determines the current cascade multiframe sequence number of the SDH frame in the container.
  • the cascade multiframe detection circuit also performs cascade cross-border detection, that is, detects the maximum difference between the current cascade multiframe sequence numbers of SDH frames in different containers in the cascade group, so as to determine whether the set buffer area meets the requirements.
  • the cascaded multiframe detection circuit detects a data signal, a K4 overhead position indication signal or an H4 overhead position indication signal, and detects whether there is an abnormality indication signal, determines the locked state of the cascaded multiframe sequence number, and determines the lock state of the cascaded multiframe sequence number, and according to the K4 byte or H4 Byte, detects the cascade sequence number of each container.
  • the cascading multi-frame detection circuit detects the cascading sequence number of each container, if three consecutive cascading sequence numbers appear, it is confirmed that the cascading sequence number is the cascade sequence number of the container.
  • the cascaded multiframe detection circuit determines the locked state of the cascaded multiframe sequence number, if it is a low-order container, it detects whether there is a multiframe delimited sequence in the K4 overhead, and if a multiframe delimited sequence is detected, then Continue to check whether the serial number of the cascade multiframe in bi t2 of K4 bytes is continuous, if it is continuous, it means that it is locked; if it is not continuous, it means that the cascade multiframe sequence number of this container is not locked; No multiframe delimitation sequence MFAS was found in any of them. If the pattern of K4 bytes is not correct, it means that the cascade multiframe sequence number of the container is not locked.
  • the cascade multiframe detection circuit determines the locked state of the cascade multiframe sequence number, if it is a high-order Container, check whether the serial number of the cascade multiframe in the H4 byte is continuous. If the serial number of the cascade multiframe is not continuous for three consecutive frames, the serial number of the cascade multiframe is not locked. If the consecutive multi-frame sequence numbers are continuous, it means that the cascade multi-frame sequence numbers are locked.
  • the cascade multiframe detection circuit detects that an abnormal indication signal appears in any container or the cascade multiframe sequence number is not locked, the cascade multiframe sequence number of the entire cascade group is considered to be unlocked.
  • the cascade sequence automatic adjustment circuit uses a space division cross matrix, and outputs the adjusted cascade sequence number of the adjusted container according to the input cascade sequence number of the C-4 container.
  • the cascade sequence automatic adjustment circuit uses a time-division cross matrix, and according to the input cascade sequence number of the C-3, C-12 or C-11 container, the cascade sequence number of the adjusted container is output in a given order.
  • the cross matrix is automatically configured, that is, the hardware is used to directly configure the cross matrix according to the cascade sequence number. Specifically, a switch circuit is used. If the cascade multiframe sequence number of the entire cascade group is not locked, the entire reset is performed. Switching circuit; if it is in the locked state, it is sorted from small to large according to the cascading sequence number of the cascade group container, and the sorting result is used to control the switching circuit to complete the automatic sorting of the containers.
  • the read control relocation and adaptive circuit detects the state of the transmission link, and after each container in the cascade group recovers from the abnormality, it re-determines the starting address of the read buffer area.
  • the read control relocation and adaptive circuit completes state adjustment through a state machine.
  • the state machine has three states: a search state, a comparison state, and an adjustment state.
  • the state transition mode is: no matter which state is currently in, if an alarm occurs, Then it enters the search state, searches for the initial state of the cascade group, and sends a reset signal to the read control circuit.
  • the comparison state compares the write address of the current container with the current read address in the comparison state, as described above. If the difference between the write address and the read address exceeds the threshold value, the system enters the adjustment state; the adjustment state sends an adjustment signal to the read control circuit, and then enters the comparison state.
  • the read control circuit generates read data permission for each container according to the SDH frame structure and the type of the container.
  • the format of the read address is (cascading sequence number, cascading multiframe sequence number, offset). For each byte of data read, the offset increases by 1. When the maximum value of the container is reached, the offset The displacement is reset.
  • the read control circuit After the read control circuit receives a reset signal from the read control relocation and adaptation circuit, it reinitializes the start address of the read data.
  • the read control circuit generates an adjustment operation after receiving the adjustment signals sent by the read control relocation and adaptive circuit, including two adjustment modes: positive adjustment and negative adjustment; for low-order containers, the positive adjustment refers to Stop reading one byte of data at a position after V3 in each TU12 structure; the negative adjustment refers to reading one byte of data at the V3 position in each T12 structure; and for high-order containers, all The positive adjustment refers to stopping reading three bytes of data continuously after the position of ⁇ 3; the negative adjustment refers to reading one byte of data at each ⁇ 3 position.
  • the invention adopts virtual cascade automatic fault detection and recovery, automatic sequence adjustment and automatic phase tracking technology, which can realize reliable automatic cascade recovery and greatly reduce the output delay, and the automatic tracking function of the invention when the network is not synchronized It can detect whether the network delay exceeds the set requirement, which further improves the reliability of the network.
  • Figure 1 is a schematic diagram of the virtual cascade of VC-3 containers
  • Figure 2 is a schematic diagram of virtual cascading of a VC-4 container
  • Figure 3 is a schematic diagram of the virtual cascade of the VC-12 container
  • Figure 4 is a schematic diagram of the virtual concatenation of the VC-11 container
  • FIG. 5 is a schematic diagram of a virtual cascade delay compensation recovery device according to the present invention.
  • FIG. 6 is a transmission pattern of bi t l in the overhead of cascaded container cascade
  • FIG. 7 is a transmission pattern of bi t2 in the overhead of the cascaded container
  • FIG. 8 is a state transition diagram of the read control relocation and adaptive circuit 5 in FIG. 5. detailed description
  • Figures 1 to 4 show schematic diagrams of virtual concatenation of VC-3, VC-4, VC-12, and VC-11 containers, which have been introduced in the background art and will not be described here again.
  • the virtual cascade delay compensation recovery device of the present invention includes a cascade multiframe detection circuit 1, a cascade sequence automatic adjustment circuit 2, a buffer area 3, a write control circuit 4, a read control relocation and an adaptive circuit 5, and read control circuit 6.
  • Cascade multiframe detection circuit 1 performs lock detection on the cascade multiframe sequence number MFI, and detects the cascade sequence number SQ of the container. Cascade multiframe detection circuit 1 detects whether the cascade multiframe sequence number MFI of the SDH frames in each container in the cascade group is continuous, and if continuous, determines the current cascade multiframe sequence number MFI of the SDH frame in the container. The cascade multiframe detection circuit 1 also performs cascade cross-border detection, that is, detects the maximum difference between the current cascade multiframe sequence number MFI of SDH frames in different containers in the cascade group, so as to determine whether the set buffer area meets the requirements.
  • cascaded multi-frame detection circuit 1 performs polling detection on each frame, assuming that there are N containers in the cascade group in buffer area 3, and the size of buffer area 3 is M times the size of the container.
  • the buffer area 3 allocated for each container is M / N. If in the entire SDH frame structure, the current cascade multiframe sequence number MFI of a certain container is equal to M / N, then record the maximum cascade multiframe sequence number MFI and the minimum cascade multiframe sequence number in the current-cascade group MFI, if the difference between the two is greater than M / N, it means that the cascade is out of bounds, and an alarm signal Conca- Ai s is generated.
  • the position of the virtual container VC in the SDH frame structure can be determined, that is, the SPE signal indication, the position of the virtual container K4 overhead K4-en or the position of the H4 overhead H4-en, and the start of the virtual container vc Position n or V5;
  • the pointer interpretation can give the virtual container pointer whether there is an abnormal indication signal AIS.
  • the above signal and the data signal Data are input into the cascaded multi-frame detection circuit 1, and the data signals Data and K4 overhead position indication signal K4_en or H4 overhead position indication signal H4_en are detected.
  • the cascade sequence number SQ of each container is detected based on the H4 byte or K4 byte, and the cascade sequence number of the container.
  • the detection method of SQ is: If three consecutive cascading sequence numbers appear consecutively, confirm that the cascading sequence number is the cascading sequence number of the container.
  • the cascaded multi-frame detection circuit 1 determines the locked state of the cascaded multi-frame sequence number MFI, if it is a low-order container, it detects the multi-frame delimitation sequence MFAS in the K4 overhead. If the pattern of the MFAS sequence is detected, then Further check whether the cascaded multiframe sequence number MFI in bit2 of K4 overhead is continuous. If continuous, it indicates that the cascaded multiframe sequence number MFI is locked. If it is not continuous, it indicates that the cascaded multiframe sequence number MFI of the SDH frame in the container. Not locked. If no MFAS sequence is detected in 64 consecutive K4 overheads, the K4 overhead pattern is considered incorrect, indicating that the container's cascaded multiframe sequence number MFI is not locked.
  • Figures 6 and 7 show the transmission patterns of bitl and bi t2 in the K4 overhead, respectively, where the MFAS of Figure 6 is an 11-bit fixed pattern "01111111110", and the Frame count of Figure 7 is the cascade multiframe sequence number of the current container MFI, Sequence indicator represents the sequence number SQ of the cascade group container.
  • the concatenated multiframe sequence number MFI in the H4 byte is detected, as shown in Table 1.
  • the H4 byte is used to transmit information about the cascade.
  • the cascade multiframe sequence number MFI includes MFI2 and MFI1. It is a 12-bit counter whose value is the container's cascade multiframe sequence number MFI. Containers with the same MFI sequence number are cascaded together.
  • the cascade sequence number SQ is the Sequence indicator, which indicates the sequence number of each container in the cascade group.
  • the cascade multiframe sequence numbers of three consecutive frames are discontinuous, the cascade multiframe sequence number MFI is not considered. Locked; if the cascade multiframe sequence numbers of three consecutive frames are consecutive, it means that the cascade multiframe sequence number MFI is locked.
  • Sequence indicator SQ MSB bits 1 1 1 0 14
  • Cascade multiframe detection circuit 1 outputs the data signal Data, the cascade sequence number SQ of the container, the cascade multiframe sequence number MFI, the cascade multiframe sequence number lock signal latch_ind, and the alarm signal Conca_Ais to the stage Coupling sequence is automatically adjusted in circuit 2.
  • the cascade sequence automatic adjustment circuit 2 adjusts the sequence of the containers according to the cascade sequence number SQ of each container in the cascade group so that the sequence of the containers is the same as the sequence of the sending end.
  • the cascade sequence automatic adjustment circuit 2 uses a space division cross matrix, and outputs the adjusted cascade sequence number of the adjusted container according to the cascade sequence number SQ of the container, such as in ascending order. Sort the output.
  • the cascade sequence automatic adjustment circuit 2 uses a time-division cross matrix, and outputs the adjusted cascade sequence number of the containers in order according to the cascade sequence number of the container, such as from small to small. Sort the output in large order.
  • the configuration of the cross matrix can be performed in two ways: program configuration and automatic configuration; program configuration is a configuration method that extracts the cascade sequence number SQ of each container through a micro control unit (MCU) and then performs cross-program calculation. ; Automatic configuration is the configuration of the cross matrix using hardware circuits directly according to the cascade sequence number SQ. The configuration information is to sort the cascading sequence numbers SQ of different containers in ascending order.
  • program configuration is a configuration method that extracts the cascade sequence number SQ of each container through a micro control unit (MCU) and then performs cross-program calculation.
  • Automatic configuration is the configuration of the cross matrix using hardware circuits directly according to the cascade sequence number SQ. The configuration information is to sort the cascading sequence numbers SQ of different containers in ascending order.
  • the cascade sequence automatic adjustment circuit 2 outputs the cascade sequence number S (!, The cascade multiframe sequence number MFI, and the data signal Data of the adjusted container to the write control circuit 4.
  • the write control circuit 4 writes the adjusted container data to the corresponding partition of the buffer area 3 according to different containers and the current cascaded multiframe sequence number MFI of the container.
  • the format of the write address is (SQ, MFI, offset).
  • the offset is increased by 1 for each byte of data written.
  • the maximum value of the container is reached, the offset is reset.
  • the maximum capacity varies according to the type of container, which is equal to the size of the type of container in bytes.
  • Buffer area 3 is partitioned according to the container and the cascaded multiframe sequence number MFI. Because the transmission paths of each container in the same cascade group can be inconsistent, when different containers sent by the sending end arrive at the receiving port at the same time, their path delays will also be inconsistent. Therefore, at the receiving end, in order to recover the cascaded data, a buffer area 3 is needed, which is used to cache the data that arrives first in the cascaded data, and the cascaded data is all in order to recover the data.
  • Cache area 3 can implement two-level partitioning. The first-level partition is partitioned according to containers, that is, the data of different containers are stored in different partitions; the second-level partition is partitioned according to the cascade multiframe sequence number MFI. The container data of the same cascade multi-frame sequence number MFI has the same base address in different container buffers.
  • the SDH network does not necessarily work in a synchronized state, that is, the clock bases at which the sender and receiver work.
  • pointers are introduced in the SDH network to adjust the frequency and phase of the container. Due to the pointer adjustment, the relative phase relationship of each container reaching the receiving end has been changing. Therefore, the present invention uses a read control relocation and adaptive circuit 5 to adjust the frequency and phase of the container and detect the status of the transmission link. After each container in the concatenation group recovers from the exception, the read start address of the cache area is re-determined, so that the cascaded data output delay is as small as possible.
  • the input signals of the read control relocation and adaptive circuit 5 include: the current write address Addr of each container output by the write control circuit 4, the current read address r_Addr output by the read control circuit 6, and the cascading sequence is automatically adjusted.
  • the output signals include: an adjustment signal Adjus t [1: 0], a read pointer initialization indication signal r—Addr—rs t and The initial address r_ Addr_int of the read pointer is output to the read control circuit 6;
  • the adjustment signal Adjus t [1: 0] can be a positive adjustment signal or a negative adjustment signal.
  • the read control relocation and adaptive circuit 5 In order to accurately recover the cascaded data, the read control relocation and adaptive circuit 5 must continuously track the phase relationship of the input containers and compare it with the phase of the read data to determine whether the phase of the read data needs to be adjusted. In the present invention, the read control relocation and adaptive circuit 5 completes the state adjustment through a state machine.
  • the state machine has three states: search state search, comparison state compare, and adjustment state adjus t. The state transition mode is shown in FIG.
  • the read control circuit 6 After the read control circuit 6 receives the adjustment signal Adjust output by the read control relocation and the adaptive circuit 5, it generates a read data enable signal Rd_en for each container according to the frame structure of the SDH and the type of the container.
  • the data is read from the buffer area 3.
  • the format of the read address is (SQ, MFI, offset). For each byte of data read, the offset is increased by 1. When the maximum value of the container is reached, the offset The amount is reset to complete the cascade recovery.
  • the maximum value of a container varies according to the type of container, which is equal to the size of a container of this type calculated in bytes.
  • the read control circuit 6 receives the read pointer initialization instruction signal r—addr—rst (that is, the reset signal) from the read control relocation and adaptive circuit 5, it reinitializes the start address of the read.
  • an adjustment operation is generated accordingly.
  • the adjustment operation is to perform the same adjustment on each container in the cascade group at the same time, including two methods: positive adjustment and negative adjustment.
  • positive adjustment is to stop reading one byte of data at a position after V3 in each TU12 structure; for high-order containers, positive adjustment is to stop reading three bytes of data continuously after the position of H3.
  • negative adjustment is to read one byte of data at the V3 position of each TU12; for high-order containers, negative adjustment is to read one byte of data at each H3 position.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Description

一种虛级联延时补偿恢复装置 技术领域
本发明涉及同步数字体系 SDH传输网络， 尤其涉及一种对采用虚级联技术 传送数据产生的延时进行补偿恢复的装置。
背景技术
随着信息技术的发展和人们对通讯带宽的巨大需求， 通讯网络已经从模拟 网络向数字网络转变，光纤技术的发展大大推动了数字通讯技术的发展，满足人 们对通讯带宽的需求。 光歼通讯提供了低成本、 高速的信息服务， 迅速代替了 传统的铜缆通讯。 为适应光纤技术的发展， 统一各通讯厂商的产品， 实现传输 信息的互通， 国际电联制定了 SDH体系的通讯标准。 SDH体系的帧信息结构有 丰富的开销字节， 给信息的传输和网络管理带来了方便， 而统一的接口参数可 使不同厂商的设备一起组网工作， 实现地域甚至全球的通讯网絡互通， 这些优 点使得以 SDH为基础的传输网成为光通讯网建设的主导方向。 由于原有的通讯 网络以准同步数字体系 PDH网络为主， 为降低网络的建设成本， 更好地利用原 有网络， SDH规定了一系列的映射方式和映射结构， 使得 PDH信号可以在 SDH 网络中传输， 适应了以电话、 电视这种固定速率电信服务要求。
从 SDH 网络本身来讲， 采用的是时分复用方式的点到点传输方式， 规定了 几个不同的固定传送速率。 近几年， 传统的电信业务进入了緩慢增长期， 利润 率一直在下降，但是数据业务却得到飞速发展，人们对于数据业务的需求强劲， 但是建立完全的数据网络所需的投资大、 周期长。 因此充分利用现有的 SDH网 络资源， 实现高速率、 大容量和长距离的数据传送是一个比较合适的方式。
由于数据业务的特点是具突发性和带宽可变化， 因此为了适应数据业务的 需要，在 SDH中引入了级联的概念。所谓级联是指将多个同种容器组合在一起， 用以传送速率介于两种 SDH标准容器之间的速率业务； 所谓虚级联是指一种逻 辑上的级联关系， 与具体级联在一起的容器的传送路径无关。 图 1、 图 2、 图 3 和图 4给出了几种类型的容器的虛级联示意图， 图中 X表示级联组内容器的数 目。 通过虚级联， SDH 网络原来如何传送这种容器， 现在可仍然保持不变， 这 就保证了与现有 SDH网络的兼容性。
为了有效利用有限的带宽， SDH 引入的虚级联的传输 4既念是将多个同种容 器在逻辑上捆绑在一起传送业务的机制， 在物理上， 这些容器的传送方式和原 来没有任何区别， 而在实际运行时， 逻辑上捆绑在一起的容器在发送端被同时 发出， 但是由于传输的路径不一致， 产生了不同的延时， 因此在接收端需要釆 用延时补偿的方法， 使业务在接收端能够正常恢复； 同时， 由于各种原因的影 响， SDH 网络并不总是工作在同步状态， 即发送端和接收端的工作时钟基准不 一致，这样会引起 SDH的指针调整，从而使到达接收端的容器的相位发生漂移， 有可能使延时恢复电路的工作不正常； 其次 SDH传输网络在运行过程中也可能 会出现各种异常。
发明内容
本发明所要解决的技术问题在于提供一种虚级联延时补偿恢复装置， 实现 可靠的级联业务的自动恢复， 达到尽可能小的延时输出。
本发明所述虚级联延时补偿恢复装置， 包括级联复帧检测电路、 级联顺序 自动调整电路、 緩存区、 写控制电路、 读控制重定位和自适应电路， 以及读控 制电路； 其中： 所述级联复帧检测电路用于对 SDH帧的级联复帧序列号进行锁 定检测， 以及对容器的级联顺序号进行检测； 所述级联顺序自动调整电路用于 才艮据各个容器的级联顺序号， 调整容器的顺序， 使其与发送端的顺序一致； 所 述緩存区按照容器和 SDH帧的級联复帧序列号进行分区， 用于緩存级联的 SDH 帧中先到达的数据帧； 所迷写控制电路用于依据每个容器中 SDK帧当前的级联 复帧序列号， 将调整顺序后的容器内的 SDH帧写入所述緩存区内； 所述读控制 重定位和自适应电路， 用于调整容器的频率和相位； 所迷读控制电路， 用于根 据所述读控制重定位和自适庶电路输出的信号， 从所迷緩存区中读出 SDH帧， 完成级联的恢复。
所述级联复帧检测电路， 检测级联组内每个容器中 SDH帧的级联复桢序列 号是否连续， 如果连续， 则确定容器中 SDH帧的当前级联复帧序列号。
所述级联复帧检测电路还进行级联越界检测， 即检测级联组内不同容器中 SDH 帧的当前级联复帧序列号之间的最大差， 从而判断设置的緩存区是否满足 要求。
所述级联复帧检测电路检测数据信号、 K4开销位置指示信号或 H4开销位 置指示信号， 以及检测是否有异常指示信号，判別级联复帧序列号的锁定状态， 并根据 K4字节或 H4字节， 检测各个容器的級联顺序号。
所述级联复帧检测电路在检测各个容器的级联顺序号时， 如果出现连续三 个相同的级联顺序号， 则确认该级联顺序号是该容器的级联顺序号。
所述级联复帧检测电路在判别级联复帧序列号的锁定状态时， 如果是低阶 容器， 则检测 K4开销中是否存在复帧定界序列，如果检测到复帧定界序列， 则 继续检测 K4字节的 bi t2中的级联复帧序列号是否连续，如果连续则表示锁定； 如果不连续， 则表示该容器的级联复帧序列号没有锁定； 如果连续 64个 K4字 节中都没有发现复帧定界序列 MFAS , 则认为 K4字节的图案不正确， 则表示该 容器的级联复帧序列号没有锁定。
所述级联复帧检测电路在判别级联复帧序列号的锁定状态时， 如果是高阶 容器，则检测 H4字节中的级联复帧序列号是否连续，如果连续三帧的级联复帧 序列号不连续， 则认为级联复帧序列号没有锁定； 如杲连续三帧的级联复帧序 列号都连续， 则表示级联复帧序列号锁定。
所述级联复帧检测电路如果检测到任何一个容器出现异常指示信号或者级 联复帧序列号没有锁定， 则认为整个级联组的级联复帧序列号没有锁定。
所述級联顺序自动调整电路采用空分交叉矩阵， 根据输入的 C-4容器的级 联顺序号， 按给定的顺序输出调整后的容器的级联顺序号。
所迷级联顺序自动调整电路采用时分交叉矩阵， 根据输入的 C-3、 C- 12或 C-11容器的级联顺序号， 按给定的顺序输出调整后的容器的级联顺序号。
所述交叉矩阵采用自动配置， 即采用硬件电路直接根据级联顺序号实现交 叉矩阵的配置， 具体是： 采用一个开关电路， 如果整个级联組的级联复帧序列 号没有锁定， 则复位整个开关电路； 如果进入锁定状态， 则根据级联组内容器 的级联顺序号， 从小到大进行排序， 并采用排序结果控制开关电路， 完成容器 的自动排序。
所述读控制重定位和自适应电路检测传输链路的状态， 当级联组内的每一 个容器都从异常中恢复正常后， 重新判断读取缓存区数椐的起始地址。
所述读控制重定位和自适应电路通过状态机完成状态调整， 所述状态机有 三个状态： 搜索态、 比较态和调整态， 其状态转移方式是： 无论当前处于哪个 状态， 如果出现告警， 则进入搜索态， 搜索出级联组的初始状态， 并向读控制 电路发送复位信号， 待告警消失后转入比较态； 在比较态中比较当前容器的写 地址和当前读地址， 如杲上述写读地址之差超过门限值， 则转入调整态； 调整 态向读控制电路发送调整信号， 然后转入比较态。
所述读控制电路根据 SDH帧结构和容器的种类， 产生每个容器的读数据允 许信号， 读地址的格式为（级联顺序号， 级联复帧序列号， 偏移量）， 每读出一 个字节的数据， 偏移量增加 1 , 当达到容器的最大值时， 偏移量复位。
所述读控制电路接收到所述读控制重定位和自适应电路发出的复位信号 后， 重新初始化读数据的起始地址。
所述读控制电路接收到所述读控制重定位和自适应电路发出的调整信号后 产生调整操作， 包括两种调整方式： 正调整和负调整； 对于低阶容器， 所述正 调整是指在每个 TU12结构中的 V3后的一个位置停止读一个字节的数据； 所述 的负调整是指在每个 Τϋ 12结构中的 V3位置读一个字节的数据； 而对于高阶容 器，所述正调整是指在 Η3的位置后连续停止读三个字节的数据； 所述负调整是 指在每个 Η3位置读一个字节的数据。
本发明采用虚级联自动故障检测恢复、自动顺序调整和自动相位跟踪技术， 可以实现可靠的虚级联的自动恢复， 大大减小输出延时， 而本发明在网络不同 步时的自动跟踪功能， 可以检测网络延时是否超过了设定的要求， 进一步提高 了网络的可靠性。
附图说明
图 1是 VC- 3容器的虚级联示意图；
图 2是 VC-4容器的虚级联示意图；
图 3是 VC-12容器的虛级联示意图；
图 4是 VC- 11容器的虚级联示意图；
图 5是本发明虛级联延时补偿恢复装置的示意图；
图 6是^ <阶容器级联用的 开销中 bi t l的传送图案；
图 7是^ ί氐阶容器级联用的 开销中 bi t2的传送图案；
图 8是图 5中读控制重定位和自适应电路 5的状态转移示意图。 具体实施方式
下面根据附图和实施例对本发明做进一步的详细说明。 图 1至图 4给出了 VC-3、 VC-4、 VC-12和 VC-11容器的虚级联示意图， 在背景技术中已经介绍过， 此处不再赞述。
如图 5所示， 本发明虚级联延时补偿恢复装置包括级联复帧检测电路 1、 级联顺序自动调整电路 2、 缓存区 3、 写控制电路 4、 读控制重定位和自适 电 路 5, 以及读控制电路 6。
级联复帧检测电路 1对级联复帧序列号 MFI进行锁定检测， 并对容器的级 联顺序号 SQ进行检测。级联复帧检测电路 1检测级联组内每个容器中 SDH帧的 级联复帧序列号 MFI是否连续， 如果连续， 则确定容器中 SDH帧的当前级联复 帧序列号 MFI。 级联复帧检测电路 1还进行级联越界检测， 即检测级联组内不 同容器中 SDH帧的当前级联复帧序列号 MFI之间的最大差， 从而判断设置的緩 存区是否满足要求，具体方法为：级联复帧检测电路 1对每个帧进行轮询检测， 假设緩存区 3中级联组内有 N个容器， 而緩存区 3的大小是容器大小的 M倍， 则平均每个容器分配的缓存区 3为 M/N。 如果在整个 SDH帧结构中， 某个容器 当前的级联复帧序列号 MFI等于 M/N, 则记录当前—级联组内的最大级联复帧序 列号 MFI和最小级联复帧序列号 MFI ,如果两者之差大于 M/N,则表示级联越界， 产生告警信号 Conca— Ai s。
SDH桢数据经过指针解释后， 可以确定 SDH帧结构中虛容器 VC的位置， 即 SPE信号指示、虚容器 K4开销的位置 K4—en或 H4开销的位置 H4— en、 以及虚容 器 vc的起始位置 n或 V5; 同时指针解释可以给出虚容器的指针是否有异常指 示信号 AIS。 上述信号和数据信号 Data输入到级联复帧检测电路 1中， 检测数 据信号 Data、 K4开销位置指示信号 K4— en或 H4开销位置指示信号 H4— en, 以 及检测是否有异常指示信号 AIS, 从而判别级联复帧序列号 MFI的锁定状态； 同时根据 H4字节或 K4字节， 检测出各个容器的级联顺序号 SQ, 对容器的级联 顺序号 SQ的检测方式为： 如杲出现连续三个相同的级联顺序号，则确认该级联 顺序号是该容器的级联顺序号。
当级联复帧检测电路 1判别级联复帧序列号 MFI的锁定状态时， 如果是低 阶容器，则检测 K4开销中的复帧定界序列 MFAS,如杲检测到 MFAS序列的图案， 再进一步检测 K4开销的 bit2中的级联复帧序列号 MFI是否连续， 如果连续则 表示级联复帧序列号 MFI锁定； 如果不连续， 则表示该容器中 SDH帧的级联复 帧序列号 MFI没有被锁定。 如果连续 64个 K4开销中都没有检测到 MFAS序列， 则认为 K4开销的图案不正确，表示该容器的级联复帧序列号 MFI没有锁定。 图 6和图 7分别给出了 K4开销中 bitl和 bi t2的传送图案， 其中图 6的 MFAS为 11位的固定图案 "01111111110", 图 7的 Frame count是当前容器的级联复帧 序列号 MFI , Sequence indicator表示级联组内容器的顺序号 SQ。
如果是高阶容器， 则检测 H4字节中的级联复帧序列号 MFI , 如表 1所示。 H4 字节是用于传送級联有关的信息， 其中级联复帧序列号 MFI 包括 MFI2 和 MFI1 , 是一个 12位的计数器， 该计数器的值就是容器的级联复帧序列号 MFI , 级联复帧序列号 MFI相同的容器是级联在一起的。 级联顺序号 SQ即 Sequence indicator, 指示了级联组内每个容器的顺序号，在检测时， 如果连续三帧的级 联复帧序列号不连续， 则认为级联复帧序列号 MFI没有锁定； 如果连续三帧的 级联复帧序列号都连续， 则表示级联复帧序列号 MFI锁定。
如果任何一个容器出现异常指示信号 AIS或者级联复幀序列号 MFI没有锁 定， 都认为整个级联组的级联复帧序列号 MFI没有锁定， 级联复帧序列号 MFI 的锁定信号用 latch— ind表示， 高电平表示锁定。 表 1
H4字节 1st 2nd
multi-fra multi-frame
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
me number number 1 multi-frame indicator
MFIl 第一复帧序列号 (bits
1-4) 级联顺序号 Sequence indicator MSB 1 1 1 0 14 n-1 ( its 1-4) 级联顺序号 Sequence indicator LSB 1 1 1 1 15
( bits 5-8)
2nd multi-frame indicator MFI2 MSB 0 0 0 0 0 n
( bits 1-4)
2nd multi-frame indicator MFI2 LSB 0 0 0 1 1
( its 5-8)
Reserved ("0000") 0 0 1 0 2
Reserved ("0000") 0 0 1 1 3
Reserved ("0000") 0 1 0 0 4
Reserved ("0000") 0 1 0 1 5
Reserved ("0000") 0 1 1 0 6
Reserved ("0000") 0 1 1 1 7
Reserved ("0000") 1 0 0 0 8
Reserved ("0000") 1 0 0 1 9
Reserved ("0000") 1 0 1 0 10
Reserved ("0000") 1 0 1 1 11 H4字节 1st 2nd
multi-fra multi-frame
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
me number number
1st multi-frame indicator
MFI1 第一复帧序列号 (bits
1-4)
Reserved ("0000") 1 1 0 0 12
Reserved ("0000") 1 1 0 1 13
Sequence indicator SQ MSB ( bits 1 1 1 0 14
1-4)
Sequence indicator SQ LSB ( bits 1 1 1 1 15
5-8)
2nd multi-frame indicator MFI2 MSB 0 0 0 0 0 n+1
( its 1-4)
2nd raulti-f rame indicator MFI2 LSB 0 0 0 1 1
( bits 5-8) 级联复帧检测电路 1将数据信号 Data、容器的级联顺序号 SQ、级联复帧序 列号 MFI、 级联复帧序列号锁定信号 latch_ind以及告警信号 Conca_Ais输出 到级联顺序自动调整电路 2中。
级联组内各个審器之间有着严格的顺序约定， 由于传输中各个容器的路径 差异， 在发送端按照顺序发送的级联组内不同的容器， 在到达接收端时， 其顺 序可能发生变化。 级联顺序自动调整电路 2根据各个容器在級联组内的级联顺 序号 SQ, 调整容器的顺序， 使其和发送端的顺序一致。 对于 C- 4的容器， 级联 顺序自动调整电路 2采用空分交叉矩阵，根据容器的级联顺序号 SQ按指定的顺 序输出调整后的容器的级联顺序号， 如按从小到大的顺序排序输出。 对于 C-3、 C-12或者 C- 11等其他类型的容器， 级联顺序自动调整电路 2采用时分交叉矩 阵，根据容器的级联顺序号 SQ按顺序输出调整后的容器的级联顺序号，如按从 小到大的顺序排序输出。
交叉矩阵的配置可以采用两种方式： 程序配置和自动配置； 程序配置是通 过微控制单元（Micro Control Uni t , 简称 MCU )提取各个容器的级联顺序号 SQ, 再进行交叉程序计算的配置方式； 自动配置是采用硬件电路直接根据级联 顺序号 SQ实现交叉矩阵的配置。 配置的信息是将不同容器的级联顺序号 SQ按 从小到大的顺序进行排序。
级联顺序自动调整电路 2将调整后的容器的级联顺序号 S (！、级联复帧序列 号 MFI以及数据信号 Data输出到写控制电路 4中。
写控制电路 4根据不同容器和容器当前的级联复帧序列号 MFI， 将调整好 顺序的容器数据写入緩存区 3的对应分区。 写入地址的格式为（SQ, MFI , 偏移 量）， 每写入一个字节的数据， 偏移量就增加 1 , 当达到容器的最大值时， 偏移 量复位。 容量的最大值根据容器种类不同而不同， 等于该类型容器按字节计算 的大小。
緩存区 3按照容器和级联复帧序列号 MFI进行分区， 由于同一级联组中各 个容器的传输路径可以不一致，在发送端同时发送的不同容器到达接收端口时， 其路径延时也会不一致， 因此在接收端， 为了恢复级联的数据， 需要有緩存区 3,用于緩存级联的数据中先到达的数据，等级联的数据都到齐了，再恢复数据。 缓存区 3可实行两级分区， 一级分区是按照容器分区， 即不同容器的数据存储 到不同的分区中； 二级分区是按照级联复帧序列号 MFI进行分区。 相同级联复 帧序列号 MFI的容器数据在不同的容器緩存区中的基地址一致。
由于 SDH网络并不一定工作在同步状态， 即发送端和接收端工作的时钟基 准并不一致， 为了适应这种不一致， SDH 网络中引入了指针来调整容器的频率 和相位。 由于存在指针调整， 使得到达接收端的各个容器的相对相位关系一直 在变化， 因此本发明采用读控制重定位和自适应电路 5来调整容器的频率和相 位， 并检测传输链路的状态， 当级联组内的每一个容器都从异常中恢复后， 重 新判断緩存区的读取起始地址， 从而使得级联的数据输出延时尽可能小。
如图 5所示， 读控制重定位和自适应电路 5的输入信号包括： 写控制电路 4输出的每个容器当前写地址 Addr、读控制电路 6输出的当前读地址 r_Addr、 级联顺序自动调整电路 2输出的级联复帧序列号的锁定信号 latch- ind和告警 信号 Conca— Ai s ; 输出信号包括： 调整信号 Adjus t [1: 0]、读指针初始化指示信 号 r—Addr— rs t和读指针初始地址 r— Addr— int , 输出到读控制电路 6中； 调整 信号 Adjus t [1: 0]可以是正调整信号或者负调整信号。
为了准确恢复级联的数据， 读控制重定位和自适应电路 5必须不断跟踪输 入的各个容器的相位关系， 并和读出数据的相位进行比较， 判断是否需要调整 读出数据的相位。 本发明中， 读控制重定位和自适应电路 5通过状态机完成状 态的调整， 状态机有三个状态： 搜索态 search, 比较态 compare 以及调整态 adjus t , 其状态转移方式如图 8所示， 无论当前处于哪个状态， 如果出现异常， 即当告警信号 Conca— Ai s为高或级联复帧序列号锁定信号 Latch_ ind为低时， 进入搜索态 search, 搜索出级联组的初始状态， 并向读控制电路 6发送复位信 号；在比较态 compare中,比较容器的当前写地址 w_Addr和当前读地址 r_Addr , 如果上述写读地址之差超过门限值， 则转入调整态 adjus t; 在调整态 adjus t 中， 向读控制电路 6发送调整信号 Ad jus t , 并转入比较态 compare。
读控制电路 6收到读控制重定位和自适应电路 5输出的调整信号 Adjus t 后， 根据 SDH的帧结构和容器的种类， 产生每个容器的读数据允许信号 Rd_en， 将数据从緩存区 3中读出来， 读地址的格式为 （SQ, MFI , 偏移量）， 每读出一 个字节的数据， 偏移量增加 1， 当达到容器的最大值时， 偏移量复位， 从而完 成级联的恢复。 容器的最大值根据容器的种类不同而不同， 等于该类型容器按 字节计算的大小。
读控制电路 6如果收到读控制重定位和自适应电路 5发出的读指针初始化 指示信号 r— addr— rs t (即复位信号）后， 重新初始化读的起始地址。
如果接收到读控制重定位和自适应电路 5发出的调整信号 Adjus t [1: 0] , 则相应地产生调整操作。 调整操作是对级联组内的每个容器都同时做相同的调 整， 包括两种方式： 正调整和负调整。 对于低阶容器， 正调整是在每个 TU12 结构中的 V3后的一个位置停止读一个字节的数据；对于高阶容器，正调整是在 H3的位置后连续停止读三个字节的数据。对于低阶容器， 负调整是在每个 TU12 的 V3位置读一个字节的数据； 对于高阶容器， 负调整是在每个 H3位置读一个 字节的数据。
最后所应说明的是， 以上实施例仅用以说明本发明的技术方案而非限制 , 尽管参照较佳实施例对本发明进行了详细说明， 本领域的普通技术人员应当理 解， 可以对本发明的技术方案进行修改或者等同替换， 而不脱离本发明技术方 案的精神和范围， 其均应涵盖在本发明的权利要求范围当中。

Claims

权利要求书
1、 一种虛级联延时补偿恢复装置， 其特征在于， 包括级联复帧检测电路、 级联顺序自动调整电路、 缓存区、 写控制电路、 读控制重定位和自适应电路， 以及读控制电路；
所述级联复帧检测电路， 用于对 SDH帧的级联复帧序列号进行锁定检测， 对容器的级联顺序号进行检测， 将级联顺序号和级联复帧序列号输出到所述级 联顺序自动调整电路；
所述级联顺序自动调整电路， 用于根据容器的级联顺序号调整级联组内容 器的顺序， 使其与发送端的顺序一致；
所述緩存区按照容器和级联复帧序列号进行分区， 用于緩存级联的 SDH帧 中先到达的 SDH帧；
所述写控制电路， 用于依据每个容器中 SDH帧当前的级联复帧序列号， 将 调整顺序后的容器中的 SDH帧写入所述緩存区内；
所述读控制重定位和自适应电路， 用于调整容器的频率和相位；
所述读控制电路， 用于根据所述读控制重定位和自适应电路输出的信号， 从所述緩存区中读出 SDH帧， 完成级联的恢复。
2、 根据权利要求 1所述的虛级联延时补偿恢复装置， 其特征在于， 所述 级联复帧检测电路， 检测级联组内每个容器中 SDH帧的级联复帧序列号是否连 续， 如果连续， 则确定容器中 SDH帧的当前级联复帧序列号。
3、 根据权利要求 1或 2所述的虛级联延时补偿恢复装置， 其特征在于， 所述级联复帧检测电路还进行级联越界检测， 即检测级联組内不同容器中 SDH 帧的当前级联复帧序列号之间的最大差，从而判断设置的緩存区是否满足要求； 具体是： 级联复帧检测电路对每个帧进行轮询检测， 如果某个容器中 SDH帧的 当前级联复帧序列号等于平均分配给每个容器的緩存区的大小， 则记录当前级 联組内的最大级联复帧序列号和最小级联复帧序列号， 如果两者之差大于平均 分配! ^个容器的緩存区的大小， 则表示级联越界。
4、 根据权利要求 2所述的虛级联延时补偿恢复装置， 其特征在于， 所述 级联复帧检测电路检测数据信号、 K4开销位置指示信号或 H4开销位置指示信 号， 以及异常指示信号， 判别级联复帧序列号的锁定状态， 并根据 K4 字节或 H4字节， 检测各个容器的级联顺序号。
5、 根据权利要求 4所述的虛级联延时补偿恢复装置， 其特征在于， 所述 级联复帧检测电路在检测各个容器的级联顺序号时， 如果出现连续三个相同的 级联顺序号， 则确认该级联顺序号是该容器的级联顺序号。
6、 根据权利要求 4所述的虚级联延时补偿恢复装置， 其特征在于， 所述 级联复帧检测电路在判别级联复帧序列号的锁定状态时， 如果是低阶容器， 则 检测 K4开销中是否存在复帧定界序列，如果检测到复帧定界序列，则继续检测 K4字节的 bi t2中的級联复帧序列号是否连续， 如果连续则表示锁定； 如果不 连续， 则表示该容器的级联复帧序列号没有锁定； 如果连续 64个 K4字节中都 没有发现 MFAS序列， 则认为 K4字节的图案不正确， 则表示该容器的级联复帧 序列号没有锁定。
7、 根据权利要求 4所述的虚级联延时补偿恢复装置， 其特征在于， 所述 级联复帧检测电路在判别级联复帧序列号的锁定状态时， 如果是高阶容器， 则 检测 H4字节中的级联复帧序列号是否连续，如果连续三帧的级联复帧序列号不 连续, 则认为级联复帧序列号没有锁定； 如果连续三帧的级联复帧序列号都连 续， 则表示级联复帧序列号锁定。
8、 根据权利要求 4所述的虚级联延时补偿恢复装置， 其特征在于， 所述 级联复帧检测电路如果检测到任何一个容器出现异常指示信号或者级联复帧序 列号没有锁定， 则认为整个级联组的级联复帧序列号没有锁定。
9、 根据权利要求 1所述的虛级联延时补偿恢复装置， 其特征在于， 所述 级联顺序自动调整电路采用空分交叉矩阵，根据输入的 C- 4容器的级联顺序号， 按给定的顺序输出调整后的容器的级联顺序号。
10、 根据权利要求 1所述的虚级联延时补偿恢复装置，其特征在于，所述 级联顺序自动调整电路采用时分交叉矩阵，根据输入的 C-3、 C-12或 C-11容器 的级联顺序号， 按给定的顺序输出调整后的容器的级联顺序号。
11、 根据权利要求 9或 10所述的虚级联延时补偿恢复装置，其特征在于， 所述交叉矩阵采用自动配置， 即采用硬件电路直接根据级联顺序号实现交叉矩 阵的配置； 具体是： 采用开关电路， 如果整个级联组的级联复帧没有锁定， 则 复位整个开关电路， 如果进入锁定状态， 则根据级联组内容器的级联顺序号， 从小到大进行排序， 并采用排序结果控制开关电路， 完成级联自动排序功能。
12、 根据权利要求 1所述的虚级联延时补偿恢复装置，其特征在于，所述 读控制重定位和自适应电路还检测传输链路的状态， 当级联组内的每一个容器 都从异常中恢复正常后， 重新判断读取緩存区数据的起始地址。
13、 根据权利要求 1所述的虛级联延时补偿恢复装置，其特征在于，所述 读控制重定位和自适应电路通过状态机完成状态调整，所述状态机有三个状态： 搜索态、 比较态和调整态， 其状态转移方式是： 无论当前处于哪个状态， 如果 出现告警， 则进入搜索态， 搜索出级联组的初始状态， 并向读控制电路发送复 位信号， 待告警消失后转入比较态； 在比较态中比较当前容器的写地址和当前 读地址， 如果上述写读地址之差超过门限值， 则转入调整态； 调整态向读控制 电路发送调整信号， 然后转入比较态。
14、 根据权利要求 1所述的虚级联延时补偿恢复装置，其特征在于，所述 读控制电路根据 SDH帧结构和容器的种类， 产生每个容器的读数据允许信号， 读地址的格式为（级联顺序号， 级联复帧序列号， 偏移量）， 每读出一个字节的 数据， 偏移量增加 1， 当到达容器的最大值时， 偏移量复位。
15、 根据权利要求 1所述的虛级联延时补偿恢复装置，其特征在于，所述 读控制电路接收到所述读控制重定位和自适应电路发出的复位信号后， 重新初 始化读数据的起始地址。
16、 根据权利要求 1所述的虚级联延时补偿恢复装置，其特征在于，所述 读控制电路接收到所述读控制重定位和自适应电路发出的调整信号后产生调整 操作， 包括两种调整方式： 正调整和负调整； 对于低阶容器， 所述正调整是指 在每个 TU12结构中的 V3后的一个位置停止读一个字节的数据； 所述的负调整 是指在每个 TU12结构中的 V3位置读一个字节的数据； 而对于高阶容器， 所述 正调整是指在 H3的位置后连续停止读三个字节的数据；所述负调整是指在每个 H3位置读一个字节的数据。
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