WO2004097925A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- WO2004097925A1 WO2004097925A1 PCT/JP2004/006213 JP2004006213W WO2004097925A1 WO 2004097925 A1 WO2004097925 A1 WO 2004097925A1 JP 2004006213 W JP2004006213 W JP 2004006213W WO 2004097925 A1 WO2004097925 A1 WO 2004097925A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 306
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 152
- 239000012298 atmosphere Substances 0.000 claims abstract description 75
- 238000000137 annealing Methods 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 239000007789 gas Substances 0.000 claims abstract description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 239000001301 oxygen Substances 0.000 claims description 24
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- 230000008569 process Effects 0.000 claims description 17
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- 239000011261 inert gas Substances 0.000 claims description 5
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- 229910052796 boron Inorganic materials 0.000 abstract description 16
- 238000009826 distribution Methods 0.000 abstract description 13
- 230000007423 decrease Effects 0.000 abstract description 11
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 72
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 29
- 229910052710 silicon Inorganic materials 0.000 description 29
- 239000010703 silicon Substances 0.000 description 29
- 229910052814 silicon oxide Inorganic materials 0.000 description 29
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- 239000010410 layer Substances 0.000 description 18
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- 238000005259 measurement Methods 0.000 description 10
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- 238000010438 heat treatment Methods 0.000 description 9
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- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Definitions
- the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a gate insulating film containing nitrogen.
- It is a component for improving the degree of integration and operating speed of semiconductor integrated circuit devices.
- the MOS FET is miniaturized, and the gate insulation J3 area is thinned.
- the gate electrode formed on the gate insulating film is usually formed by a polysilicon layer or a stack of a polysilicon layer and a silicide layer.
- the polysilicon layer is usually ion-implanted with impurities simultaneously with the source Z drain region.
- An n-type impurity is ion-implanted into the gate electrode and the source Z drain region of the surface channel type n-channel MOSFET.
- P-type impurities are ion-implanted into the gate electrode and the source Z drain region of the surface channel type p-channel MOS FET.
- Suppress current Can be Silicon nitride oxide generally has a higher dielectric constant than silicon oxide, and is effective in increasing the physical film thickness while suppressing the inversion capacity equivalent film thickness.
- Japanese Unexamined Patent Application Publication No. 2002-1980531 discloses that nitrogen is introduced into a silicon oxide gate insulating film formed on a silicon substrate by remote plasma nitridation, and then 800 ° C. to 110 ° C. It has been proposed that a gate insulating film having a uniform nitrogen concentration be formed by redistributing nitrogen by annealing the gate insulating film in a N 2 atmosphere at ° C. It is stated that by forming a gate insulating film having a uniform nitrogen concentration of 6 at% or more, for example, 8 at% or 10 at%, a long-lasting and highly reliable transistor can be obtained.
- remote plasma nitridation is a process in which nitrogen plasma is generated by a microphone mouth wave or the like in a plasma generation chamber separate from the processing chamber containing the substrate, and active nitrogen is transported to the processing chamber to perform nitriding. .
- Japanese Patent Application Laid-Open No. 2002-1107674 discloses that when nitrogen enters the vicinity of the interface on the Si substrate side, the mobility in the MO line> ⁇ evening decreases, so that the nitrogen concentration near the Si substrate interface is reduced. It is proposed to introduce more nitrogen into the film surface side to reduce the gate leakage current.
- the silicon oxynitride film to which nitrogen has been introduced in advance to radical nitridation using nitrogen gas, the nitrogen flow diffused from the surface is suppressed, and the amount of nitrogen introduced near the silicon substrate interface is suppressed, and the film surface Proposes to increase the nitrogen concentration of Disclosure of the invention
- An object of the present invention is to provide a method for manufacturing a semiconductor device having a thin gate insulating film and having excellent MOSFET performance.
- Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing penetration of boron ion-implanted into a gate electrode into a gate insulating film and suppressing a decrease in mobility of a channel region. It is to be.
- a gate insulating layer is formed on an active region of a semiconductor substrate.
- 1A to 1F are a cross-sectional view and a graph for explaining an experiment conducted by the inventor and the result thereof.
- FIGS. 2A to 2D are a cross-sectional view and a graph for explaining an experiment conducted by the inventor and a result of the experiment.
- 3A and 3B are tables and graphs showing the conditions and results of still other experiments performed by the present inventors.
- FIGS. 4A and 4B are tables and graphs showing the conditions and results of still other experiments performed by the present inventors.
- FIGS. 5A to 5D are cross-sectional views of a semiconductor substrate for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
- F-I-G ⁇ r-6- ⁇ -6B is a table and a graph showing the results and results of still another experiment conducted by the present inventors.
- 7A, 7B, and 7C are cross-sectional views schematically showing the configuration of a remote plasma nitridation device, a decoupled RF nitrogen plasma device, and the configuration of a gate insulating layer using an 8-k material. It is sectional drawing shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- Introducing nitrogen into the silicon oxide film is effective in preventing boron from penetrating through the gate insulating film during boron ion implantation into the gate electrode.
- the thickness of the gate insulating film becomes thinner, it becomes more difficult to prevent the penetration of boron, and boron reaches the interface between the gate insulating layer J and the silicon substrate. Mobility is reduced when boron reaches the channel region.
- the boron concentration at the interface tends to be non-uniform.
- the dielectric constant of the insulating film can be increased.
- Increasing the physical film thickness while keeping the inversion capacitance equivalent film thickness (Te ff) small is effective in suppressing gate leakage current.
- the NBT I characteristic is the deterioration characteristic when the temperature is increased by applying stress.
- the technique of generating nitrogen plasma at a location away from the substrate and introducing active nitrogen into the substrate is said to be a damage-free process that does not damage the substrate.
- the present inventor has found that even if active nitrogen generated by plasma is introduced into the insulating film of a silicon substrate placed away from the plasma, the substrate may be damaged in some way. Denier treatment at higher temperature than nitrogen introduction process would be effective in recovering this damage, so the effect of anneal treatment was investigated.
- FIGS. 1A to 1E are cross-sectional views showing steps of preparing a sample of an experiment performed by the present inventors.
- a gate oxide film 5 having a thickness of 1. Onm was formed on the surface of the active region 4 of the silicon substrate 1 in an oxygen atmosphere at 965 ° C.
- a nitrogen pump excited by a 1.5 kW microwave Nitrogen was introduced into the gate insulating film 5 in an atmosphere of 450 ° C. using active nitrogen derived from plasma. Nitrogen is introduced into the surface of the silicon oxide film to form a silicon nitride oxide film 5X.
- the active nitrogen was introduced using a remote plasma nitridation device available from Applied Materials, Inc. of Santa Clara, California, USA.
- FI G. 7 A schematically shows the configuration of a remote plasma nitriding device.
- N 2 gas is introduced into plasma generation chamber 21 to generate nitrogen plasma.
- Activated nitrogen (radical) is generated from nitrogen plasma.
- the reaction chamber 2 is provided with a lamp heating device 23 including a large number of lamps, and can heat the wafer 24.
- an annealing treatment was performed in a nitrogen atmosphere at 1050 ° C. to recover damage to the substrate caused by the introduction of active nitrogen.
- the silicon oxynitride film 5X becomes a silicon oxynitride film 5y by annealing.
- a 100-nm-thick polycrystalline silicon layer is deposited on the gate insulating film by CVD and patterned using a resist pattern, resulting in a gate length of 0.5 m to 1.0 m.
- the gate electrode 6 of the degree was formed.
- the gate insulating film 5y was also patterned to form a gate insulating film 5z.
- B which is a P-type impurity
- a silicon oxide film with a thickness of about 6 Onm is deposited on the substrate by chemical vapor deposition (CVD) to cover the gate electrode, and reactive ion etching is performed to remove the silicon oxide film on the flat surface
- CVD chemical vapor deposition
- p-type impurities B were further ion-implanted to form a high-concentration source / drain region 9.
- the p-type impurity B is also ion-implanted into the gate electrode 6.
- an interlayer insulating film was formed, an opening for exposing the source drain region and the gate electrode was formed, and an electrode was formed.
- sample S1 was obtained.
- FIG. IF is a graph showing the characteristics of the two types of created MOS FETs.
- the horizontal axis represents Vg_Vth obtained by subtracting the threshold value Vth from the gate voltage Vg in units of V.
- the vertical axis indicates the normalized mutual conductance obtained by multiplying the transconductance Gm by the inversion capacitance equivalent film thickness Te ff and further multiplying the ratio WZL of the width W and the length L of the channel region by the unit m SXnm.
- the transconductance is normalized regardless of the thickness of the gate insulating film and the size of the channel region.
- the characteristic s1 of sample S1 that was annealed at 1050 ° C in a nitrogen atmosphere after the introduction of active nitrogen was almost the same as the characteristic s2 of sample S2 that was not annealed in a nitrogen atmosphere. It shows higher transconductance. It is clear that annealing has improved the characteristics of the MOSFET. It is considered that the carrier mobility was improved and the saturation current was improved.
- a nitriding process similar to the process shown in FIG. 1C was performed at a substrate temperature of 550 ° C.
- the thickness of the gate insulating film was 1.457 nm as measured by an ellipsometer.
- the third sample S3 was annealed at 1050 ° C. in a nitrogen atmosphere after introducing nitrogen.
- This annealing treatment is an annealing treatment in an inert gas.
- the fourth sample S4 was annealed at 950 ° C. in a NO atmosphere after introducing nitrogen.
- This annealing treatment is an annealing treatment involving oxidation and nitridation.
- an annealing treatment at 1050 ° C was performed in a nitrogen atmosphere.
- the thickness of the gate insulating film measured by ellipsometry overnight was 1.538. nm.
- the fourth sample has additional annealing in NO.
- the film thickness increased by annealing in NO was 0.081 nm.
- each annealing process is performed by rapid thermal annealing RTA, and is very short. After that, an insulated gate electrode and a source Z drain region were formed as in the first and second samples.
- FIG. 2D is a graph showing the characteristics of the third, fourth, and fifth samples created.
- the horizontal axis and the vertical axis are the same as in FIG. 1F.
- the properties s4 of ⁇ ⁇ treated with 950 ° C (nitridation, oxidation) annealing in NO atmosphere showed a clear improvement.
- the characteristic s5 of sample S5 which was subjected to (oxidation) annealing at 1000 ° C. in an oxygen atmosphere after the introduction of active nitrogen was a characteristic intermediate between the two.
- Si—O—N silicon-oxygen-nitrogen
- annealing in an oxidizing or nitridizing atmosphere causes oxidation or nitridation of the substrate, and the gate insulating film becomes thicker.
- Effective gate insulating film thickness 2 nm or less In the case of forming a film, an annealing treatment in a NO atmosphere with a small increase in film thickness would be more preferable.
- the increase in the insulating film thickness due to the annealing treatment in the NO gas atmosphere is preferably set to 0.2 nm or less.
- the initial oxide film thickness is preferably 1.5 nm or less.
- TDDB time dependent dielectric breakdown
- the sample of (2) has almost the same nitrogen distribution in the insulating film as the sample of (1), but the effect on reliability is large.
- the reason for this is that the silicon-oxygen-nitrogen (Si-0-N) bond is efficiently formed near the interface on the substrate side by the heat treatment in the NO atmosphere after the active nitrogen introduction treatment. Is thinking. Note that performing annealing in a N 2 gas atmosphere at a higher temperature after annealing in a NO gas atmosphere is merely an essential step to improve the NBT I characteristics.
- a remote plasma nitriding apparatus and a decoupled RF nitrogen plasma apparatus available from Applied Materials, Inc. of Sanyo Clara, California are also known.
- FI G. 7 B schematically illustrates the configuration of a decoupled RF nitrogen plasma device.
- nitrogen plasma is generated by RF excitation of a coil 26 provided on the top of a reaction chamber 25 containing a sample 27 at the bottom. Nitrogen plasma is generated only in the region along the upper wall of the reaction chamber, away from sample 27. This device is abbreviated as DPN below.
- Two types of samples were formed using a DPN nitriding apparatus.
- FIG.3A shows conditions for preparing two types of samples S6 and S7 and a sample S8 for comparison.
- a silicon oxide film having a thickness of 0.85 nm was formed by a lamp annealing apparatus in an oxygen atmosphere at 900 ° C. After that, nitrogen plasma was excited with RF power of 700 W in the DPN device, and active nitrogen was introduced into the silicon oxide film of the substrate placed below in a room temperature atmosphere.
- annealing treatment (RT ⁇ ) was performed in a reduced-pressure oxygen atmosphere at 1000 ° C, and then an annealing treatment in a nitrogen atmosphere at 1050 ° C (RT ⁇ ). RTA).
- RTNO nitric oxide
- RTA Processing
- FIG. 3B shows the measurement results of these samples.
- the abscissa indicates the inversion capacitance-converted film thickness T eff in nm, and the ordinate indicates the gate leak current Ig in units (A / cm 2 ).
- the characteristic s8 of the sample in which the gate insulating film was formed only of the silicon oxide film was the two points indicated by the X marks, and became a straight line outside.
- the characteristic s6 of the sixth sample S6 is lower than the characteristic s8 of the comparative sample S8, indicating that the gate leak current can be reduced.
- the measurement point s7 of the seventh sample S7 is a nitriding oxide treatment in N ⁇ , oxidation is suppressed, and the effective gate insulating film thickness is smaller than the measurement point s6. It also exists below the characteristic s8, indicating that the gate leakage current can be reduced as in the case of the sample S6.
- the degree of reduction of gate leakage current is Le S 6 and S 7 are almost the same.
- the effective gate insulating film thickness is reduced by 0.0113 nm.
- the transconductance Gm is excellent, and as a characteristic of the semiconductor device, the saturation current can be improved by 3.6% in the MOS transistor having a gate length of 40 nm.
- the table in FIG. 4A schematically illustrates the steps for preparing the two types of samples.
- the ninth sample S9 was prepared by forming a 0.8-nm-thick silicon nitride film in a 900 ° C oxygen atmosphere with a lamp annealing apparatus, and using a 700 W decoupled RF nitrogen plasma at room temperature. Active nitrogen was introduced (DPN) into the gate oxide film. Thereafter, an annealing treatment RTO was performed in a reduced-pressure oxygen atmosphere at 1000 ° C., followed by an annealing treatment (RTA) in a nitrogen atmosphere at 1050 ° C.
- RTO annealing treatment
- the tenth sample S10 forms a 0.8-nm-thick silicon oxide film, introduces active nitrogen with a DPN device, and then anneales in a NO gas atmosphere at 950 ° C. Treatment (RTNO) was performed, followed by annealing (RTA) in a nitrogen atmosphere of 1 ⁇ ⁇ ⁇ ⁇ ⁇ ° ⁇ .
- RTNO Treatment
- RTA annealing
- FIG. 4B is a graph showing the measurement results of these two types of samples.
- the horizontal axis indicates the depth from the surface in units of nm, and the vertical axis indicates the measured nitrogen concentration in units (atoms / cc).
- Characteristic s9 of the sample annealed in an oxygen atmosphere has a higher peak value near the surface, and the nitrogen concentration gradually decreases with depth. Although the change in nitrogen concentration by one digit or more is shown within the measurement range, the interface between the gate insulating film and the silicon substrate exists in the middle.
- the thickness of the nitrided oxide film was 1.324 nm, the peak of the nitrogen concentration was 8.6 at%, and the nitrogen concentration at the interface with the substrate was 3.6 at%.
- the nitrogen concentration at the interface is 1Z2 or less of the peak nitrogen concentration.
- the characteristic s10 of sample S10 which was annealed in a NO atmosphere after the introduction of active nitrogen, shows that the peaks on the surface side seem to spread somewhat flat. It should include the nitrogen distribution due to the introduction and the nitrogen distribution due to the annealing treatment in the NO atmosphere. After that, it shows a tendency to decrease with depth while showing a nitrogen concentration slightly higher than that of characteristic s9, and the distribution is almost the same as that of characteristic s9 from a certain depth.
- the thickness of the nitrided oxide film was 1.174 nm
- the peak of the nitrogen concentration was 7.6 at%
- the nitrogen concentration at the interface with the substrate was 4.9 at%.
- the nitrogen concentration has a peak on the surface side of the gate insulating film, and decreases with depth toward the interface with the silicon substrate. Therefore, by introducing a large amount of nitrogen into the gate insulating film, boron penetration can be effectively suppressed, and the nitrogen concentration at the interface with the silicon substrate is suppressed to preferably 5 at% or less, and the It can be seen that a decrease in mobility can be suppressed.
- the experiment was performed under the condition that the excitation energy of the decoupled RF plasma was reduced from 700 W to 500 W, expecting that active nitrogen was introduced only near the surface of the silicon oxide film.
- the table in FIG. 6A schematically shows the steps for preparing three types of samples.
- the first sample S11 was prepared by forming a 0.8 nm thick silicon oxide film in a 900 ° C. oxygen atmosphere by a lamp annealing apparatus, and then using a 500 W decoupled RF nitrogen plasma. Active nitrogen was introduced (DPN) into the gate oxide film at room temperature without bias electric field. Thereafter, an annealing treatment (RTO) was performed in a reduced-pressure oxygen atmosphere at 1000 ° C., and subsequently, an annealing treatment (RTA) was performed in a nitrogen atmosphere at 150 ° C.
- RTO annealing treatment
- RTA annealing treatment
- the first sample S12 was formed by forming a 0.8-nm-thick silicon oxide film in a 900 ° C. oxygen atmosphere with a lamp annealing apparatus. Active nitrogen was introduced (DPN) into the gate oxide film at room temperature using 0 W decoupled RF nitrogen plasma. Thereafter, an annealing treatment (RTNO) was performed in a reduced-pressure NO atmosphere at 950 ° C, followed by an annealing treatment (RTA) in a nitrogen atmosphere at 1050 ° C.
- DPN active nitrogen
- RTNO annealing treatment
- RTA annealing treatment
- the thirteenth sample S13 was prepared by forming a 0.8-nm-thick silicon oxide film using a lamp annealing apparatus in an oxygen atmosphere at 900 ° C, and using a 500 W decoupled RF nitrogen plasma. Activated nitrogen was introduced (DPN) into the gate oxide film at room temperature.
- an annealing process RTO
- RTNO annealing process
- RTAA annealing process
- Performing RTA at a higher temperature after annealing in a NO atmosphere is for improving NBTI characteristics and is not an essential step.
- FIG. 6B is a graph showing the measurement results of these three types of samples.
- the horizontal axis indicates the depth from the surface in units of nm, and the vertical axis indicates the measured nitrogen concentration.
- the characteristic s11 of the eleventh sample S11 subjected to the annealing treatment in the oxygen atmosphere has a higher peak value near the surface, and the nitrogen concentration gradually decreases with the depth. It shows a change in nitrogen concentration of one digit or more within the measurement range.
- the interface between the gate insulating film and the silicon substrate exists on the way.
- the thickness of the nitrided oxide film was 1.189 nm, the peak of the nitrogen concentration was 7.5 at%, and the nitrogen concentration at the interface with the substrate was 2.2 a.
- the nitrogen concentration at the interface is 12 or less of the peak nitrogen concentration.
- the characteristic s12 of the twelfth sample S12 that was annealed in an NO atmosphere after the introduction of active nitrogen has a slightly increased peak near the surface and spreads. Thereafter, while showing a slightly higher nitrogen concentration than characteristic S11, it tends to decrease with depth, but the nitrogen amount increases as it approaches the interface, with two peaks at the surface and near the interface. Shows a typical distribution. Annealing in a NO atmosphere seems to tend to introduce nitrogen near the interface with the substrate.
- the thickness of the nitrided oxide film is 1.170 nm, the nitrogen concentration peak is 7.8 at%, and the substrate is The nitrogen concentration at the interface with was 4.8 at%.
- the thickness of the nitrided oxide film was 1.157 nm, the peak of the nitrogen concentration was 7.4 at%, and the nitrogen concentration at the interface with the substrate was 2.4 at%.
- FIGS. 5A to 5D are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention based on the above experimental results.
- an element isolation region 3 is formed on a silicon substrate 1 by STI. Desired ion implantation is performed in the active region defined by the STI element isolation region to form an n-type well 4n and a p-type well 4p. Although only two wells are shown, a plurality of wells are formed at the same time.
- the exposed silicon substrate surface is subjected to pyrogenic oxidation at 800 ° C. to form a silicon oxide film 11 having a thickness of 7 nm.
- Pyrojek Sidani is a method of performing Sidani in an atmosphere in which hydrogen is burned in oxygen.
- the gate oxide film with a thickness of 7 nm is a gate insulating film for fabricating a MOS FET with an operating voltage of about 3 V.
- the grown silicon oxide film 11 is removed by etching in an active region where a MOS FET for operating at a low voltage is formed. Dry oxidation is performed in an oxygen atmosphere at 965 ° C. to form a silicon oxide film 12 having a thickness of 1.2 nm.
- the 1.2-nm-thick gate oxide film is used as a gate insulating film to fabricate a MOSFET with an operating voltage of about 1 to 1.2 V, for example.
- the natural oxide film may be removed in a reducing atmosphere such as a hydrogen radical. By oxidizing a clean silicon surface, a high-quality silicon oxide film can be formed.
- the gate insulating layers having two kinds of thicknesses are formed has been described, the gate insulating layers having three or more kinds of thicknesses may be formed.
- the thick silicon oxide film 11 formed earlier also grows slightly.
- the well having the thin gate insulating film 12 also has n-type and p-type.
- active nitrogen is introduced into the gate insulating films 11 and 12 in an atmosphere of 550 ° C. by RPN nitrogen plasma obtained by a 1.5 kW microwave. After the active nitrogen is introduced, the gate insulating films become silicon nitride oxide films 11x and 12x.
- anneal in 950 ° C N2 gas atmosphere As shown in Fig. 5C, anneal in 950 ° C N2 gas atmosphere.
- the gate insulating film is further oxynitrided by N ⁇ GaN, and the damage is recovered. ⁇ -In this way, a gate insulating film lly, 12y is formed. Subsequently, annealing at a higher temperature may be performed in a nitrogen atmosphere in order to suppress deterioration of the NBT I characteristics.
- a polycrystalline silicon layer having a thickness of 100 nm is formed on the gate insulating film, and is patterned to a desired gate length using a resist pattern.
- a gate electrode having a gate length of 40 nm is formed on the thin gate insulating film 12y.
- ion implantation of n-type impurities and p-type impurities is performed using the patterned gate electrode and a resist mask for selecting the n-channel region and the p-channel region, and the extension regions 7p and 7n are formed.
- a silicon oxide film having a thickness of about 6 Onm is deposited, and RIE is performed to form a sidewall spacer 8.
- P-type impurities are ion-implanted to form source / drain regions 9 n and 9 p.
- the exposed silicon surface is silicided and covered with an interlayer insulating film. An opening is formed in the interlayer insulating film 2, a lead plug is formed, and necessary wiring and an interlayer insulating film are formed.
- CMOS integrated circuit having a thin gate insulating layer and a thick gate insulating layer, suppressing the penetration of boron even in the thin gate insulating layer, and suppressing the decrease in the mobility of the channel region is formed.
- a semiconductor device having a thin effective gate insulating film thickness of 2 nm or less, particularly 1.7 nm or less, capable of preventing boron penetration and suppressing a reduction in channel region mobility can be obtained. It is formed.
- a high nitrogen concentration is introduced into the gate insulating film on the surface side and a low nitrogen concentration is introduced at the interface with the silicon substrate, thereby suppressing the penetration of boron into the gate insulating film, Mobility reduction in the region can be suppressed.
- anneal in oxynitride in NO may be replaced with anneal in NO diluted with an inert gas.
- a silicon oxide film as a color film formed first on a semiconductor substrate
- a silicon nitride oxide film containing 3 at% or less of nitrogen at an interface with the substrate may be formed.
- a high-k material film having a high dielectric constant may be stacked over the silicon nitride oxide film.
- FIG. 7C shows a configuration in which films of hi gh_k (high dielectric constant) material are stacked.
- the hi 81-1 ⁇ material has a significantly higher dielectric constant than silicon oxide.
- a 0.58-nm-thick silicon oxide film 31 is formed on a surface of a silicon substrate 30 in an oxygen atmosphere at 750 ° C by a lamp annealing apparatus, and a gate oxide film is formed at room temperature by a 500 W decoupled RF nitrogen plasma. Active nitrogen was introduced into the reactor (DP N). After that, an annealing treatment (RTNO) was performed in a 900 ° C NO gas atmosphere, and further an annealing treatment (RTA) was performed in a 1050 ° C nitrogen atmosphere.
- RTNO annealing treatment
- RTA annealing treatment
- this nitrided oxide film was 0.80 nm. By adjusting the thickness of the underlying oxide film, plasma nitriding strength, NO gas annealing temperature, time, etc., it will be possible to further reduce the thickness.
- oxide films such as A1, Hf, Zr, and their silicate oxide films
- a high-k material film 32 such as that described above, a reaction between the semiconductor substrate and the high-k material can be prevented, and a gate insulating film having excellent reliability and driving ability can be provided.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims
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JP2005505936A JP5121142B2 (ja) | 2003-04-30 | 2004-04-28 | 半導体装置の製造方法 |
US11/107,781 US7514376B2 (en) | 2003-04-30 | 2005-04-18 | Manufacture of semiconductor device having nitridized insulating film |
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PCT/JP2003/005561 WO2004097922A1 (ja) | 2003-04-30 | 2003-04-30 | 半導体装置の製造方法 |
JPPCT/JP03/05561 | 2003-04-30 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006066503A (ja) * | 2004-08-25 | 2006-03-09 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2006203038A (ja) * | 2005-01-21 | 2006-08-03 | Fujitsu Ltd | 窒化膜の形成方法、半導体装置の製造方法、キャパシタの製造方法及び窒化膜形成装置 |
JP2008539592A (ja) * | 2005-04-29 | 2008-11-13 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | ブロッキング特性の異なるゲート絶縁膜を備えた半導体デバイス |
JP2009152390A (ja) * | 2007-12-20 | 2009-07-09 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法 |
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CN102456732B (zh) * | 2010-10-19 | 2014-10-08 | 格科微电子(上海)有限公司 | Mos晶体管及其制造方法、cmos图像传感器 |
CN110233095B (zh) * | 2018-03-05 | 2021-11-23 | 中芯国际集成电路制造(上海)有限公司 | 栅介质层、场效应管的制造方法及场效应管器件 |
TW202129061A (zh) * | 2019-10-02 | 2021-08-01 | 美商應用材料股份有限公司 | 環繞式閘極輸入/輸出工程 |
CN116031141A (zh) * | 2022-12-25 | 2023-04-28 | 北京屹唐半导体科技股份有限公司 | 工件处理方法、工件处理设备及半导体器件 |
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JP2000228522A (ja) * | 1999-02-08 | 2000-08-15 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2001093903A (ja) * | 1999-09-24 | 2001-04-06 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002222941A (ja) * | 2001-01-24 | 2002-08-09 | Sony Corp | Mis型半導体装置及びその製造方法 |
JP2004023008A (ja) * | 2002-06-20 | 2004-01-22 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
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US6933248B2 (en) * | 2000-10-19 | 2005-08-23 | Texas Instruments Incorporated | Method for transistor gate dielectric layer with uniform nitrogen concentration |
JP2002151684A (ja) * | 2000-11-09 | 2002-05-24 | Nec Corp | 半導体装置及びその製造方法 |
JP2003133550A (ja) * | 2001-07-18 | 2003-05-09 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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JP2000228522A (ja) * | 1999-02-08 | 2000-08-15 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2001093903A (ja) * | 1999-09-24 | 2001-04-06 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002222941A (ja) * | 2001-01-24 | 2002-08-09 | Sony Corp | Mis型半導体装置及びその製造方法 |
JP2004023008A (ja) * | 2002-06-20 | 2004-01-22 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006066503A (ja) * | 2004-08-25 | 2006-03-09 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2006203038A (ja) * | 2005-01-21 | 2006-08-03 | Fujitsu Ltd | 窒化膜の形成方法、半導体装置の製造方法、キャパシタの製造方法及び窒化膜形成装置 |
US7696107B2 (en) | 2005-01-21 | 2010-04-13 | Fujitsu Microelectronics Limited | Nitride film forming method, semiconductor device fabrication method, capacitor fabrication method and nitride film forming apparatus |
JP4554378B2 (ja) * | 2005-01-21 | 2010-09-29 | 富士通セミコンダクター株式会社 | 窒化膜の形成方法、半導体装置の製造方法及びキャパシタの製造方法 |
US7951727B2 (en) | 2005-01-21 | 2011-05-31 | Fujitsu Semiconductor Limited | Capacitor fabrication method |
JP2008539592A (ja) * | 2005-04-29 | 2008-11-13 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | ブロッキング特性の異なるゲート絶縁膜を備えた半導体デバイス |
JP2009152390A (ja) * | 2007-12-20 | 2009-07-09 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法 |
Also Published As
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WO2004097922A1 (ja) | 2004-11-11 |
CN1701426A (zh) | 2005-11-23 |
KR100627219B1 (ko) | 2006-09-25 |
CN100487877C (zh) | 2009-05-13 |
KR20060004649A (ko) | 2006-01-12 |
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