Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
  • H03K3/356—Bistable circuits
  • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Definitions

• This invention relates to a trigger circuit with hysteresis and a CMOS integrated circuit comprising such a trigger with hysteresis.
• the invention relates to a new inverter circuit with hysteresis, particularly a new Schmitt trigger circuit and a CMOS integrated circuit comprising such an inverter with hysteresis.
• the invention proposes an integrated circuit adapted to any CMOS semiconductor on insulator technology.
• the preferred CMOS semiconductor on insulator technology in this case is the Partially Depleted Silicon On Insulator (PD SOI) technology.
• FIG. 1 illustrates one of several possible symmetric implementations of such a Schmitt trigger circuit.
• the circuit in Figure 1 comprises six transistors: transistors N2 and P2 forming the main inverter of the Schmitt trigger, while firstly transistors Nl and N3 , and secondly transistors PI and P3 form two retroaction networks.
• Each of the said two retroaction networks fixes a trigger threshold and the two thresholds thus obtained consequently induce a hysteresis effect (the hysteresis value being fixed by the voltage difference between these two thresholds) . Therefore, the Schmitt trigger is switched over at different values of the said input voltage, depending on the direction of change of the input voltage.
• This type of circuit is shown in Figure 2.
• This scheme includes three N-channel junction field effect transistors (NFET) and three P-channel junction field effect transistors (PFET) for which the substrates are fixed to the power supply potentials. This is achieved by connecting the substrate connectors of PFET transistors to the power supply voltage, while the substrate connectors of NFET transistors are connected to the ground.
• the threshold voltages of transistors are thus fixed in time, independently of the input signal and its history, which overcomes the history effect problem but slows down the device .
• this trigger is much less efficient when the power supply voltage is approximately equal to the value of the transistor threshold voltage. Consequently, use of this circuit is limited due to its degraded operation at a low power supply voltage, which takes place at the detriment of the speed and / or the silicon surface area.
• the purpose of the invention is to be able to use a Schmitt trigger circuit that takes advantage of the SOI technology and is effective particularly at a low power supply voltage.
• Document US 5,608,344 proposes an analog comparator circuit with hysteresis comprising in particular an input stage made up of a differential pair of P-channel FET transistors to the bodies of which are applied fixed continuous potentials, by means of switches ordered dynamically.
• This circuit does not take into account the constraints of the SOI technology (in particular history effect) .
• this circuit does not propose to control the bodies of the N-channel and P-channel complementary FET transistors of a CMOS inverter stage carrying out a hysteresis effect.
• the invention proposes a trigger circuit with hysteresis using the SOI technology, characterized in that it comprises at least two CMOS inverter stages, each inverter stage being composed of a first branch comprising at least one P-channel junction field effect transistor (PFET) in series between a first power supply potential V DD and an output node from the inverter stage, and a second branch comprising at least one- N-channel junction field effect transistor (NFET) in series between the said output node from the inverter stage and a second power supply potential, the said transistors of each inverter stage having their grids connected together to receive an input signal.
• PFET P-channel junction field effect transistor
• NFET junction field effect transistor
• each of the inverters directly or indirectly receives the input signal of the said circuit, while the output signal from the said circuit is obtained directly or indirectly from the output signal from one of the inverter stages.
• the substrate potential of each transistor of at least one inverter stage is dynamically controlled by a control signal output from the said circuit .
• the structure of the circuit as a succession of inverter stages in series between the input to the said circuit and its output, and the dynamic modification of the threshold voltage of the transistors of at least one inverter stage enable introduction of hysteresis effect based on acceleration of transistor blocking (in fact the PFET transistor (s) of the main inverter of the circuit according to the invention for a positive variation of the input voltage) rather than on delaying the starting conduction of transistor (s) (in fact the NFET transistor (s) of the main inverter of the circuit according to prior art for a positive variation of the input voltage) .
• the invention can thus provide an "improvement” (by introducing an acceleration) where the circuit according to prior art caused a “degradation” (by introducing a deceleration) to introduce an unbalance of the V. and V + threshold voltages.
• the circuit according to the invention has higher performance characteristics than the circuit according to prior art.
• the merit factor (taking account of the speed, total consumption and the silicon area) of the invention is better than the merit factor for prior art for a wide range of power supply voltages .
• the substrate potentials of PFET and NFET transistors of at least one inverter stage are controlled by the same control signal.
• the substrate potentials of the PFET and NFET transistors of the controlled inverter stage are controlled by a signal determined by a state of the circuit on the output side of the said controlled inverter stage.
• the said substrate potentials of the PFET and NFET transistors of the controlled inverter stage can consequently be controlled by the output signal from an inverter stage, called the control inverter stage located downstream on the output side of the said controlled inverter stage.
• control inverter stage is preferably separated from the controlled inverter stage by an even number of inverter stages in series between the said controlled inverter stage and the said control inverter stage.
• said control inverter stage is the inverter stage immediately on the output side of the said controlled inverter stage, and the even number of inverter stages then being equal to zero.
• the substrate potentials of the PFET transistors of at least one controlled inverter stage and the substrate potentials of the NFET transistors complementary to the said PFET transistors are all controlled by control signals that are different for each.
• each of the control signals is a signal determined by a state of the circuit on the output side of the said controlled inverter stage and this signal determined by a state of the circuit may be the output signal from an inverter stage called the control inverter stage, located on the output side of the said controlled inverter stage.
• Each control inverter stage ⁇ is preferably separated from the said controlled inverter stage by an even number (or zero) of inverter stages in series between the said controlled inverter stage and the said control stage.
• the substrate potentials of transistors in the first inverter stage are not the only potentials to be dynamically controlled.
• Substrate potentials of transistors other than the first stage can also be either connected conventionally to the power supply for PFETs or to the ground for NFETs, or they can be dynamically controlled by a state of the circuit on the output side and more particularly by the output signal from an inverter stage located on the output side.
• the different inverter stages are chained in sequence to operate in a "nested" manner, the substrate potentials of the transistors in an inverter stage other than the last inverter stage being controlled by the output signal from the inverter stage located directly on the output side and the substrate potentials of the transistors in the last inverter stage being either floating, or fixed to a power supply voltage.
• the circuit according to the invention comprises three inverter stages . The first two inverter stages are chained in series such that the output signal from the first inverter is applied to the input of the second inverter.
• the second and third inverter stages are also chained in series such that the output signal from the second inverter is applied to the input of the third inverter and to the substrates of the transistors in the first inverter stage.
• the threshold trigger circuit according to the invention advantageously performs a Schmitt Trigger function.
• figure 1 shows a conventional symmetric implementation of a Schmitt trigger circuit
• - figure 2 shows a Schmitt trigger circuit adapted to the conventional circuit in Figure 1 to be used in SOI and for which the substrate potentials of all transistors are fixed so that they are not left floating
• figure 3a diagrammatically shows the Schmitt trigger circuit according to the invention
• figure 3b more precisely shows the Schmitt trigger circuit according to the preferred embodiment of the invention
• figure 4 shows a very simplified illustration of how the circuit according to the preferred embodiment of the invention operates, and shows time diagrams for the different circuit signals during a transition of, the input signal IN from the low state to the high state
• figure 5 illustrates the fact that the transistor threshold voltages forming the core of the trigger function according to prior art as illustrated in Figure 2, are always greater than the threshold voltages of transistors forming the core of the trigger function according to the invention
• - figure 6 shows an elementary embodiment of the
• FIG. 1 shows a conventional symmetric embodiment of the CMOS Schmitt trigger circuit on a solid substrate.
• This well known circuit comprises three P-channel junction field effect transistors (PFET) PI, P2 and P3 , and three N- channel junction field effect transistors (NFET) Nl, N2 and N3.
• transistors N2 and P2 form the main inverter of the Schmitt trigger, while the two assemblies composed firstly of transistors Nl and N3 and secondly of transistors PI and P3 form two retroaction networks .
• Each of these retroaction networks fixes one threshold, and when combined the two thresholds thus obtained induce a hysteresis effect.
• the output signal OUT remains high.
• the input voltage V IN must drop below the switching threshold V. during a negative variation, to cause a new switching. Therefore finally, depending on the direction of the variation of the input voltage V IN , the Schmitt trigger is switched at different values of the said input voltage V ⁇ N .
• Schmitt trigger circuit illustrated in Figure 1 is that all substrate potentials of all transistors in the circuit are fixed so that they are not floating. Substrate connectors of P-channel junction field effect transistors (PI, P2 , P3) are connected to the power supply voltage for this purpose, while substrate connectors of N-channel junction field effect transistors (Nl, N2 , N3 ) are connected to the ground. In the context of this application of the conventional circuit to applications on SOI, substrate potentials are all imposed at fixed voltages and consequently threshold voltages are fixed in time, independently of the input signal and its history, which overcomes the history effect problem.
• PI P-channel junction field effect transistors
• Nl N-channel junction field effect transistors
• substrate potentials of transistors Nl and PI in the first inverter stage are controlled by the output voltage V 0 u ⁇ 2 from the second inverter. Since V 0 u ⁇ 2 is equal to 0, the substrate potential of the transistor Nl is equal to 0 and the substrate potential of transistor PI is also equal to 0.
• the circuit according to the invention performs better than the circuit according to prior art.
• the merit factor (taking account of the speed, total consumption and silicon surface area) of the invention is better than the merit factor for prior art .
• a circuit composed of two inverter stages and for which the substrate potentials of the transistors in the first inverter stage are controlled by the output signal from the second inverter stage also performs the required function, except for one inversion, while taking full advantage of the SOI technology.
• the said output signal OUT from the circuit is also applied to the grids of the two transistors P2 (PFET transistor) and N2 (NFET transistor) .
• Transistors P2 and N2 perform the dynamic control function for substrate potentials of transistors PI and Nl .
• the said first control signal is determined by a first state of the circuit on the output side of the said controlled inverter stage and the second control signal is determined by a second state of the circuit on the output side of the said controlled inverter stage.
• the signal determined by the said first state of the circuit can consequently be the output signal from a first inverter stage, called the first control inverter stage, located on the output side of the said controlled inverter stage and the signal determined by the said second state of the circuit can be the output signal from a second inverter stage called the second controlled inverter stage, also located on the output side of the said controlled inverter stage.
• the signal determined by the said first state of the circuit can be an output signal from a first inverter stage called the control inverter stage, located on the output side of the said controlled inverter stage and the signal determined by the said second state of the circuit may be the output signal from a second inverter stage, called the second control inverter stage, also located on the output side of the said controlled inverter stage.
• Each control inverter stage is preferably separated from the said controlled inverter stage by an even number (or zero) of inverter stages in series between the said controlled inverter stage and the said control stage .
• control inverter stages INV 2 and INV 4 are each separated from the said controlled inverter stage by an even or zero number of inverter stages in series: the control inverter stage INV 2 is located immediately on the output side of the said controlled inverter stage (the number of inverter stages located between the said controlled inverter stage and INV 2 then being zero) and the control inverter stage INV 4 is separated from the controlled inverter stage by inverter stages INV 2 and INV 3 (the even number then being equal to two) . Finally, note that the output OUT from the circuit is directly connected to the output OUT3 from the third inverter stage INV 3 .
• Each inverter stage may also be made using an odd number of elementary inverters chained in series .
• the substrate potential of the NFET transistor Nl of the first inverter stage is controlled by the output voltage V 0 u ⁇ n from the inverter INV N 2 and the substrate potential of transistors in inverter INV N 2 is controlled by the output voltage V 0 u ⁇ of inverter I V N3 .
• the invention is not limited to the particular embodiments described above, but includes any trigger with hysteresis, inverter or not, complying with its spirit.
• the invention does not apply solely to a trigger circuit with hysteresis, but includes any integrated circuit on a semiconductor on insulator substrate, particularly on an SOI substrate, comprising such a trigger circuit with hysteresis according to the invention.

Landscapes

• Logic Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Toys (AREA)
• Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
• Oscillators With Electromechanical Resonators (AREA)
• Electrotherapy Devices (AREA)
• Ultra Sonic Daignosis Equipment (AREA)
• Manipulation Of Pulses (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=32982178

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (12)

Citations (3)

Family Cites Families (3)

• 2003
  • 2003-04-02 FR FR0304088A patent/FR2853474B1/fr not_active Expired - Fee Related
• 2004
  • 2004-04-02 WO PCT/IB2004/001402 patent/WO2004088844A1/en active IP Right Grant
  • 2004-04-02 EP EP04725457A patent/EP1611681B1/de not_active Expired - Lifetime
  • 2004-04-02 DE DE602004006734T patent/DE602004006734T2/de not_active Expired - Fee Related
  • 2004-04-02 AT AT04725457T patent/ATE363766T1/de not_active IP Right Cessation
  • 2004-04-02 US US10/551,588 patent/US20060232313A1/en not_active Abandoned

Patent Citations (3)

Also Published As

Similar Documents

Legal Events