WO2004075426A1 - 信号処理装置、及びダイレクトコンバージョン受信装置 - Google Patents
信号処理装置、及びダイレクトコンバージョン受信装置 Download PDFInfo
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- WO2004075426A1 WO2004075426A1 PCT/JP2004/000313 JP2004000313W WO2004075426A1 WO 2004075426 A1 WO2004075426 A1 WO 2004075426A1 JP 2004000313 W JP2004000313 W JP 2004000313W WO 2004075426 A1 WO2004075426 A1 WO 2004075426A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
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- the present invention relates to a signal processing apparatus, and more particularly to a technology of a signal processing apparatus capable of removing a DC offset contained in an input signal.
- the direct convergence system has been known as one of the wireless reception methods for realizing the requirements for downsizing, low power consumption, and price reduction of wireless communication devices such as mobile phones.
- FIG. 24 is a diagram showing a general configuration of a receiving apparatus to which the direct conversion method is applied (hereinafter, referred to as “direct conversion receiving apparatus”).
- direct conversion receiving apparatus an RF (Radio Frequency) signal which is a high frequency signal received by antenna 101 is amplified by LNA (Low Noise A) and then branched into two paths. It is input to the RF port of mixers 103 and 104. Then, each amplified RF signal is down-converted by the respective mixer 103, 104. At this time, local signals that are local oscillation signals are input from the input terminals 105 and 106 to the local ports of the mixers 103 and 104, respectively, and these local signals are 90 degrees apart from each other.
- LNA Low Noise A
- the frequency is selected to be approximately the same as the carrier (carrier) frequency of the (desired) RF signal to be received. As a result, it is possible to obtain the base-pand signal in one down-conver- sion.
- the baseband signals output from the mixers 103 and 104 are amplified by the amplifiers 107 and 108, respectively, and pass through low pass filters (LPF) 109 and 110 for channel selection.
- the baseband signals passed through the low pass filters 109 and 110 are amplified by the amplifiers 1 1 1 1 alog to Digital Converter) 1 13, 1 14 convert to a digital signal.
- LPF low pass filters
- the baseband signals passed through the low pass filters 109 and 110 are amplified by the amplifiers 1 1 1 1 1 alog to Digital Converter) 1 13, 1 14 convert to a digital signal.
- downconversion to the base band is performed before signal components other than the channel signal are filtered. Even in the former stage, it is not possible to earn enough gains. Therefore, the intensity of the desired wave after the down conversion is basically weak, and the influence of the DC (Direct Current) offset of the outputs of the mixers 103 and 104 becomes relatively large.
- FIG. 25A shows that a local signal leaks through the path 115 into the RF port of the mixer 103. In this case, such local signal jamming causes DC offset due to self-mixing of the oral signals. This DC offset is a so-called static DC offset that does not change with time.
- FIG. 25B shows that an oral signal passes through path 116 into the RF port of mixer 103. In this case, as in the case of Fig. 25A, DC offset occurs due to local signal convergence.
- the DC offset amount fluctuates depending on the gain setting of the LNA 102. Therefore, at the time of LNA gain setting immediately after the start of reception of the RF signal, the amount of DC offset fluctuates.
- a local signal that has been transmitted to the input terminal of the LNA 102 may flow back to the antenna 101, and this may be radiated back into space, and then may return from the antenna to the LNA 102 and the mixer 103 again.
- the DC offset in this case is a so-called dynamic DC offset that fluctuates due to changes in the surrounding environment.
- FIG. 26A shows that a part of the RF signal received by the antenna 101 is input to the local port of the mixer 103 through the path 117.
- the input of the RF signal to the local port causes a DC offset due to the self-mixing of the RF signals.
- This DC offset is noticeable when there is a strong disturbance in the frequency band near the desired RF signal.
- the reception strength of the disturbance wave is
- This DC offset is a dynamic DC offset because it fluctuates due to the effects of FIG. 26B illustrates that a portion of the RF signal amplified by LNA 102 travels through path 118 into the local port of mixer 103.
- the RF signal intercalation causes a DC offset due to the self-mixing of the RF signals.
- This DC offset has both the property of dynamic DC offset due to fading etc. and the property of step DC offset fluctuation due to LNA gain change. Besides this, the DC offset also fluctuates due to the second-order distortion of the mixer.
- FIGS. 27 and 28 can be considered.
- 27A shows a method in which a capacitor 119 for blocking the DC component is provided at the output portion of the mixer 103
- FIG. 27B shows a method in which the high pass filter 120 for blocking the DC component is provided at the output portion of the mixer 103. It shows. Both methods shown in Fig. 27A and Fig. 27B have high-pass characteristics in characteristics.
- Fig. 27C shows a method in which the feedback element 121 is added to the amplifier 107 to apply DC service, and its function is both a high pass filter and an amplifier.
- ADC 122, signal processing unit 123, and DAC 124 are added, DC offset amount is taken in by ADC 122.
- DC processing amount is detected by signal processing unit 123, and DC offset is canceled in DAC 124 (cancelled) Shows how to generate a signal.
- the feedforward type is used, but a feedback type can be used. Also, in the method shown in FIG. 28, it is known to detect the DC offset amount in an undesired reception time slot and fix the signal for canceling the DC offset in the desired reception time slot. There is.
- an amplifier having an inverting input end and a non-inverting input end, and a feedback amplifier for feedback amplifying a signal output from the amplifier DC feedback high-pass filter comprising: a feedback amplifier that is a non-linear element that varies non-linearly to provide low gain for small amplitude signals and high gain for large amplitude signals have.
- part of the (desired) signal component to be received may be lost, and the DC offset amount may change with time.
- the DC offset amount may change with time.
- the method shown in FIG. 28 is complicated in hardware. It is necessary to generate a control signal synchronized with a reception time slot by a logic operation circuit and supply it to a circuit that processes analog signals such as RF signals. And the inability to cope with DC offset variations within the desired receive time slot.
- the DC voltage of the feedback signal is also The voltage is much higher than the ideal midpoint potential close to the voltage. That is, the output DC level of the non-linear element also becomes a voltage level considerably deviated from the ideal midpoint potential. Therefore, the non-linear element is in a high gain state even for a small amplitude signal, and the cut-off frequency of the high pass filter remains high. Therefore, in the technique of Patent Document 2, the time constant of the high-pass filter is determined by the absolute value of the DC offset contained in the input signal, and the effect of increasing the time constant with the convergence of the output DC level can not be obtained.
- the present invention has been made in view of the above problems, and is a signal processing apparatus capable of achieving both compatibility with dynamic DC offset and signal transmission that does not cause loss of a (desired) signal component to be received. And aims to provide a direct conversion receiver.
- a signal processing apparatus comprises: extracting means for extracting a signal of a voltage portion which is out of a preset voltage range from a signal to be processed; DC potential of the signal to be processed based on the extracted signal And adjusting means for adjusting and outputting.
- a direct conversion receiving apparatus comprises: mixing means for frequency mixing a received high frequency signal and an oscillation signal and converting the mixed signal into a baseband signal; and a voltage falling outside a voltage range preset from the base band signal. It is characterized by comprising: extraction means for extracting a part of the signal; and adjustment means for adjusting and outputting a DC potential of the base pand signal based on the extracted signal.
- FIG. 1 is a diagram showing an example of a schematic configuration of the direct conversion receiving device in the present embodiment.
- FIG. 2 is a diagram showing a schematic configuration example of the signal processing circuit 6 a in the signal processing device in the first embodiment.
- FIG. 3A is a diagram showing an example of the configuration of an active filter.
- FIG. 3B is a diagram showing a configuration example 1 of the signal extraction circuit 15.
- FIG. 3C is a diagram showing an input voltage-current characteristic of the signal extraction circuit 15.
- FIG. 4 is a diagram showing a configuration example 2 of the signal extraction circuit 15.
- FIG. 5 is a diagram showing a configuration example 3 of the signal extraction circuit 15.
- FIG. 6 is a diagram showing a schematic configuration example of the signal processing circuit 6 a in the signal processing device in the second embodiment.
- FIG. 7 is a view showing a schematic configuration example of the signal processing circuit 6 a in the signal processing device in the third embodiment.
- FIG. 8 is a diagram showing a schematic configuration example of the signal processing circuit 6 a in the signal processing device in the fourth embodiment.
- FIG. 9 is a view showing a schematic configuration example of the signal processing circuit 6 a in the signal processing device in the fifth embodiment.
- FIG. 10 is a diagram showing an example of a schematic configuration of a signal processing circuit 6 a in the signal processing device according to the sixth embodiment.
- FIG. 11 is a diagram showing an example of a schematic configuration of a signal processing circuit 6 a in the signal processing device in the seventh embodiment.
- FIG. 12 is a diagram showing an example of a schematic configuration of a signal processing circuit 6 a in the signal processing device in the eighth embodiment.
- FIG. 13 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the ninth embodiment.
- FIG. 14 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the tenth embodiment.
- FIG. 15 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the eleventh embodiment.
- FIG. 16 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the twelfth embodiment.
- FIG. 17 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the thirteenth embodiment.
- FIG. 18 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the fourteenth embodiment.
- FIG. 19 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the fifteenth embodiment.
- FIG. 20 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the sixteenth embodiment.
- FIG. 21 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the seventeenth embodiment.
- FIG. 22 is a diagram showing a schematic configuration example of a signal processing circuit 6 a in the signal processing device in the eighteenth embodiment.
- FIG. 23 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a in the signal processing device in the nineteenth embodiment.
- -Fig. 24 is a diagram showing a general configuration of a receiving apparatus to which the strict conversion scheme is applied.
- FIG. 25A is a diagram showing a main example of a generation mechanism of DC offset.
- FIG. 25B is a diagram showing another example of the generation mechanism of DC offset.
- FIG. 26A is a diagram showing a main example of a generation mechanism of DC offset.
- FIG. 26B is a view showing another example of a generation mechanism of DC offset.
- FIG. 27A is a diagram showing a conventional method for removing a DC offset.
- FIG. 27B is a diagram showing another conventional method for removing the DC offset.
- FIG. 27C is a diagram showing another conventional method for removing the DC offset.
- FIG. 28 is a diagram showing a conventional method for removing a DC offset BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a diagram showing an example of a schematic configuration of a direct-compilation receiver according to the present embodiment.
- the direct conversion receiver S includes an antenna 1 for receiving an RF (Radio Frequency) signal as a high frequency signal, an LNA (Low Noise Amplifier) 2 for amplifying the RF signal, and an oscillation signal (local A local oscillator 3 generates a local signal as an oscillation signal, a phase shifter 4 phase-shifts the phase of the local signal by 90 degrees, and frequency mixing of the amplified RF signal and the local signal to generate a baseband signal.
- RF Radio Frequency
- LNA Low Noise Amplifier
- Mixers 5a and 5b as mixing means for converting (down converting), signal processing circuits 6a and 6b as signal processing units for performing predetermined processing on the spanned signal, channel selection filters and processing IF (Interface) processing circuit 7 a, 7 b including ADC (Analog to Digital Converter) that converts the base band signal (I component, Q component) into a digital signal, and converted digital signal And a digital domain signal processing device 8 as a demodulation control unit that performs signal demodulation and the like based thereon.
- ADC Analog to Digital Converter
- the local signals input to mixer 5a and mixer 5b have a phase difference of 90 degrees with each other by phase shifter 4, and the carrier of the (desired) RF signal to be received at that frequency ) It is selected almost identical to the frequency.
- the digital domain signal processing device 8 is composed of a logic operation circuit (for example, mainly composed of a CPU).
- the signal processing circuits 6a and 6b perform processing such as DC offset removal on the baseband signals obtained by the down-compilation of the mixers 5a and 5b, and also have the function of adjusting the DC potential of the signals. Have. This makes it possible to achieve both dynamic DC offset and signal transmission that does not cause loss of the (desired) signal component to be received.
- the signal processing apparatus including the signal processing circuits 6a and 6b and the IF (Interface) processing circuits 7a and 7b and the like will be described. explain about.
- the signal processing circuits 6a and 6b are mainly described. Since the signal processing circuits 6a and 6b have the same circuit configuration, the signal processing circuit 6a is representative. Explain as.
- FIG. 2 is a diagram showing an example of a schematic configuration of the signal processing circuit 6a in the signal processing device in the first embodiment.
- the signal processing circuit 6 a performs predetermined processing on a base band signal input from an input terminal 10 as an input unit, and outputs the processed signal from an output terminal 11 as an output unit. More specifically, as shown in FIG. 2, the signal processing circuit 6a in the first embodiment includes: a high pass filter (HPF) 12 as a direct current component blocking means (extraction means); an amplifier 13; A low pass filter (LPF) 14 as removing means, a signal extracting circuit 15 as signal extracting means (extracting means), and an inverting amplifier 16 as inverting means are provided.
- HPF high pass filter
- LPF low pass filter
- the high-pass filter 12 and the amplifier 13 are inserted in the output path leading to the low-pass filter (LPF) 14 in the feedback path that is fed back from the output terminal 1 1 to the output node of the high-pass filter 12
- a signal extraction circuit 15 and an inverting amplifier 16 are interposed.
- the feedback path is a negative feedback path via the inverting amplifier 16.
- the feedback point 17 where the signal is fed back through the feedback path functions as the DC potential adjusting means (adjusting means) of the present invention, and adjusts the DC potential of the base band signal passed through the high pass filter 12. It has become.
- the high pass filter 12 has a function of blocking the direct current (hereinafter referred to as “DC”) component of the input baseband signal.
- FIG. 3A is a diagram showing an example of the configuration of the active filter, and instead of the high-pass filter 12, an active filter 1 composed of an amplifier 35, a single pass filter 36 and an inverting amplifier 3 7 2 a may be applied.
- the amplifier 13 amplifies the baseband signal from the feedback point 17. 4000313
- the amplifier 13 determines the gain of the DC potential adjusting means of the present invention.
- the base bend signal output from the amplifier 13 is output from the output terminal 11 and input to the feedback path.
- at least one channel selection filter or a channel selection filter may be applied.
- the low pass filter 14 has a function of removing high frequency components of the baseband signal input to the feedback path from the amplifier 13.
- the cut-off frequency of the low-pass filter 14 is selected so as to extract a frequency component corresponding to the time variation of the DC offset caused by fading or the disturbance light's first length. That is, it plays a role of removing the influence of high frequency components that is not related to the DC offset.
- the signal extraction circuit 15 has a function of extracting a signal of a voltage portion which is out of the voltage range when the voltage of the baseband signal from the low pass filter 14 is out of a preset voltage range.
- FIG. 3B is a diagram showing a configuration example 1 of the signal extraction circuit 15
- FIG. 3C is a diagram showing an input voltage-current characteristic of the signal extraction circuit 15.
- the diode 15a and the diode 15b are connected in antiparallel, and one end of the load resistor 15c is connected to the connection point B thereof.
- the connection point B is connected to the inverting amplifier 16.
- the other end of the load resistor 15c is connected to a voltage source 15d for matching the input of the inverting amplifier 16 with the DC level.
- the baseband signal is input from the connection point A of the signal extraction circuit 15.
- rvOj shown in FIG. 3C is a DC voltage supplied from the voltage source 15 d, and “VI” is a turn-on voltage of the diodes 15 a and 15 b. That is, in the signal extraction circuit 15, the input current I becomes almost zero in the voltage range of “V0 ⁇ V1” to “V0 + V 1J” in the voltage of the input signal. The output voltage appears in proportion to the current I.
- the output voltage is a voltage
- the bias voltage of the source 15 d that is, “V0”
- the voltage V of the input signal is out of this voltage range (exceeds this voltage range)
- the voltage portion outside that voltage range Only the excess component is reflected in the output voltage, that is, the signal of the voltage part which is out of the relevant voltage range is extracted and output to the inverting amplifier 16 become.
- the voltage of the base-pand signal input to the signal extraction circuit 15 is within a predetermined voltage range, the signal is not transmitted to the output node (connection point B), and the voltage is out of the voltage range.
- the signal of the voltage portion out of the voltage range of the signal is transmitted to the output node (node B).
- the voltage range of “V0 ⁇ VI” to “V0 + V1” is set so that the voltage of the baseband signal input to the signal extraction circuit 15 in the steady state falls within the voltage range.
- FIG. 3B the configuration example of the anti-parallel connection of the two diodes 15a and 15b is shown, but it is not limited to this.
- FIG. 4 is a diagram showing a configuration example 2 of the signal extraction circuit 15.
- the diode groups 15 e and 15 f in which two diodes are connected in series are anti-parallel connected, and the other parts are the same as the example of FIG. 3 B.
- the number of diodes connected in series may be any number of three or more.
- a plurality of diode groups in which two diodes are in antiparallel connection may be connected in series, or an intermediate configuration of these May be. Also, in the example shown in FIGS.
- one of the antiparallel connected diodes or the group of diodes may be omitted, and a configuration using forward on voltage and reverse breakdown voltage of one diode may be used.
- signal extraction circuit 15 is not only configured according to the diodes, bipolar Trang Soo evening or field effect transistor (FET: field effect transistor) may be constituted by applying.
- FIG. 5 is a diagram showing a configuration example 3 of the signal extraction circuit 15.
- the core portion is provided with an N-type MOS (Metal Oxide Semiconductor) FET 15 g and a P-type MOS SFET 15 h.
- the gate G of the N-type MOSFET 15 g is connected to the gate G of the P-type MOS FET 15 h, and the source S of the N-type MOSFET 15 g is connected to the source of the P-type M 15 SFET 15 h .
- the n-type MOSFET 15 g and the p-type MOS FET 15 h are connected to operate as source followers.
- connection point C between the gate G of the N-type MO SFET 15 g and the gate G of the P-type MOS FET 15 h is connected to the input terminal 15 i to which the above-described base-band signal is input.
- connection point D between the source S of 15 g and the source S of P-type MOSFET 15 h is connected to the output terminal 15 j.
- the positive power supply voltage VDD is applied to the power supply terminal 15 k
- the constant bias voltage VDD / 2 is applied to the connection point D
- the output is taken out as a current.
- this signal extraction circuit 15 The amplification operation is not performed in the voltage range of “VDDZ2 + VTp” to rVDDZS + VTnJ. Therefore, when the voltage of the input signal goes out of this voltage range, amplification operation is performed, and the signal of the voltage part out of the voltage range is extracted and output to the inverting amplifier 16 .
- the circuit configuration of the signal extraction circuit 15 shown in FIG. 5 other than the core portion may be any circuit configuration as long as the above signal can be extracted.
- the inverting amplifier 16 has a function of inverting and amplifying the polarity of the signal extracted by the signal extraction circuit 15.
- the inverted signal will be fed back to the output node of high pass filter 12.
- the inverting amplifier 16 may be configured to be interposed between the amplifier 13 and the first pass filter 14 or between the low pass filter 14 and the signal extraction circuit 15.
- the amplifier 13 may be replaced by an inverting amplifier, and the inverting amplifier 16 may be replaced by a non-inverting amplifier.
- the amplifier 13 may be replaced with an inverting amplifier and the inverting amplifier 16 may be omitted.
- the operation of the signal processing apparatus in the first embodiment will be described.
- the operation in the steady state will be described.
- the baseband signal input from the input terminal 10 passes through the high pass filter 12, is amplified by the amplifier 13, and is output from the output terminal 11.
- the voltage range of the signal extraction circuit 15 is set so that the voltage of the baseband signal from the low pass filter 14 in the steady state falls within the voltage range. No, and therefore, no negative feedback of the signal to the output node of the high pass filter 12 takes place.
- the operation in the case where the DC offset amount changes stepwise at a certain time will be described.
- the cutoff frequency of high pass filter 12 is sufficiently low
- the step of the DC voltage due to the DC offset fluctuation included in the input base pand signal is not blocked by the high pass filter 12 in this case, and passes through the high pass filter 12 almost as it is. It is input to the amplifier 13 and amplified.
- the base band signal including the step of the DC voltage is input to the low pass filter 14 of the feedback path, where the low frequency component is extracted and input to the signal extraction circuit 15.
- the signal extraction circuit 15 the signal component of the portion (in the example of FIG. 3B, the component exceeding 2 XV 1 in Peak To Peak) among the input base pand signal components is The DC offset is extracted as a non-negligible time fluctuation and output (transmitted) to the inverting amplifier 16.
- the extracted signal is inverted and amplified by the inverting amplifier 16 and fed back to the output node of the high pass filter 12.
- the output cathode of the high pass filter 12 is charged immediately, and the potential changes in the opposite direction to the step variation of the DC offset. That is, at the feedback point 17 shown in FIG. 2, the signal extracted by the signal extraction circuit 15 from the baseband signal that has passed through the high pass filter 12 is canceled and the DC potential of the baseband signal is adjusted. become. This operation continues until the voltage of the base band signal input to the signal extraction circuit 15 falls within the above voltage range (a range in which the signal is not extracted).
- the signal extraction (transmission) operation continues to be stopped until the DC offset fluctuation does not occur again, that is, the steady state is continued.
- This relates to the transfer function from the output node of the high pass filter 12 to the output terminal 11 when the voltage of the baseband signal input to the feedback circuit is outside the preset voltage range. It means that the low cutoff frequency is higher than the low cutoff frequency of the high pass filter 12.
- the signal processed by the signal processing circuit 6 a and output from the output terminal 11 is converted into a digital signal by the IF processing circuit 7 a (same as the signal processing circuit 6 b side), digital domain signal processing
- the signal demodulation is performed in the device 8.
- transmission without loss of a desired signal component which is incompatible with the prior art using a simple high-pass element, and correspondence to dynamic offset Can be compatible.
- there is no need for complicated ADC and DAC there is no need to externally supply a control signal synchronized with the time slot, and a desired reception time slot It is possible to cope with the variation of DC offset within.
- the variation of the DC offset is not indirectly observed and controlled in the form of the variation of the received signal level, and the variation of the DC offset is directly Since it is regularly monitored and the cancellation operation is performed, it is excellent in the certainty of the operation. That is, even if the received signal level does not fluctuate, if the DC offset fluctuates, the mechanism for causing the output DC level to converge reliably operates, and the DC offset does not fluctuate even if the received signal level fluctuates. No extra action is taken to cause the signal component to drop out.
- the configuration is simple because a control device is not required to determine fluctuations in the received signal level and generate a control signal to the high pass filter.
- the input and output nodes are separated in a DC manner by the .. eight pass filter 12 and the time constant as well as the convergence of the output DC level in the technique of Patent Document 2
- the filter 14 for example, depending on the condition of the high frequency component level of the output of the amplifier 13 or the relationship between the frequency characteristic of the amplifier 13 and the time constant of the DC offset assumed, etc. Even in the signal processing circuit 6a in which the filter 14 is omitted, the same effect as that of the first embodiment can be obtained.
- the signal processing apparatus shows an example of the present invention, but another embodiment will be described below.
- the same components as those in the signal processing apparatus in the first embodiment (or the fifth embodiment) are given the same reference numerals. Note that duplicate explanations shall be omitted.
- the low pass filter 14 may be omitted, and the configuration of the signal extraction circuit 15 may be the same as the first embodiment. As in one embodiment (eg, FIG. 3B, It is one of the configurations in Figure 4 and Figure 5).
- FIG. 6 is a diagram showing an example of a schematic configuration of the signal processing circuit 6a in the signal processing device in the second embodiment.
- the signal processing circuit 6a in the second embodiment differs from the signal processing circuit 6a in the first embodiment in that the amplifier 13 is replaced with an amplifier 18.
- the amplifier 18 includes an adjustment terminal for adjusting the DC level of the output voltage, in addition to the input terminal and the output terminal, and functions as a DC potential adjustment means of the present invention. It is designed to adjust the DC potential of the signal.
- the amplifier 18 determines the gain of the DC potential adjusting means of the present invention.
- the feedback signal output from the inverting amplifier 16 (the signal extracted by the signal extraction circuit 15 and inverted and amplified by the inverting amplifier 16) is input to the adjustment terminal of the amplifier 18. Ru.
- the signal component extracted by the signal extraction circuit 15 from the baseband signal that has passed through the high pass filter 12 is canceled out, and the DC voltage of the baseband signal is adjusted. Therefore, according to the second embodiment, similar to the case of the first embodiment, the same effect as the first embodiment can be obtained without being influenced by the step variation of the DC offset.
- inverting amplifier 16 is replaced by a non-inverting amplifier or the inverting amplifier is switched from amplifier 18 to the entrance of the feedback path. It is necessary to intervene in the meantime.
- FIG. 7 is a diagram showing an example of a schematic configuration of the signal processing circuit 6a in the signal processing device in the third embodiment.
- the signal processing circuit 6a in the third embodiment is different from the signal processing circuit 6a in the first embodiment in that the inverting amplifier 16 is a noninverting amplifier 20 and the amplifier 13 is a difference. The difference is that they are replaced by dynamic amplifiers 19 respectively.
- the differential amplifier 19 has an inverting input terminal, a non-inverting input terminal, and an output terminal, and functions as a DC potential adjusting means of the present invention. The DC potential of the spanned signal is adjusted. Also, the differential amplifier 19 determines the gain of the DC potential adjusting means of the present invention.
- the base-pand signal passed through the high pass filter 12 is input to the inverting input terminal of the differential amplifier 19, extracted by the signal extraction circuit 15, and amplified by the amplifier 20.
- the signal is input to the non-inverted input terminal of the differential amplifier 19 and the difference between the two input signals is taken and output in the differential amplifier 19.
- the differential amplifier 19 the signal extracted by the signal extraction circuit 15 from the baseband signal that has passed through the high-pass filter 12 is canceled out, and the DC potential of the base-banded signal is adjusted. It will be. Therefore, according to the third embodiment, similar to the case of the first embodiment, the same effect as that of the first embodiment can be obtained without being influenced by the step variation of the DC offset.
- FIG. 8 is a diagram showing an example of a schematic configuration of the signal processing circuit 6a in the signal processing device in the fourth embodiment.
- the signal processing circuit 6a in the fourth embodiment is provided with an adder 21 at a feedback point 17 shown in FIG. 2 in comparison with the signal processing circuit 6a in the first embodiment. The point is different.
- the adder 21 functions as the DC potential adjusting means of the present invention, and adjusts the DC potential of the baseband signal which has passed through the high pass filter 12.
- the adder 2 1 outputs the baseband signal that has passed through the high pass filter 12 and the feedback signal output from the inverting amplifier 16 (which is extracted by the signal extraction circuit 1 5 to the inverting amplifier 16). And the inverted and amplified signal) is output.
- the adder 21 the signal extracted by the signal extraction circuit 15 from the baseband signal that has passed through the eight-pass filter 12 is canceled out, and the DC potential of the baseband signal is adjusted. Become. Therefore, according to the fourth embodiment, as in the first embodiment, the same effect as that of the first embodiment can be obtained without being affected by the step variation of the DC offset.
- FIG. 9 is a diagram showing an example of a schematic configuration of the signal processing circuit 6a in the signal processing device in the fifth embodiment.
- the signal processing circuit 6a in the fifth embodiment is different from the signal processing circuit 6a in the first embodiment in that the high-pass filter 12 as a DC component blocking means is omitted, and The difference is that an integrator 22 is provided as an integrating means (adjustment means) at the exit of the feedback path.
- the baseband signal input from the input unit 10 is amplified by the amplifier 13 and a pass filter of the feedback path is generated.
- the low frequency component is extracted at 14 and input to the signal extraction circuit 15 which is a signal extraction means (extraction means).
- the signal extraction circuit 15 of the input baseband signal components, the signal component of the portion falling outside the above voltage range is extracted as a non-negligible time variation of the DC offset, and is output to the inverting amplifier 16 (Transmitted)
- the extracted signal is then inverted and amplified by the inverting amplifier 16 and output to the integrator 22.
- the integrator 2 2 is provided at the exit of the feedback path in the fifth embodiment, the present invention is not limited to this, and the integrator 2 2 is interposed between the signal extraction circuit 15 and the inverting amplifier 16. It may be configured to hesitate.
- FIG. 10 is a diagram showing a schematic configuration example of the signal processing circuit 6 a in the signal processing device in the sixth embodiment.
- the signal processing circuit 6a in the sixth embodiment is different from the signal processing circuit 6a in the fifth embodiment in that the amplifier 13 is replaced with an amplifier 18.
- This amplifier 18 has the same function as the amplifier 18 in the second embodiment.
- the feedback signal output from the integrator 2 2 (signal extraction circuit The signal extracted at 15, inverted and amplified at the inverting amplifier 16, and integrated at the integrator 2 2) is input to the adjustment terminal of the amplifier 18.
- the signal portion extracted and integrated by the signal extraction circuit 15 is canceled out from the input basepand signal, and the DC potential of the basepand signal is adjusted. . Therefore, according to the sixth embodiment, as in the first embodiment, the same effect as that of the first embodiment can be obtained without being affected by the step variation of the DC offset.
- the integrator 22 may be configured to be interposed, for example, between the signal extraction circuit 15 and the inverting amplifier 16. .
- FIG. 11 is a diagram showing a schematic configuration example of the signal processing circuit 6 a in the signal processing device in the seventh embodiment.
- the signal processing circuit 6a in the seventh embodiment is different from the signal processing circuit 6a in the fifth embodiment in that the inverting amplifier 16 is a noninverting amplifier 20, and the amplifier 13 is The difference is that they are replaced by differential amplifiers 19 respectively.
- This differential amplifier 19 has the same function as the differential amplifier 19 in the third embodiment.
- the input baseband signal is input to the inverting input terminal of the differential amplifier 19-the feedback signal output from the integrator 22 (which is extracted by the signal extraction circuit 15 and inverted amplifier 1
- the signal inverted and amplified at 6 and integrated at the integrator 22) is input to the non-inverting input terminal of the differential amplifier 19 and the difference between both input signals is taken at the differential amplifier 19 It is output.
- the differential amplifier 19 the signal portion extracted and integrated by the signal extraction circuit 15 is canceled from the input baseband signal, and the DC potential of the baseband signal is adjusted. . Therefore, according to the seventh embodiment, as in the first embodiment, the same effect as that of the first embodiment can be obtained without being affected by the step variation of the DC offset.
- the integrator 22 may be configured to be interposed between the signal extraction circuit 15 and the amplifier 20, for example.
- FIG. 12 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a in the signal processing device in the eighth embodiment.
- the signal processing circuit 6a in the eighth embodiment is provided with an adder 21 at the feedback point 17 shown in FIG. 2 as compared with the signal processing circuit 6a in the fifth embodiment. The point is different.
- This adder 21 has the same function as the adder 21 in the fourth embodiment.
- the adder 21 receives the baseband signal input and the feedback signal output from the integrator 22 (extracted by the signal extraction circuit 15 and inverted and amplified by the inverting amplifier 16). , And the signal integrated in the integrator 2 2) is added and output.
- the integrator 22 may be configured to be interposed, for example, between the signal extraction circuit 15 and the inverting amplifier 16.
- FIG. 13 is a diagram showing a schematic configuration example of the signal processing circuit 6 a and the like in the signal processing device in the ninth embodiment.
- the signal processing circuit 6 a in the ninth embodiment is different from the signal processing circuit 6 a in the first embodiment in that the first pass filter 14 and the signal extraction circuit 15 have a ninth embodiment. 3 differs in that a variable gain amplifier 2 3 as a means for variable gain is interposed.
- the signal processing apparatus is provided with a gain control unit 6c that performs gain control of the gain variable amplifier 23.
- the gain control unit 6 c is constituted by, for example, a logical operation circuit, calculates gain, and supplies a control signal according to this to the variable gain amplifier 23.
- the variable gain amplifier 23 can change the gain by the control signal from the gain control unit 6c.
- the gain can be obtained also when the amplitude of the desired signal component included in the input base signal is changed.
- the variable gain amplifier 23 may be interposed between the first pass filter 14 and the signal extraction circuit 15 as well.
- FIG. 14 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the tenth embodiment.
- the signal processing circuit 6a in the tenth embodiment is different from the signal processing circuit 6a in the first embodiment in that the inverting amplifier 16 has a variable gain inverting amplifier as the second gain variable means. 2 differs in that 4 has been replaced.
- the signal processing apparatus is provided with a gain control unit 6c that performs gain control of the variable gain inverting amplifier 24.
- the gain control unit 6c calculates gain and provides a control signal corresponding to this to the variable gain inverting amplifier 24.
- the gain variable inverting amplifier 24 can change the gain by the control signal from the gain control unit 6c.
- variable gain inverting amplifier 24 in addition to the same effect as that of the first embodiment can be obtained, by changing the gain of the variable gain inverting amplifier 24. It is possible to adjust the speed of the tracking response to the DC offset fluctuation and the behavior of the overshoot during the tracking. Also in the signal processing circuit 6a of the second to eighth embodiments, the variable gain inverting amplifier 24 (or variable gain amplifier) is applied instead of the inverting amplifier 16 (or amplifier 20). In this case, it is possible to obtain the same as in the tenth embodiment.
- FIG. 15 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the 11th embodiment.
- the signal processing circuit 6a in the first embodiment is different from the signal processing circuit 6a in the first embodiment in that the amplifier 13 is a variable gain amplifier 25 as a first gain variable means. It differs in that it has been replaced by.
- gain control of the variable gain amplifier 25 in the signal processing apparatus The gain control unit 6 c is provided to perform the The gain control unit 6c calculates the gain and provides a control signal corresponding thereto to the variable gain amplifier 25.
- the variable gain amplifier 25 can change the gain by the control signal of the gain control section 6 c.
- the entire circuit can have the function of a variable gain amplifier.
- the variable gain amplifier 25 may be applied instead of the amplifier 13 so that the same effect as the eleventh embodiment can be obtained. You can get it.
- FIG. 16 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the twelfth embodiment.
- the signal processing circuit 6a in the 12th embodiment is the same as the signal processing circuit 6a in the first embodiment, and the amplifier 13 is replaced with a variable gain amplifier 25. The difference is that the point and the inverting amplifier 16 are replaced by a variable gain inverting amplifier 24.
- the signal processing apparatus is provided with a gain control unit 6c that performs gain control of the variable gain inverting amplifier 24 and the variable gain amplifier 25.
- the gain control unit 6 c calculates, for example, the gain, and supplies a control signal corresponding to this to the variable gain inverting amplifier 24 and the variable gain amplifier 25.
- the variable gain inverting amplifier 24 and the variable gain amplifier 25 can change the gain by the control signal from the gain control unit 6c.
- the entire circuit can be provided with the function of the variable gain amplifier, and the variable gain inverting amplifier 2 4 By changing the gain of, it is possible to adjust the speed of the tracking response to DC offset fluctuation and the behavior of the overshoot during tracking.
- the gain control unit 6c may control the gains of the variable gain inverting amplifier 24 and the variable gain amplifier 25 with correlation to each other, or may control them independently of each other. As an example of correlated control, there is a method of keeping the product of gains of variable gain inverting amplifier 24 and variable gain amplifier 25 constant.
- variable gain amplifier 25 is applied instead of the amplifier 13 and the gain is substituted for the inverting amplifier 16 (or the amplifier 20).
- the variable inverting amplifier 24 (or variable gain amplifier) may be applied, whereby the same effect as that of the twelfth embodiment can be obtained.
- FIG. 17 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the thirteenth embodiment.
- the signal processing circuit 6a in the 13th embodiment has a gain between the low pass filter 14 and the signal extraction circuit 15 compared to the signal processing circuit 6a in the first embodiment. The difference is that variable amplifier 23 is interposed and that inverting amplifier 16 is replaced with variable gain inverting amplifier 24.
- the signal processing apparatus is provided with a gain control unit 6c that performs gain control of the variable gain amplifier 23 and the variable gain inverting amplifier 24.
- the gain control unit 6 c calculates the gain and provides a control signal according to this to the variable gain amplifier 23 and the variable gain inverting amplifier 24.
- the variable gain amplifier 23 and the variable gain inverting amplifier 24 can change the gain by the control signal from the gain control unit 6c.
- the gain can be obtained also when the amplitude of the desired signal component included in the input base signal is changed.
- the gain of the variable amplifier 23 it is possible to prevent the input amplitude to the signal extraction circuit 15 in the steady state from becoming too small or too large.
- By changing the gain it is possible to adjust the speed of tracking response to DC offset fluctuation and the behavior of overshoot at tracking.
- the gain control unit 6c may control the gains of the variable gain amplifier 23 and the variable gain inverting amplifier 24 with correlation to each other, or may control them independently of each other.
- correlated control there is a method of keeping the product of gains of variable gain amplifier 23 and variable gain inverting amplifier 24 constant. By this method, the speed of tracking response to DC offset fluctuation and the behavior of overshoot during tracking can be kept constant. Also, the signal extraction (transmission) / non-extraction (non-transmission) threshold in the signal extraction path 15 can be substantially changed.
- variable gain amplifier 23 is interposed between the low pass filter 14 and the signal extraction circuit 15 and the inverting amplifier 1 6
- the variable gain inverting amplifier 24 (or variable gain amplifier) may be applied instead of (or the amplifier 20), whereby the same effect as that of the thirteenth embodiment can be obtained.
- FIG. 18 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the fourteenth embodiment.
- the signal processing circuit 6a in the 14th embodiment is similar to the signal processing circuit 6a in the first embodiment, and it is between the single-pass filter 14 and the signal extraction circuit 15. The difference is that the variable gain amplifier 23 is interposed between the two, and that the variable amplifier 13 is replaced with the variable gain amplifier 25.
- the signal processing apparatus is provided with a gain control unit 6c that performs gain control of the variable gain amplifier 23 and the variable gain amplifier 25.
- the gain control unit 6 c calculates the gain, and provides a control signal according to this to the variable gain amplifier 23 and the variable gain amplifier 25.
- the gain variable amplifier 23 and the variable gain amplifier 25 can change the gain by the control signal from the gain control unit 6c.
- the 14th embodiment in addition to being able to obtain the same effect as the first embodiment, even when the amplitude of the desired signal component included in the input baseband signal changes, By adjusting the gain of the variable gain amplifier 23, it is possible to prevent the input amplitude to the signal extraction circuit 15 in the steady state from becoming too small or too large, and the whole variable gain amplifier as a whole circuit. It is possible to have the function of
- the gain control unit 6 c may control the gains of the variable gain amplifier 23 and the variable gain amplifier 25 with correlation to each other, or may control them independently of each other.
- correlated control there is a method of keeping the product of gains of variable gain amplifier 23 and variable gain amplifier 25 constant. By this method, it is possible to keep the speed of the tracking response to DC offset fluctuation and the behavior of the overshoot at the time of tracking constant. It is possible to provide the function of a variable gain amplifier as a whole.
- the variable gain amplifier 23 is interposed between the low pass filter 14 and the signal extraction circuit 15 and the amplifier 13 is replaced by Alternatively, the variable gain amplifier 25 may be applied to obtain the same effect as that of the 14th embodiment.
- FIG. 19 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the fifteenth embodiment.
- the signal processing circuit 6a in the fifteenth embodiment has a gain between the low pass filter 14 and the signal extraction circuit 15 compared to the signal processing circuit 6a in the first embodiment. The difference is that variable amplifier 23 is interposed, inverting amplifier 16 is replaced with variable gain inverting amplifier 24, and amplifier 13 is replaced with variable gain amplifier 25.
- the signal processing apparatus is provided with a gain control unit 6c that performs gain control of the variable gain amplifier 23, the variable gain inverting amplifier 24, and the variable gain amplifier 25.
- the gain control unit 6 c calculates the gain and provides a control signal according to the gain to the variable gain amplifier 23, variable gain inverting amplifier 24 and variable gain amplifier 25.
- the variable gain amplifier 23, variable gain inverting amplifier 24 and variable gain amplifier 25 can change the gain according to the control signal from the gain control unit 6 c.
- the gain can be obtained also when the amplitude of the desired signal component included in the input baseband signal changes.
- the gain of the variable amplifier 23 it is possible to prevent the input amplitude to the signal extraction circuit 15 in the steady state from becoming too small or too large.
- the gain it is possible to adjust the speed of the tracking response to the DC offset fluctuation and the behavior of the pershooting at the time of tracking, and furthermore, by changing the gain of the variable gain amplifier 25 It becomes possible to provide the function of the variable gain amplifier as the whole path.
- the gain control unit 6 c may control the gains of the variable gain amplifier 23, the variable gain inverting amplifier 24, and the variable gain amplifier 25 in correlation with one another, You may control independently.
- correlated control there is a method of keeping the product of the gains of the variable gain amplifier 23, the variable gain inverting amplifier 24 and the variable gain amplifier 25 constant.
- the speed of tracking response to DC offset fluctuation and the behavior of overshoot during tracking are kept constant while signal extraction (transfer) / non-extraction (not performed by signal extraction circuit 1 5) Transmission thresholds can be substantially changed.
- the tracking response speed to DC offset fluctuation, the overshoot behavior during tracking, and the effective threshold of signal extraction (transmission) / non-extraction (non-transmission) in the signal extraction circuit 15 are fixed. It is possible to change the overall gain of the circuit while maintaining it.
- variable gain amplifier 23 is interposed between the first pass filter 14 and the signal extraction circuit 15 and the amplifier 1 3
- variable gain amplifier 25 may be applied, and the variable gain inverting amplifier 24 (or variable gain amplifier) may be applied instead of the inverting amplifier 16 (or the amplifier 20). The same effect as that of the fifteenth embodiment can be obtained.
- FIG. 20 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the sixteenth embodiment.
- the signal processing circuit 6a in the 16th embodiment has the same configuration as the signal processing circuit 6a in the 15th embodiment, but the signal processing apparatus in the 16th embodiment further includes baseband control. Part 6 d is provided.
- the baseband control unit 6 d controls the gain of the variable gain amplifier 25 in accordance with the strength of the received RF signal.
- Gain setting information is supplied to the gain control unit 6c.
- the gain control unit 6 c is a variable gain amplifier 23, a variable gain inverting amplifier 24, and a variable gain amplifier 2. The gain of 5 is calculated, and the control signal according to this is given to all or a part of the variable gain amplifier 23, the variable gain inverting amplifier 24, and the variable gain amplifier 25 to perform gain control. .
- the sixteenth embodiment it is possible to obtain the same effect as that of the first embodiment. It is possible to optimize the speed of tracking response to DC offset fluctuation, the behavior of overshoot at tracking, and the transient response accompanying amplifier gain change.
- the signal processing apparatus according to the second to eighth embodiments may be configured as the signal processing apparatus according to the sixteenth embodiment as in the first embodiment. Similar effects can be obtained.
- FIG. 21 is a diagram showing an example of a schematic configuration of the signal processing circuit 6 a and the like in the signal processing device in the seventeenth embodiment.
- the signal processor in the seventeenth embodiment has the same configuration as the signal processor in the sixteenth embodiment, but the gain control method of each amplifier is different.
- the baseband control unit 6 d controls the gain of the variable gain amplifier 25 according to the strength of the received RF signal, and further, the gain of the variable gain amplifier 25 is The setting information is supplied to the gain control unit 6c.
- the digital domain signal processing device 8 is configured to supply bit error (detecting a signal demodulation error) rate data evaluated at the time of signal demodulation to the gain control unit 6c.
- the gain control unit 6c performs the gain variable amplifier 23 and the variable gain inverting amplifier 2 so as to minimize the demodulation error.
- variable gain amplifier 2 based on the gain setting information of the variable gain amplifier 25 supplied from the baseband control unit 6 d and the bit error rate information supplied from the digital domain signal processing unit 8, the gain control unit 6 c Variable gain amplifier 2 3, variable gain inverting amplifier 2 4, and variable gain amplifier 2 5 Calculate the gain of the variable gain amplifier 2 3, variable gain inverting amplifier 2 4, and variable gain amplifier It is given to all or part of 25 to perform gain control.
- the same effects as those of the first embodiment can be obtained. It is possible to optimize the speed of tracking response to DC offset fluctuation, the behavior of overshoot at tracking, the transient response etc. accompanying the gain change of the amplifier, and the reduction of bit error rate.
- the signal processing apparatus of the second to eighth embodiments may be configured as the signal processing apparatus of the seventeenth embodiment as in the first embodiment, whereby the seventeenth embodiment can be realized. The same effect can be obtained.
- FIG. 22 is a diagram showing a schematic configuration example of a signal processing circuit 6 a in the signal processing device in the eighteenth embodiment.
- the signal processing circuit 6a in the eighteenth embodiment is different from the signal processing circuit 6a in the first embodiment in that the high pass filter 26 is connected from the entrance of the feedback path to the output terminal 11. The difference is that it is interposed between them.
- the high-pass filter 12 is selected to have characteristics that optimize the response characteristics of the feedback path connected thereafter, and the characteristics required for the cancellation of the static offset are: It can be realized. Therefore, according to the eighteenth embodiment, the same effect as that of the first embodiment can be obtained more effectively. Also in the signal processing circuit 6a of the second to seventeenth embodiments described above, the high pass filter 26 may be interposed between the inlet of the feedback path and the output terminal 11, thereby The same effect as that of the eighth embodiment can be obtained.
- FIG. 23 is a diagram showing a schematic configuration example of the signal processing circuit 6a in the signal processing device in the nineteenth embodiment.
- the signal processing circuit 6a in the first nineteenth embodiment includes an eight-pass filter 29; an amplifier 30; a low pass filter 31; a signal extraction circuit 32; Each element (circuit) has two inputs and two outputs, and the signal path is differential.
- the signal processing circuit 6a in the nineteenth embodiment has the same basic function as the signal processing circuit 6a in the first embodiment, but the signal processing circuit 6a in the nineteenth embodiment has the same function.
- Each element (circuit) is designed to perform the same processing on two signals.
- input terminals 2 7 a and 2 7 b have the same polarity but different from each other.
- the same base-pand signal is input, and each signal passes through the high-pass filter 29 and is amplified by the amplifier 30, and then output from the output terminals 2 8 a and 2 8 b and the respective feedback paths.
- Is input to The low-pass filter 31 removes the harmonic components of each of the base-pand signals input to the feedback path, and the signal extraction circuit 32 removes the voltage of these base-spanned signals outside the preset voltage range. In some cases, the signal of the voltage part outside the voltage range is extracted. Then, the extracted signals are amplified by the amplifier 33 and then fed back to each other's signal path.
- the present invention is realized by the configuration of a feed pack type circuit (feedback circuit).
- the present invention is not limited to this, and is realized by a feedforward type circuit configuration. It is also possible.
- the signal processing apparatus of the present invention is applied to the direct conversion receiving apparatus, but the present invention is not limited to this, and it is possible to cope with dynamic DC offset with a simple configuration.
- the present invention can be applied to any receiving apparatus that needs to be compatible with signal transmission that does not cause loss of a desired signal component.
- the voltage of the processing target signal is out of the preset voltage range, the voltage is outside the voltage range by the extraction unit including the signal extraction unit and the like.
- the signal of the voltage portion is extracted, and the DC potential of the signal to be processed is adjusted on the basis of the extracted signal by the adjustment means comprising the DC potential adjustment means and the like.
- the output can be adjusted and output, and the transmission without loss of the desired signal component can be compatible with the response to the dynamic offset.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/545,671 US20060141972A1 (en) | 2003-02-20 | 2004-01-16 | Signal processing device and direct conversion reception device |
JP2005502665A JP4222368B2 (ja) | 2003-02-20 | 2004-01-16 | 信号処理装置、及びダイレクトコンバージョン受信装置 |
Applications Claiming Priority (2)
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JP2003042686 | 2003-02-20 | ||
JP2003-042686 | 2003-02-20 |
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WO2004075426A1 true WO2004075426A1 (ja) | 2004-09-02 |
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PCT/JP2004/000313 WO2004075426A1 (ja) | 2003-02-20 | 2004-01-16 | 信号処理装置、及びダイレクトコンバージョン受信装置 |
Country Status (3)
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US (1) | US20060141972A1 (ja) |
JP (1) | JP4222368B2 (ja) |
WO (1) | WO2004075426A1 (ja) |
Cited By (1)
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JP2006295638A (ja) * | 2005-04-12 | 2006-10-26 | Matsushita Electric Ind Co Ltd | 受信回路 |
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JP4332095B2 (ja) * | 2004-10-01 | 2009-09-16 | パナソニック株式会社 | Dcオフセットキャリブレーションシステム |
US7532874B2 (en) * | 2005-11-09 | 2009-05-12 | Texas Instruments Incorporated | Offset balancer, method of balancing an offset and a wireless receiver employing the balancer and the method |
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Also Published As
Publication number | Publication date |
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JPWO2004075426A1 (ja) | 2006-06-01 |
JP4222368B2 (ja) | 2009-02-12 |
US20060141972A1 (en) | 2006-06-29 |
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