Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
  • H10D30/6739—Conductor-insulator-semiconductor electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
  • H10D30/6743—Silicon
  • H10D30/6744—Monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
  • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions

Definitions

• the present invention relates generally to transistors and, more particularly, to fin field effect transistors (FinFETs).
• FinFETs fin field effect transistors
• Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with existing gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk MOSFET devices below the 0.1 ⁇ m process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance.
• Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs.
• double-gate MOSFETs the use of two gates to control the channel significantly suppresses short-channel effects.
• a FinFET is a recent double-gate structure that includes a channel formed in a vertical fin.
• the FinFET is similar to existing planar MOSFET in layout and fabrication.
• the FinFET also provides a range of channel lengths, CMOS compatibility and large packing density compared to other double-gate structures.
• a FinFET transistor uses a vertically formed strained channel layer that is self-aligned to the fin channel.
• the strained channel layer may include a crystalline material that is lattice constant mismatched with the crystalline material of the fin of the FinFET.
• the lattice constant mismatch induces tensile strain within the strained channel layer that increases carrier mobility. Increasing the carrier mobility, in turn, increases the drive current of the FinFET transistor, thus, improving FinFET performance.
• a semiconductor structure that includes a fin.
• the fin includes a first crystalline material and a plurality of surfaces.
• the structure further includes a layer formed on at least a portion of the plurality of surfaces, the layer including a second crystalline material.
• the first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the layer.
• a transistor includes a fin that further includes a first crystalline material and first and second end portions.
• the first crystalline material has a first lattice constant.
• the transistor further includes source and drain regions formed adjacent the first and second end portions of the fin.
• the transistor also includes a first layer of second crystalline material formed on at least a portion of the fin.
• the second crystalline material has a second lattice constant, wherein the first lattice constant is greater than the second lattice constant.
• the transistor additionally includes a dielectric layer formed on at least a portion of the first layer and a gate electrode formed on at least a portion of the dielectric layer.
• a method of forming a semiconductor device includes forming a fin that includes a first crystalline material and multiple surfaces. The method further includes forming a first layer on at least a portion of the multiple surfaces. The first layer includes a second crystalline material, wherein the first crystalline material is lattice constant mismatched with the second crystalline material to induce tensile strain within the first layer.
• FIG. 1 illustrates exemplary layers of a substrate that may be used for forming a fin of a FinFET consistent with the present invention
• FIG. 2A illustrates an exemplary fin consistent with the invention
• FIG. 2B illustrates a cross-sectional view of the exemplary fin of FIG. 2A consistent with the invention
• FIGS. 2C and 2D illustrate exemplary source and drain regions formed adjacent the fin of FIGS. 2A and 2B consistent with the invention
• FIG. 3A illustrates a cross-sectional view of a strained layer formed on a fin consistent with the invention
• FIG. 3B illustrates a top view of the strained layer of FIG. 3A formed upon a fin and source and drain regions consistent with the invention
• FIG. 4A illustrates a cross-sectional view of a gate dielectric and gate electrode formed upon a fin consistent with the invention
• FIG. 4B illustrates a top view of the gate dielectric and gate electrode of FIG. 4A formed upon a fin consistent with the invention
• FIG. 5 illustrates a strained insulator underneath the fin of FIGS. 2A and 2B consistent with another embodiment of the present invention.
• FIG. 6 illustrates damescene source/drain regrowth consistent with another embodiment of the present invention.
• an increased mobility channel FinFET is provided.
• a vertically formed strained channel layer consistent with the present invention, is self-aligned to the fin channel of the FinFET.
• the strained channel layer may include a crystalline material that is lattice mismatched with the crystalline material of the fin of the FinFET such that tensile strain is induced within the strained channel layer.
• FIG. 1 illustrates a cross-section of a substrate 100 formed in accordance with an exemplary embodiment of the present invention.
• Substrate 100 may be a silicon on insulator (SOI) structure that includes a fin channel layer 105 formed upon, for example, a buried oxide layer 110. Buried oxide layer 110 may be formed on a silicon layer (not shown).
• the thickness of fin channel layer 105 may range, for example, from about 500A to about 2000A and the thickness of buried oxide layer 110 may range, for example, from about 1000A to about 3000A.
• Fin channel layer 105 may include a crystalline material with a lattice constant larger than the lattice constant of a crystalline material selected for a strained channel layer (described with respect to FIGS. 3 A and 3B below). If, for example, silicon is selected for the strained channel layer, fin channel layer 105 may include a crystalline material with a lattice constant large than the lattice constant of silicon. Fin channel layer 105 may include, for example, Si x Ge ( ⁇ - x) with x approximately equal to 0.7. Other values of x may be appropriately selected.
• substrate 100 may be formed by wafer bonding epitaxial Si x Ge (I _ x) to an oxide/Si substrate wafer.
• Si x Ge I _ x
• other existing techniques may be used for forming substrate 100.
• a vertical fin 205 may be formed from fin channel layer 105.
• Fin 205 may be formed, for example, with a width (w) in a range of 10-15 nm. Fin 205 may be formed from fin channel layer 105 using any existing process, including, but not limited to, existing photolithographic and etching processes.
• source 210 and drain 215 regions may be formed adjacent the respective ends of fin 205, as shown in FIGS. 2C and 2D. Source 210 and drain 215 regions may be formed by, for example, deposition of a layer of crystalline material over fin 205.
• Source 210 and drain 215 regions may be formed from the layer of crystalline material using, for example, existing photolithographic and etching processes. One skilled in the art will recognize, however, that other existing techniques may be used for forming source 210 and drain 215 regions.
• Source 210 and drain 215 regions may include a crystalline material such as, for example, Si x Ge ( i- X) , with x approximately equal to 0.7.
• a strained layer 305 may be formed on fin 205, source 210 and drain 215, as shown in FIGS. 3A and 3B.
• Strained layer 305 may be formed on fin 205, source 210 and drain 215 using any appropriate existing process.
• strained layer 305 may be formed on fin 205, source 210 and drain 215 using a selective epitaxial deposition process.
• Strained layer 305 may include a crystalline material whose lattice constant is smaller that the lattice constant of the crystalline material used for fin 205. With a lattice mismatch between fin 205 and strained layer 305 tensile strain is produced in strained layer 305.
• Strained layer 305 may be formed, for example, with a thickness t that is approximately 1/2 to 1/3 of the fin 205 width w.
• the thickness t of strained layer 305 may be 5 nm.
• Strained layer 305 may include, but is not limited to, silicon.
• silicon One skilled in the art will recognize that other crystalline materials with lattice constants less than the crystalline material used to form fin 205 may, alternatively, be used.
• a gate dielectric 405 and gate electrode 410 may be formed on the portion of fin 205 not covered by source 210 and drain 215, as shown in FIGS. 4A and 4B.
• the gate dielectric 405 may include a thin layer of dielectric material, such as SiO, Si0 2 , SiN, SiON, HF0 2 , Zr0 2 , A1 2 0 3 , HFSiO(x) ZnS, MgF 2 ⁇ or other dielectric materials.
• Gate electrode 410 may be formed upon gate dielectric 405 and may include, for example, a layer of polysilicon.
• Gate dielectric 405 and gate electrode 410 may be formed on fin 205 using any existing processes, such as, for example, existing deposition and patterning processes. Formation of gate dielectric 405 and gate electrode 410 upon fin 205, thus, produces a FET sidewall vertical channel that includes a thin strained layer 305 at both vertical surfaces of fin 205.
• Strained layer 305 provides improved carrier mobility through the induction of tensile strain in strained layer 305 caused by the lattice mismatch between strained layer 305 and fin 205.
• This carrier mobility enhancement can increase the drive current of a FinFET transistor created using the semiconductor structure shown in FIGS. 4A and 4B.
• FIG. 5 illustrates an exemplary strained insulator 505 that may, consistent with another embodiment of the present invention, be formed beneath a fin of a FinFET, such as fin 205 shown in FIGS. 2A and 2B .
• Fin 205 may be formed upon the insulating material of strained insulator 505 such that the crystalline material of fin 205 and strained insulator 505 are lattice mismatched.
• a lattice mismatch between fin 205 and strained insulator 505 produces tensile strain in fin 205 that, in turn, improves carrier mobility of the FinFET.
• any appropriate insulating material with a lattice constant that is mismatched with the crystalline material of fin 205, may be used as strained insulator 505.
• FIG. 6 illustrates exemplary damascene source/drain regrowth consistent with another embodiment of the present invention.
• TEOS tetraethylorthosilicate
• a mask (mask 1) 610 may then be used to open a gate area 615.
• Fin 605 may be thinned down and a gate 620 may be formed by depositing and polishing polysilicon in gate area 615.
• a second mask (mask 2) 625 may be used to open a source and drain area 630.
• a nitride layer of active area 600, within the opened source and drain area 630, may be etched to expose a region of the source and drain area 630. From the exposed region, silicon can be selectively re- grown to produce a source 635 and a drain 640.

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• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 2003
  • 2003-01-23 US US10/349,042 patent/US6803631B2/en not_active Expired - Lifetime
• 2004
  • 2004-01-15 KR KR1020057013666A patent/KR20050096155A/ko not_active Abandoned
  • 2004-01-15 EP EP04702513.5A patent/EP1593161B1/en not_active Expired - Lifetime
  • 2004-01-15 WO PCT/US2004/000967 patent/WO2004068585A1/en not_active Ceased
  • 2004-01-15 JP JP2006502829A patent/JP2006516821A/ja active Pending
  • 2004-01-15 CN CNB200480002593XA patent/CN100521230C/zh not_active Expired - Fee Related
  • 2004-01-20 TW TW093101515A patent/TWI326489B/zh not_active IP Right Cessation
  • 2004-04-28 US US10/833,112 patent/US6897527B2/en not_active Expired - Lifetime

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