Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
  • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
  • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
  • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/26—Processing photosensitive materials; Apparatus therefor
  • G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/26—Processing photosensitive materials; Apparatus therefor
  • G03F7/42—Stripping or agents therefor
  • G03F7/427—Stripping or agents therefor using plasma means only
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
  • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
  • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/942—Masking
  • Y10S438/947—Subphotolithographic processing
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/976—Temporary protective layer
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Definitions

• the present invention is in the field of semiconductor fabrication and more particularly in the field of producing small features in a semiconductor device.
• the minimum feature size dictates, to a large extent, not only the performance or speed of an integrated circuit device, but also the size of the device.
• the size and speed of an integrated circuit device are critical parameters. Accordingly, it is generally desirable in any fabrication facility to be able to produce increasingly smaller features.
• steppers One traditional method of reducing feature sizes has been to replace existing photolithography equipment (commonly referred to as steppers) with next generation steppers.
• steppers photolithography equipment
• a semiconductor fabrication method that preferably includes forming a bilayer resist having an imaging layer and an under layer over a semiconductor substrate.
• the imaging layer is patterned to produce or define a printed feature having a printed dimension.
• the under layer is then processed to produce a sloped sidewall void in the under layer.
• the void has a finished dimension in proximity to the underlying substrate that is less than the printed dimension.
• Processing the under layer may include exposing the wafer to a high density, low pressure N 2 -based plasma maintained at a temperature of less than 10 °C.
• FIG 1 is a partial cross-sectional view of a semiconductor substrate over which an etch stop layer and a dielectric layer have been formed;
• FIG 2 illustrates processing subsequent to FIG 1 in which a dielectric cappping layer is formed over the dielectric layer
• FIG 3 illustrates processing subsequent to FIG 2 in which an under layer of a bilayer resist structure is coated over the wafer;
• FIG 4 illustrates processing subsequent to FIG 3 in which an imaging layer of the bilayer resist structure is formed
• FIG 5 illustrates processing subsequent to FIG 4 in which the imaging layer is patterned by photolithography imaging
• FIG 6 illustrates processing subsequent to FIG 5 in which a tapered wall via is formed in the under layer of the bilayer resist
• FIG 7 illustrates processing subsequent to FIG 6 in which a feature defined by the tapered wall via is formed in the underlying dielectric; and FIG 8 illustrates processing subsequent to FIG 7 in which the under layer is stripped from the wafer.
• the process steps and structures described herein do not cover a complete process flow for the manufacture of an integrated circuit.
• the present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are conventionally used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention.
• the following description does not address the interconnection of the transistors formed or other processing generally referred to as "back end" processing.
• the present invention contemplates a semiconductor fabrication technique in which a feature is printed or defined in a photoresist film over a disposable film. The disposable film is then processed to produce an opening or void having tapered sidewalls.
• the tapered sidewalls terminate on an underlying substrate such that the dimension of the opening at the substrate interface is smaller than the dimension of the printed feature.
• the processing of the disposable film to produce the tapered sidewalls may include a high density, low pressure N 2 -based plasma etch.
• the substrate can then be etched with the processed disposable layer in place to produce an etched feature in the substrate.
• the etched feature has a dimension that is roughly equal to the dimension of the opening at the substrate interface (i.e., smaller than the printed dimension).
• FIGs 1 through 8 illustrate a semiconductor fabrication processing sequence emphasizing significant aspects of the present invention.
• FIG 1 is a partial, cross-sectional view of a semiconductor wafer 100 at an intermediate stage in the fabrication of an integrated circuit.
• wafer 100 includes a substrate 102 over which an etch stop layer (ESL) 104 and a dielectric layer 106 have been formed.
• Substrate 102 may include a monocrystalline silicon or other semiconductor substrate that has been processed to include a plurality of electronic devices typically including p-channel and n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) and interspersed transistor isolation structures.
• substrate 102 may include one or more interconnect layers and one or more layers of interlevel dielectrics (ILDs) all as will be familiar to those in the field of semiconductor fabrication.
• Dielectric layer 106 and ESL 104 may also be referred to as comprising a portion of substrate 102.
• ESL 104 is a silicon-nitride (SiN) or carbon doped silicon-nitride (SiCN) layer having a thickness of approximately 500 angstroms.
• the silicon nitride may include plasma enhanced chemically vapor deposited (PECVD) silicon nitride produced by forming a plasma from ammonium and silane in a CND reactor chamber maintained at a temperature in the range of approximately 300 to 500 °C.
• PECVD plasma enhanced chemically vapor deposited
• Carbonated silicon nitride may be used in lieu of conventional silicon nitride when a lower dielectric constant material is desirable.
• Dielectric layer 106 may include approximately 3000 to 9000 angstroms of an electrically insulating material such as silicon oxide (SiO 2 ) or carbonated silicon oxide (SiCOH). Dielectric 106 likely serves as an ILD layer between a pair of interconnects (not shown) disposed above and below it.
• the silicon oxide may be formed by CVD by decomposing tetraethylorthosilicate (TEOS), by reacting silane and oxygen, by reacting dichlorosilane and nitrous oxide, or by another suitable CND oxide technique.
• TEOS tetraethylorthosilicate
• the SiCOH embodiment of layer 106 may be employed as a low-K dielectric (a material having a dielectric constant of less than approximately 3.0) where it is desirable to reduce intralayer and interlayer capacitive coupling effects.
• a capping layer 108 is formed over dielectric layer 106.
• Capping layer 108 may be incorporated into the process for at least two reasons.
• Dielectric layer 106 when serving as an ILD is typically subjected to some form of planarization process such as a chemical mechanical polish (CMP) process.
• CMP chemical mechanical polish
• the deposition of capping layer 108 may be used to achieve a desired final ILD thickness where the final ILD includes dielectric layer 106 and capping layer 108.
• dielectric layer 106 is or includes a low-K material such as SiCOH
• a relatively thin capping layer 108 may provide a stable film on which subsequent layers may be formed.
• capping layer 108 comprises approximately 800 angstroms of TEOS-based silicon oxide. With reference now to FIG 3 and FIG 4 a film 109 is formed over capping layer 108.
• Film 109 is a temporary film that will be removed before completion of the fabrication process.
• film 109 is a bilayer photoresist (BLR) that includes a relatively thick light absorbing polymeric under layer or disposable film (UL) 110 and a relatively thin imaging layer (IL) 112.
• IL 112 is a silicon containing photoresist imaging layer having a silicon content of approximately 6 to 15 percent by weight while UL 110 is a photo-insensitive polymer.
• Bilayer resists are used to compensate for the reduced depth of focus characteristic of photolithography systems that employ a short imaging wavelength (248 nm or less) and a large numerical aperture ( ⁇ A) lens. Such systems are almost universally employed to produce geometries of 100 nm or less.
• Bilayer resists address this problem by providing a thin film imaging layer and a thick, photo insensitive under layer. After patterning the imaging layer, the resulting pattern is transferred into the thick under layer using a special etch process that etches the under layer without substantially etching the imaging layer or the underlying substrate.
• An example of a commercially available bilayer resist is the SiBERTM resist system from Shipley Company, LLC.
• film 109 is formed by first coating wafer 100 with the polymeric UL 110.
• a thickness of UL 110 is preferably in the range of 3500 to 15000 angstroms.
• the coated UL is then baked at a temperature in the range of approximately 150 to 250 °C to cross-link the polymeric material and mechanically harden the film.
• IL 112 is coated over UL 110.
• a thickness of IL 112 is preferably in the range of approximately 500 to 3000 angstroms.
• LL 112 is baked at a temperature preferably in the range of 90 to 140 °C to form film 109 as depicted in FIG 4.
• the IL 112 is then exposed to imaging radiation through a conventional photomask and submersed in a suitable photoresist develop solution to selectively remove portions of IL and create a patterned IL 114 as shown in FIG 5.
• the exposure of IL 112 may be performed, for example, with 248 nm or 193 nm lithography equipment.
• Patterned IL 114 defines a void or printed feature 116.
• the photolithographic processing of the imaging layer to produce patterned IL 114 leaves UL 110 substantially intact since UL 110 is not photosensitive. Referring now to FIG 6, the printed feature 116 in patterned LL 114 is transferred into
• processing UL 110 by processing UL 110 to create a void, referred to herein as tapered wall via 120 in UL 110.
• processing referred to herein as dry develop processing is used to transfer printed feature 116 into UL 110.
• the dry develop processing of UL 110 employs chemistry and processing conditions that produce a tapered wall via 120 in UL 110 where tapered wall via 120 is characterized, as its name suggests, by tapered or sloping sidewalls 122.
• sidewalls 122 are characteristically sloped at an angle between roughly 70° to 89° (relative to an upper surface of the underlying substrate) and substantially straight (as seen in cross section).
• the tapered sidewalls 122 of via 120 beneficially provide a mechanism for effectively defining an integrated circuit feature that is smaller than its corresponding printed feature 116.
• the processing of UL 110 forms a tapered wall via 120 that effectively shrinks the geometries of the integrated circuit feature relative to size of the printed feature.
• the dry develop processing of UL 110 may be carried out in a conventional plasma etch chamber such as a chamber used to dry etch silicon oxide.
• the etcher used for the dry develop processing of UL 110 is dedicated to such processing and is not used for other etch processing within the fabrication facility.
• this "dedicated chamber" embodiment it is theorized that dedicating the chamber to dry develop processing reduces defects and improves the efficiency of the dry develop process.
• the under layer is developed or etched using an O 2 chemistry that tends to form vertical-sidewall or, even worse, bowed-sidewall voids. Vertical sidewall voids are not capable of achieving the feature size reduction benefit described above. Bowed-sidewall voids are ineffective because they are characterized by thin, overhanging portions of under layer material that tend to give way during the dry develop.
• a high density plasma refers to a plasma having an ion density in excess of approximately 10 11 ions/cm 3 and "low pressure" refers to a pressure of 15 mT or less.
• the dry develop processing of UL 110 is carried out in an inductively coupled plasma reactor with an RF source power in excess of 500 W, an RF bias power in excess of 50 W, an N 2 flow rate of at least 20 seem (no other gases are introduced into the chamber), a pressure of less than 15 mT, and a wafer (chuck) temperature of less than 10 °C.
• the dry develop processing may, for example, use an RF source power of 500 to 2500 W, an RF bias power of 50 to 200 W, an N 2 flow of 20 to 100 seem, a chamber pressure of 3 to 15 mT, and a wafer temperature of -10 to 10 °C. It is theorized that the N 2 dry develop chemistry, in conjunction with the high density, low pressure plasma etch parameters, produces a higher concentration of nitrogen "neutrals" than do comparable NH 3 /O 2 plasmas and that the plentiful nitrogen neutrals are responsible for producing the tapered sidewalls 122 in tapered wall via 120.
• the tapering of sidewalls 122 produced by the disclosed dry develop technique results in a feature size shrinkage of roughly 40 to 70 nm.
• the BLR dry develop processing technique disclosed herein may be used to create a tapered wall via 120 having a printed dimension (reference numeral 124) of approximately 170 nm and a final or lower dimension (126) of approximately 105 nm.
• tapered wall via 120 may be used to form a final feature having a minimum feature size that is less than the minimum feature size that the photolithography can print. If the printed feature 116 in pattered IL 114 has a dimension that is roughly the minimum feature size that the stepper can print, the tapered wall via 120 will result in an integrated circuit feature formed in the underlying wafer with a minimum dimension that is less than the printable minimum dimension. Those skilled in the field of photolithography having the benefit of this disclosure will appreciate that, in this manner, tapered wall via 120 can extend the useful life of the photolithography equipment by providing alternative means to shrink the size of a printed feature.
• the tapered wall via 120 can also be used to reduce the number of fatal defects by enabling a relaxation of the photolithography parameters without effecting the performance or die size of the finished device. More specifically, tapered wall via can be used in conjunction with a photolithography process that prints features 116 with a dimension that is greater than the minimum dimension specified for feature 116. After completing the wafer etch processing, the feature produced in the wafer will have a minimum feature that is comparable to the minimum feature specified for feature 116.
• a feature 128 of the integrated circuit is formed in wafer 100 using an anisotropic etch process with UL 110 (and IL 112) as an etch mask after the dry develop processing of UL 110.
• a fluorine-based reactive ion etch (RIE) process is used to form integrated circuit feature 128.
• feature 128 is a via formed in the underlying dielectric 106 and capping layer 108.
• a similarly processed void may serve as a trench from which an interconnect may be formed using a damascene process.
• the silicon containing embodiment of IL 114 is typically etched away during such an etch process leaving only the UL 110 over the wafer 100 including feature 128 as shown in FIG 7.
• feature 128 has a finished feature size (126) that is substantially equal to the finished dimension of tapered wall via 120 in UL 110.
• the remaining portions of UL 110 are stripped from wafer 100 using a conventional photoresist strip solution.
• wafer 100 is in condition for subsequent processing (not depicted) such as a metal deposition processing to fill feature 128 with a conductive material that may serve as a contact or an interconnect.

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Plasma & Fusion (AREA)
• Drying Of Semiconductors (AREA)
• Solid State Image Pick-Up Elements (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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Publications (3)

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• 2003
  • 2003-01-17 US US10/346,263 patent/US6858542B2/en not_active Expired - Lifetime
  • 2003-12-12 TW TW092135222A patent/TWI336106B/zh not_active IP Right Cessation
• 2004
  • 2004-01-16 JP JP2006501001A patent/JP2006516364A/ja active Pending
  • 2004-01-16 WO PCT/US2004/001219 patent/WO2004065934A2/en not_active Ceased
  • 2004-01-16 EP EP04703010A patent/EP1588219A2/en not_active Withdrawn
  • 2004-01-16 KR KR1020057013155A patent/KR20050094438A/ko not_active Ceased

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