KR20050094438A - 작은 형상부를 제조하기 위한 반도체 제조 방법 - Google Patents

작은 형상부를 제조하기 위한 반도체 제조 방법 Download PDF

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Publication number
KR20050094438A
KR20050094438A KR1020057013155A KR20057013155A KR20050094438A KR 20050094438 A KR20050094438 A KR 20050094438A KR 1020057013155 A KR1020057013155 A KR 1020057013155A KR 20057013155 A KR20057013155 A KR 20057013155A KR 20050094438 A KR20050094438 A KR 20050094438A
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KR
South Korea
Prior art keywords
layer
substrate
film
dimension
printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020057013155A
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English (en)
Korean (ko)
Inventor
테리 지. 스팍스
아제이 싱홀
커크 제이. 스트로제우스키
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20050094438A publication Critical patent/KR20050094438A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/976—Temporary protective layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020057013155A 2003-01-17 2004-01-16 작은 형상부를 제조하기 위한 반도체 제조 방법 Ceased KR20050094438A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/346,263 US6858542B2 (en) 2003-01-17 2003-01-17 Semiconductor fabrication method for making small features
US10/346,263 2003-01-17

Publications (1)

Publication Number Publication Date
KR20050094438A true KR20050094438A (ko) 2005-09-27

Family

ID=32712103

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057013155A Ceased KR20050094438A (ko) 2003-01-17 2004-01-16 작은 형상부를 제조하기 위한 반도체 제조 방법

Country Status (6)

Country Link
US (1) US6858542B2 (https=)
EP (1) EP1588219A2 (https=)
JP (1) JP2006516364A (https=)
KR (1) KR20050094438A (https=)
TW (1) TWI336106B (https=)
WO (1) WO2004065934A2 (https=)

Families Citing this family (16)

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US20040144585A1 (en) * 2003-01-24 2004-07-29 Vasser Paul M. Human powered golf cart with auxiliary power source
US7473644B2 (en) * 2004-07-01 2009-01-06 Micron Technology, Inc. Method for forming controlled geometry hardmasks including subresolution elements
CN101416293B (zh) * 2006-03-31 2011-04-20 应用材料股份有限公司 用于介电膜层的阶梯覆盖与图案加载
US8367303B2 (en) * 2006-07-14 2013-02-05 Micron Technology, Inc. Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control
US8563431B2 (en) * 2006-08-25 2013-10-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7973413B2 (en) * 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US20090057907A1 (en) * 2007-08-30 2009-03-05 Ming-Tzong Yang Interconnection structure
US7901852B2 (en) * 2008-02-29 2011-03-08 Freescale Semiconductor, Inc. Metrology of bilayer photoresist processes
US20100051896A1 (en) * 2008-09-02 2010-03-04 Samsung Electronics Co., Ltd. Variable resistance memory device using a channel-shaped variable resistance pattern
JP2010135624A (ja) * 2008-12-05 2010-06-17 Tokyo Electron Ltd 半導体装置の製造方法
KR20100082604A (ko) * 2009-01-09 2010-07-19 삼성전자주식회사 가변저항 메모리 장치 및 그의 형성 방법
KR101617381B1 (ko) * 2009-12-21 2016-05-02 삼성전자주식회사 가변 저항 메모리 장치 및 그 형성 방법
US9159581B2 (en) 2012-11-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a semiconductor device using a bottom antireflective coating (BARC) layer
CN105499069B (zh) * 2014-10-10 2019-03-08 住友重机械工业株式会社 膜形成装置及膜形成方法
KR102379165B1 (ko) 2015-08-17 2022-03-25 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US10867842B2 (en) * 2018-10-31 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for shrinking openings in forming integrated circuits

Family Cites Families (17)

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US4061530A (en) * 1976-07-19 1977-12-06 Fairchild Camera And Instrument Corporation Process for producing successive stages of a charge coupled device
DE3686721D1 (de) * 1986-10-08 1992-10-15 Ibm Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.
JP3001607B2 (ja) * 1989-04-24 2000-01-24 シーメンス、アクチエンゲゼルシヤフト 二層法における寸法安定な構造転写方法
US5196376A (en) * 1991-03-01 1993-03-23 Polycon Corporation Laser lithography for integrated circuit and integrated circuit interconnect manufacture
KR940010315B1 (ko) * 1991-10-10 1994-10-22 금성 일렉트론 주식회사 반도체 소자의 미세 패턴 형성 방법
US5320981A (en) * 1993-08-10 1994-06-14 Micron Semiconductor, Inc. High accuracy via formation for semiconductor devices
US5750441A (en) * 1996-05-20 1998-05-12 Micron Technology, Inc. Mask having a tapered profile used during the formation of a semiconductor device
US6251734B1 (en) * 1998-07-01 2001-06-26 Motorola, Inc. Method for fabricating trench isolation and trench substrate contact
US6432832B1 (en) * 1999-06-30 2002-08-13 Lam Research Corporation Method of improving the profile angle between narrow and wide features
US6313019B1 (en) * 2000-08-22 2001-11-06 Advanced Micro Devices Y-gate formation using damascene processing
US6645677B1 (en) * 2000-09-18 2003-11-11 Micronic Laser Systems Ab Dual layer reticle blank and manufacturing process
US6548347B2 (en) * 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US6541360B1 (en) * 2001-04-30 2003-04-01 Advanced Micro Devices, Inc. Bi-layer trim etch process to form integrated circuit gate structures
US6649517B2 (en) * 2001-05-18 2003-11-18 Chartered Semiconductor Manufacturing Ltd. Copper metal structure for the reduction of intra-metal capacitance
JP2002353195A (ja) * 2001-05-23 2002-12-06 Sony Corp 半導体装置の製造方法
US6559048B1 (en) * 2001-05-30 2003-05-06 Lsi Logic Corporation Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
KR100400254B1 (ko) * 2001-12-18 2003-10-01 주식회사 하이닉스반도체 반도체 소자의 제조방법

Also Published As

Publication number Publication date
JP2006516364A (ja) 2006-06-29
TW200507103A (en) 2005-02-16
WO2004065934A2 (en) 2004-08-05
US20040142576A1 (en) 2004-07-22
TWI336106B (en) 2011-01-11
WO2004065934A3 (en) 2005-03-10
WO2004065934A8 (en) 2005-08-04
US6858542B2 (en) 2005-02-22
EP1588219A2 (en) 2005-10-26

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