WO2004057658A2 - Transistor mis a grille auto-alignee et son procede de fabrication - Google Patents
Transistor mis a grille auto-alignee et son procede de fabrication Download PDFInfo
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- WO2004057658A2 WO2004057658A2 PCT/FR2003/050173 FR0350173W WO2004057658A2 WO 2004057658 A2 WO2004057658 A2 WO 2004057658A2 FR 0350173 W FR0350173 W FR 0350173W WO 2004057658 A2 WO2004057658 A2 WO 2004057658A2
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Classifications
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Definitions
- the present invention relates to an MIS transistor with a self-aligned gate and to its manufacturing process.
- MIS transistor is understood to mean a transistor having a Metal-Insulator-Semiconductor structure such as, for example MOS (Metal-Oxide-Semiconductor) transistors.
- MOS Metal-Oxide-Semiconductor
- the invention relates more particularly to the manufacture on a silicon substrate of such transistors, capable of operating in the microwave domain.
- the invention finds applications in microelectronics for the manufacture of microwave and / or power circuits, for example for the production of circuits usable in the telecommunications field.
- the components and circuits of the microwave type are usually produced on gallium arsenide (AsGa) substrates or on silicon (Si) substrates.
- the circuits formed on one substrate of gallium arsenide are generally not of great complexity and do not have a high integration density.
- the architecture of these circuits is therefore not optimized from the point of view of their compactness.
- FIG. 1 appended also gives an example of a microwave component, in this case a MOS (Metal Oxide Semiconductor) transistor, produced on a silicon substrate.
- MOS Metal Oxide Semiconductor
- the transistor of FIG. 1 comprises a source region 10, a channel region 12 and a drain region 14 defined in a silicon substrate 16.
- the source 10 and the drain 14 are, for example, formed by implantation of doping impurities of type n if the channel 12 is of type p, or of type p if the channel 12 is of type n.
- An insulating layer of silicon oxide 18 is formed on the surface of the substrate 16 and covers the source 10, channel 12 and drain 14 regions.
- a non-through opening 20 is made by etching in the oxide layer 18, substantially perpendicular to the channel region 12.
- a thin oxide layer 22 forms a grid insulation.
- a grid 24 is finally formed in the opening 20 above the layer 22 of grid insulation.
- the material forming the gate 24, in this case a metal, has a low resistivity and thus allows high frequency operation of the transistor produced.
- the integration density of the devices produced in accordance with FIG. 1 depends on the precision with which the opening 20, and therefore the grid 24, are aligned with respect to channel 12 and with respect to source and drain regions 10, 14. This precision depends directly on the quality of the manufacturing tools (in particular of alignment) of the semiconductor devices.
- a solution for increasing the compactness and the integration density of the circuits consists in self-aligning the gate 24 relative to the zones 10, 14 source and drain.
- the grid 24 is self-aligned with respect to the source and drain zones 10, 14 when the relative position of the grid 24 and the source and drain zones 10, 14 does not result from an alignment of the means used (masks for example) to produce these parts, but when the position of the source and drain zones 10, 14 is directly defined by the position of the grid 24 itself.
- the self-alignment of the grid with respect to the source and drain regions results from a method of forming the source and drain regions 10, 14. in which these regions are formed by implantation of impurities. in the substrate using the grid, made previously, as an implantation mask. The location of the grid thus precisely and automatically fixes the position of the source 10 of the channel 12 and of the drain 14.
- the methods of forming transistors with a grid self-aligned with respect to the source and drain zones generally involve treatments. high temperature.
- a heat treatment at a temperature of the order of 750 ° C. or more is carried out after the implantation of impurities, in order to '' activate the source and drain zones.
- the gate material used to make the transistors should preferably have a resistivity of between approximately 1 and 100 ⁇ .cm.
- the materials having a resistivity located in the indicated range either are not able to withstand the temperatures of the heat treatments used in the indicated processes for manufacturing transistors with a self-aligned grid, or either withstand these temperatures but diffuse and contaminate adjacent layers, reducing their performance.
- a material frequently used for the realization of the grid of the transistors with auto-grid aligned is polycrystalline silicon (Si poly).
- Polycrystalline silicon is in fact capable of withstanding the temperature, commonly of the order of 750 °, of the heat treatments implemented during the formation of these transistors.
- the resistivity of polycrystalline silicon, of the order of 10 3 ⁇ .cm is not compatible with the applications envisaged for transistors in the microwave domain. Furthermore, it is not known how to sufficiently decrease the resistivity of polycrystalline silicon to obtain operation of the transistors at microwave frequency.
- Most metals are also able to withstand heat treatments, but they diffuse in the adjacent layers, which transforms the performance of these layers.
- a low resistivity grid material such as copper (Cu) or silver (Ag) compatible with CMOS integration.
- Cu copper
- Ag silver
- a barrier material such as, for example, titanium nitride (TiN)
- TiN titanium nitride
- silver oxidizes very easily even at low temperatures, which increases its resistivity. Ag is therefore also difficult to use.
- the least resistive materials cannot be used, it is known to reduce the grid resistance by using a T-shaped grid having a vertical bar, the underside of which is situated above an insulating layer overhanging the channel.
- the overall impedance of the grid, in particular the stray capacitance (Miller capacity) between the grid and the source and the drain and the source is small, because the overlap surface between the grid and the source or the grid and the drain is limited to the section of the vertical bar of the T.
- the resistance of the grid itself is reduced by the presence of the horizontal bar of the T which is wider than the vertical bar.
- the transistor produced with such a T-grid can be self-aligned or not. As explained above, the use of the non-self-aligned grid has a negative impact on the density of integration of devices using this technology.
- the manufacturing process on a semiconductor substrate of an MIS (Metal-Insulator-Semiconductor) transistors comprises the following steps: a) the production on the substrate of a dummy grid consisting of one or more material (s) capable of withstanding heat treatment.
- the dummy grid is produced for example, by forming on the substrate a stack of layers comprising in order, an oxide layer called the pedestal layer, a layer of polycrystalline or amorphous silicon and a layer of silicon nitride. The stack is then shaped by etching to form the shape of the dummy grid with lateral flanks.
- Such a process in which the location of the grid is first occupied by a dummy grid, this dummy grid being replaced in a terminal phase by the final grid is called the damascene process.
- the dummy grid produced during the process, has a double function: it allows, firstly, to define the location of the source and drain regions during step b), then to define the location of the final gate of the transistor made of low resistivity material. Indeed, the coating of the dummy grid on its lateral flanks forms, after the elimination of this dummy grid, a "mold" for the final grid.
- the transistor appears as shown in Figure 2 of the drawings appended to this application. This figure corresponds to Figure 5 of the aforementioned patent.
- the description which follows of this figure is intended to show an example of a state of the manufacturing stage of a transistor, before elimination of the dummy gate. It describes the state of the transistor at this stage of manufacture independently of the embodiments to arrive at this state.
- a silicon substrate 100 for example p doped, are implanted gradual source and drain regions identified in FIG. 2 with the references 118 and 120. These regions 118, 120 are implanted on either side of a zone of channel 112. A layer of silicide, formed above the source regions 118 and drain 120, is indicated with the references 119 and 121 respectively.
- a stack 110 of layers together forming the dummy grid is located above the channel 122 and the silicide layer 119, 121.
- This stack comprises a layer 114 called thermal oxide, the lower part of which comes immediately above the layers 119 , 121 and channel 122.
- a central part of the stack 110 comprises, above the layer 114 of thermal oxide, a layer of polycrystalline or amorphous silicon 104 then a layer of silicon nitride 106. The sides of this central part are bordered from the inside to the outside by a rise in the layer 114 of thermal oxide, lateral spacers 116 for example made of phosphorus-doped silicon oxide or PSG (phosphosilicate glass), and finally another layer 124 in oxide of phosphorus doped silicon.
- This last layer 124 borders the lateral flanks of the stack 110 at the level of the spacers 116 and also comes above the layers 119, 121 of silicide.
- the lower part of the spacers 116 rests on a peripheral part of the
- a layer 126 either of unintentionally doped intrinsic silicon oxide, or of borophosphosilicate (BPSG) is situated above the. Layer 124 and coats the grid stack 110.
- BPSG borophosphosilicate
- the total thickness of the layers 104 and 106 is, for example, of the order of 100 to 500 nm and corresponds substantially to the thickness of the gate of the transistor which will ultimately be obtained at the end of the manufacturing process.
- the elimination of the dummy grid comprises a final step of chemical etching, for example with hydrofluoric acid.
- a shape of the opening which is flared corresponding substantially to the T shape which it is desired to obtain for the grid
- L 'acid attack more or less rapid depending on the material, allows to flare an opening 130 shown in Figure 3, according to a particular profile chosen. In the case of the example described, it is, seen in section, a T-profile.
- the attack speed of the layer of lateral spacers 116 in PSG is 5 times greater than the attack speed of the thermal oxide 114 and 3 times greater than the attack speed of l intrinsic oxide of the layer 126.
- the layer 126 is borophosphosili ⁇ ate (BPSG) it is noted that the attack speed of the PSG is 6 times higher than that of the BPSG.
- the shape of the flaring obtained for the horizontal bar of the T is dependent on the attack of the lateral spacers, the size of which depends above all on the optimization of the source and drain and which must be made with a material having a higher attack speed than the material used for planarization.
- the object of the invention is to propose a MOS transistor which has improved performance compared to the transistors of the prior art.
- Another object is to propose such a particularly compact transistor compatible with the production of CMOS circuits (complementary MOS) with a high integration density.
- the invention relates to an MIS transistor, having a gate resistance and a Miller capacity of controlled and reproducible value having a very high cut-off frequency making it possible to operate in the microwave range, for example greater than 200 gigahertz.
- the invention further relates to a transistor having leakage currents lower than those of the prior art.
- the invention also aims to propose methods for producing such a transistor.
- An object of the present invention is, therefore, to propose a method of manufacturing an MIS transistor with a gate, source and drain self-aligned and capable of operating in the microwave range.
- the invention relates to a self-aligned MIS transistor having a source area and a drain area on either side of a channel area, as well as a T-shaped gate structure.
- a self-aligned MIS transistor having a source area and a drain area on either side of a channel area, as well as a T-shaped gate structure.
- horizontal and vertical or higher, lower used in the present application do not refer to the horizontal direction and to the vertical terrestrial direction.
- the horizontal direction is that of the plane of a plate supporting the transistors
- the vertical direction is the direction perpendicular to this plate.
- first extension zones between the channel and source and drain zones respectively have doping of the same nature as the source and drain zones but lower.
- second extension zones between the channel and source and drain zones respectively or between the channel zones and the first extension zones have a doping of opposite nature to that of the source and drain zones .
- the invention also relates to a manufacturing process on a semiconductor substrate at least one self-aligned MIS transistor having a source area and a drain area on either side of a channel area, as well as a T-shaped gate structure composed of a vertical bar located above the channel zone, surmounted by a horizontal bar projecting on either side of the vertical bar, this horizontal bar having a lower part, a lateral part and an upper part, the grid structure being constituted by a stack of one or more conductive layers, a base area of the grid structure being defined as being around the base of the vertical bar of the T, characterized in that it comprises a step of producing a solid form having the form in T of the grid that we want to make, and the coating of this shape in a shaped material, this material covering the base area of the grid structure, the vertical bar of the T, and the lower and lateral parts of the horizontal bar e of the T of the final grid.
- the coating material covers the base area of the grid structure, the vertical bar of the T, and the lower and lateral parts of the horizontal bar of the T of the final grid, it is meant that material will be preserved throughout the subsequent manufacturing stages, and will remain in the transistor. It is therefore a material capable of withstanding all the chemical treatments subsequent to its installation.
- the shaped material covers at least part of the source and drain zones.
- the coating material will consist of silicon nitride Si 3 N 4 , hafnium oxide Hf0 2 , zirconium oxide Zr0 2 or also aluminum oxide A1 2 0 3 .
- the initial material forming the initial solid form coated by the form material is not the material forming the grid, it may be for the vertical bar of the T of a metal or of polycrystalline silicon and for the horizontal bar of a bilayer formed by a first under layer of polycrystalline silicon, or of a metal or of a silicide, and of a second under layer of silica or of nitride of silicon.
- the material forming the final grid may for example be a metal or polycrystalline silicon.
- the initial material forming the initial solid form coated by the form material is the initial material forming the grid
- it may be for the vertical bar of the T of oxidizable metal or polycrystalline silicon and for the horizontal bar d 'a metal or a silicide for the first sublayer and silica or silicon nitride for the second sublayer.
- the coating material consists of silicon nitride Si 3 N 4
- the material constituting the initial solid form may be polycrystalline silicon and the final material of the metal or polycrystalline silicon.
- the initial material is the same as the final grid material it may be oxidizable metal or polycrystalline silicon.
- the material constituting the initial solid form may be a metal or polycrystalline silicon and the final material of the metal or polycrystalline silicon.
- the initial material is the same as the final grid material, it may be oxidizable metal or polycrystalline silicon.
- the coating material consists of zirconium oxide Zr0 2
- the material constituting the initial solid form may be a metal or polycrystalline silicon and the final material a metal or polycrystalline silicon.
- the initial material is the same as the final grid material it may be metal or polycrystalline silicon BRIEF DESCRIPTION OF THE DRAWINGS
- FIG. 1, already described is a schematic cross section of a MOS transistor of known type formed on a solid semiconductor substrate;
- - Figure 2 already described, is a schematic cross section showing a step of producing a transistor having a T-grid;
- - Figure 3 already described, is a schematic cross section of a step of producing a transistor representing in particular the shape of a T-shaped opening into which a gate will be inserted.
- Figures 1 to 3 relate to the prior art.
- Figures 4 to 13 show cross sections of transistors during manufacture and represent the shape of what will be called to become at the end of the manufacturing process a transistor according to one inventio.
- FIG. 4 represents the form of a grid produced according to the invention. The method of obtaining this form will now be described, this form is produced on a. substrate 2, for example, made of p-doped silicon. A stack of layers is produced on this substrate as follows. First, a layer 4 in a material with high permittivity, the remains of this layer will later form a grid or pedestal insulator. This insulator is sacrificial or not.
- the first sub-layer 10 may be, for example, an intrinsic poly silicon or a metal or a silicide.
- the surface sublayer 12 could be, for example, a layer of silica.
- the etching of the hard mask 8 formed by an intrinsic polycrystalline silicon under layer 10 and a silica under layer 12 is carried out, to give the shape of the horizontal bar of the T which will be a part of the shape of the final grid.
- the vertical bar 6 of the T-grid structure is made by isotropic etching of the layer 6 of metal or polycrystalline silicon, under the hard mask 8, selectively with respect to the grid insulation 4 or pedestal.
- the role of the silica layer 12 will subsequently be to avoid the growth of an epitaxial layer and the siliciding of the gate structure. At the end of this first step we obtain the T-shape of the future grid.
- This shape rests on a pedestal 4, on which rests substantially the shape of the bar vertical 6 of the T consisting for example of a layer of highly doped polycrystalline silicon (As, boron, phosphorus) or of a layer of alloy of Si: Ge: C.
- the shape of the horizontal bar 8 of the T comes to- above the vertical bar 6 in the form of the hard mask 8.
- the vertical bar 6 of the T has a lower surface 61 in contact with the insulating layer 4, a lateral surface 62 and an upper surface 63 in contact with the lower sub-layer 10 of the hard mask 8.
- the horizontal bar 8 of the T has a lower surface 81, a lateral surface 82 and an upper surface 83.
- the T-structure shown in Figure 4 is coated with a material of form 14 whose function will be to keep the shape of the T-structure until the end of the manufacturing process. It will, therefore, also keep the size of the patterns.
- the choice of the material of form 14 supposes that the various physicochemical treatments which it will undergo during the manufacturing process will consume it little, or even leave it intact. Indeed, the methods of eliminating the hard mask 8, of the sacrificial grid formed of the materials contained in the vertical bar 6 and the horizontal bar 8 of the T, of the sacrificial oxide 4, and the various cleanings preceding the deposition of the The final stack of grids must leave this shaped material intact or consume as little as possible.
- the material of form 14 can be deposited by a LPCVD technique (Lo pressure Chimical Vapor Deposition). Materials such as Si 3 N 4 , Hf0 2 , Zr0 2 or A1 2 0 3 for example are capable of meeting the above-mentioned requirements for the material of form 14.
- the material of form 14 shown in FIG. 5 completely coats the T-structure shown Figure 4, and covers layer 4 of gate insulation. It will be noted in particular that the material 14 completely covers the lateral surface 62 of the vertical bar 6, the lower 81 and upper 83 surfaces of the horizontal bar 8 as well as the lateral surface 82 of this horizontal bar. In the example shown in FIG.
- the cover of the gate base by the material 14 extends so as to cover a part of zones 16 and 18 which will become after implantation as explained below the source and the drain respectively.
- the lower and upper surfaces 61 and 63 of the vertical bar of the T which are in contact respectively with the gate oxide 4 and the lower surface 81 of the T, are not coated.
- complementary areas n and p are produced by masking.
- one proceeds, in itself known manner, to the ion implantation of the zones 16 and 18 of the layer 2, which will thus become as indicated above the source and the drain. So that the grid edge is not masked by the drop shadow of the hard mask 8, the ion implantation beam will be inclined, as indicated by arrows in FIG.
- a first weak ion implantation is usually carried out in the vicinity of the grid, for example, some 10 13 / cm 3 to some 10 14 / cm 3 .
- a second stronger implantation, for example, of some 10 14 to some 10 15 / cm 3 is carried out after the installation of spacers represented at 116 in FIG. 2.
- the hard mask 8 plays among others the role of spacer. The plates will be rotated during the ion implantation in order to maintain the symmetry of the structures.
- the implantation is carried out asymmetrically as shown in FIG. 5, leading to source and drain zones 16, 18 asymmetrical.
- FIG. 5 At the end of this second step, the shape shown in FIG. 5 is obtained.
- a channel area 20 On the substrate 2, a channel area 20 has thus been produced, corresponding to the non-implanted area of the substrate 2, with on either side implanted zones 16, 18, source and drain respectively as well as the T-structure shown in Figure 4 coated as indicated above by the shaped material 14.
- the implantation is asymmetrical there is also a zone 19 weakly implanted compared to the other zones 16, 18 of source and drain.
- an anisotropic etching of the shape material 14 is then carried out.
- the objective of this etching is to clear the source and drain zones 16 and 18 respectively.
- Figure 6 only the shape obtained from a symmetrical layout has been shown.
- FIG. 6 The shape obtained from this engraving is shown in FIG. 6. With respect to the shape shown in FIG. 5, it can be seen that the upper surface of the form material 14, covering the upper surface 83 of the dummy grid and part of the upper lateral surface 82 of the horizontal bar 8 of the T are no longer covered with the coating material 14. Likewise, the upper part of the layer 4 of grid insulator protruding on either side of a vertical projection of the horizontal bar 8 of the grid T on the plane of the layer 4, is no longer covered with the coating material 14.
- the surfaces cleared by the elimination of part of the layer 4 and, being immediately above the source and drain zones 16 and 18 have been identified. 22 and 24 respectively.
- source and drain zones are raised by a selective epitaxy making it possible to thicken, from surfaces 22 and 24, the source and drain zones 16 and 18 respectively.
- the growth of the selective epitaxial layer can be done with faceting at the edge of the pattern. This faceting has been represented by an inclination 26, 28 of the epitaxial growth layer itself marked 30, 32, these layers 30, 32 being located respectively above the source 16 and drain 18 regions. Since the exposed part of the hard mask 8 is not silicon or one of its alloys, there is no growth of epitaxial layer on the grid structure. At the end of this stage the future transistor has the form 'shown in Figure 7. Compared to Figure 6, the source and drain areas have been enlarged by an elevation. A source 34 and a drain 36 are now formed by the part 16 and the epitaxial growth part 30, and by the part 18 and the epitaxial growth part 32 respectively.
- the coating layer 14 it is possible, starting from the state shown in FIG. 5, to etch the coating layer 14 to eliminate the part of this layer which lies beyond a surface located below the horizontal bar of the T The portion of gate oxide 4 located under the layer 14 thus reduced is also eliminated.
- This etching of the coating 14 also removes the portion of the coating 14 located above the upper surface 83 and an upper part of the coating 14 of the side surface 82 of the horizontal bar 8 of the T. then the epitaxial growth of the source and drain zones 16 and 18 from the surfaces 22 and 24 respectively of these zones.
- the ion implantation is then carried out after thickening of the source and drain zones in the same way as that described in relation to FIG. 5.
- the ion implantation carried out after thickening of the sources and drain 16, 18 makes it possible to reduce the depth junction in the source 16 and drain 18 regions of the part buried in the substrate.
- this reduction in the thickness of the implanted zones 16 and 18 does not appear in FIG. 8, but it should be understood that these zones are less thick in the mode of realization commented in connection with FIG. 8 as in that commented in connection with FIG. 7.
- part of the dopant is retained in the raised epitaxial layer 30, 32.
- the resistance of layers of the source 16 and drain 18 regions heavily doped stays the same.
- FIG. 8 shows a first optional variant in which the region of the extensions between the channel region and each of the source 16 and drain 18 regions has a greater junction depth than the heavily doped region. These regions of greater depth are shown in dotted lines at 42 and 44 in FIG. 8. To obtain this result, it suffices to adjust the thickness of the shaping material 14 relative to the thickness of the epitaxial layers 30, 32 of the sources. 16 and drain 18 raised.
- a second ion implantation is carried out. While the ion implantation of the regions of greater depth 42 and 44 corresponds to the implantation of the source and drain extensions, the second ion implantation is of the same type as the substrate 2, and therefore of the type opposite to the source implantation and drain. This implantation is done in pockets 45, 46 which are are found under zones 42, 44 of the first ion implantation.
- the advantage of these embodiments is to allow to adjust the series resistance of the source of the transistor under the gate while reducing the parasitic capacitance in the contact areas of the raised source and drain 30 and 32.
- the implementation of pocket 45 and 46 also makes it possible to reduce the leakage of the transistors without significant influence on the parasitic capacities of the source and of the drain 16 and 18 because the thickness of the layers 30 and 32 makes it possible to avoid the penetration of the implanted ions to form the zones 45 and 46 under zones 16 and 18 respectively.
- P, Sb for example if the source and drain are of type n;
- P, Sb for example if the pockets are of type n (source and drain of type p).
- FIGS. 9 to 12 correspond to the case represented in FIG. 7. It should be understood that the further manufacturing from the case shown in FIG. 8 is exactly the same as that which will now be described.
- self-aligned source and drain 16, 18 are silicided.
- the hard mask is protected superficially by the layer of Si0 2 and laterally by the form layer 14.
- the transistor 1 is in the state shown in FIG. 9.
- the raised layers 30, 32 are covered respectively by a layer 50, 52 of silicide. In known manner, this layer of silicide will be used for making the electrical contacts.
- an insulating layer for example of oxide, is deposited, this layer covering the entire part shown in FIG. 9 including the shape in grid T.
- a planarization of the layer 54 by chemical mechanical polishing is then carried out.
- the layer 12 of Si0 2 of the hard mask 8 is completely attacked and partially the sublayer 10 of poly-intrinsic Si or of metal or of silicide.
- the insulating oxide layer 54 completely covers the drain and source regions 34, 36 as well as the lateral parts of the vertical bar 6 of the T and outcrop at the same level as what remains of the sub-layer 10 of poly-intrinsic Si. It is noted that the lateral parts of layer 14 which coated the side part of the horizontal bar of the T protrude above this level.
- the final grid structure is then stacked by depositing a grid insulator or by oxidizing the substrate 2.
- a layer of gate insulator 65 completely covers the internal surface of the coating layer 14 as well as the part located immediately above the channel zone 20.
- the insulator layer 65 comprises thus a part 64 taking the place of the layer part 4 which was located under the surface 63 of the vertical bar of the T.
- the part 64 of the grid insulator layer 65 could be replaced by part 64 ', shown in dotted lines in Figure 12, obtained by oxidation of layer 2 at the foot of the vertical bar of T.
- the grid insulator layer 65 comprises a part 66 covering the lateral internal wall of layer 14 which formed the vertical bar of T.
- parts 67 and 68 which respectively cover the internal surface of the lower part and the lateral part of the horizontal bar of the T.
- the insulating material of the grid 65 can be deposited, for example, by a method of the LPCVD type giving rise to a proper deposit. This deposition is followed by the deposition of a grid material 69 by LPCVD also. Polishing will make it possible to free up isolated areas not shown and to planarize the grid structure thus produced.
- the grid structure was made in damascene.
- the layer 12 of the hard mask 8 is removed. If this layer 12 is SiO 2 deposited, may proceed by attack with diluted FH. If the gate insulator 4 is thermal Si02 it will also be eliminated during this attack but at a speed 3 times lower than the insulator forming the layer 12. An insulator of the Hf02 type will hardly attack (or even almost attack null) it will be removed from the substrate by dry etching following the etching of layer 14; ditto for Zr02. On the other hand A1203 will be eliminated at a speed comparable to that of layer 4 in Si02.
- a shrinkage of the layer 4 under the layer 14 will be observed, up to a limit 41, as described in relation to FIG. 7, and exposure of the material 10 which is either polycrystalline Si or metal or silicide.
- the material 10 which is either polycrystalline Si or metal or silicide.
- self-aligned and selective epitaxy is carried out on the source and drain regions 16, 18 as well as on the layer 10 forming a layer 11 shown in FIG. 13.
- the layer 11 replaces on the layer 10, the layer 12 of for example Si02.
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Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/539,928 US20070001239A1 (en) | 2002-12-16 | 2003-12-15 | Mis transistor with self-aligned gate and method for making same |
EP03809986A EP1573793A2 (fr) | 2002-12-16 | 2003-12-15 | Transistor mis a grille auto-alignee et son procede de fabrication |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR0215916 | 2002-12-16 | ||
FR0215916A FR2848726B1 (fr) | 2002-12-16 | 2002-12-16 | Transistor mis a grille auto-alignee et son procede de fabrication |
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WO2004057658A2 true WO2004057658A2 (fr) | 2004-07-08 |
WO2004057658A3 WO2004057658A3 (fr) | 2004-08-19 |
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PCT/FR2003/050173 WO2004057658A2 (fr) | 2002-12-16 | 2003-12-15 | Transistor mis a grille auto-alignee et son procede de fabrication |
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US (1) | US20070001239A1 (fr) |
EP (1) | EP1573793A2 (fr) |
FR (1) | FR2848726B1 (fr) |
WO (1) | WO2004057658A2 (fr) |
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US8698230B2 (en) * | 2012-02-22 | 2014-04-15 | Eastman Kodak Company | Circuit including vertical transistors with a conductive stack having reentrant profile |
JP5944285B2 (ja) | 2012-09-18 | 2016-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9000539B2 (en) | 2012-11-08 | 2015-04-07 | Texas Instruments Incorporated | Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance |
US10734498B1 (en) * | 2017-10-12 | 2020-08-04 | Hrl Laboratories, Llc | Method of making a dual-gate HEMT |
CN111868931B (zh) | 2018-02-14 | 2024-03-12 | Hrl实验室有限责任公司 | 高度缩放的线性GaN HEMT结构 |
US11404541B2 (en) | 2018-02-14 | 2022-08-02 | Hrl Laboratories, Llc | Binary III-nitride 3DEG heterostructure HEMT with graded channel for high linearity and high power applications |
TWI736300B (zh) * | 2020-06-01 | 2021-08-11 | 國立陽明交通大學 | 射頻積體電路及其製造方法 |
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US5289030A (en) * | 1991-03-06 | 1994-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with oxide layer |
FR2757312B1 (fr) * | 1996-12-16 | 1999-01-08 | Commissariat Energie Atomique | Transistor mis a grille metallique auto-alignee et son procede de fabrication |
JP3544833B2 (ja) * | 1997-09-18 | 2004-07-21 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6127233A (en) * | 1997-12-05 | 2000-10-03 | Texas Instruments Incorporated | Lateral MOSFET having a barrier between the source/drain regions and the channel region |
US6180978B1 (en) * | 1997-12-30 | 2001-01-30 | Texas Instruments Incorporated | Disposable gate/replacement gate MOSFETs for sub-0.1 micron gate length and ultra-shallow junctions |
US5994191A (en) * | 1998-07-09 | 1999-11-30 | Advanced Micro Devices, Inc. | Elevated source/drain salicide CMOS technology |
US6077733A (en) * | 1999-09-03 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned T-shaped gate through dual damascene |
JP2002026310A (ja) * | 2000-06-30 | 2002-01-25 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4447128B2 (ja) * | 2000-07-12 | 2010-04-07 | 富士通マイクロエレクトロニクス株式会社 | 絶縁ゲート型半導体装置の製造方法 |
KR100342306B1 (ko) * | 2000-09-05 | 2002-07-02 | 윤종용 | 트랜지스터 및 이의 형성 방법 |
KR100398874B1 (ko) * | 2001-11-21 | 2003-09-19 | 삼성전자주식회사 | 티자형의 게이트 전극을 갖는 모스 트랜지스터 및 그 제조방법 |
US6452229B1 (en) * | 2002-02-21 | 2002-09-17 | Advanced Micro Devices, Inc. | Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication |
-
2002
- 2002-12-16 FR FR0215916A patent/FR2848726B1/fr not_active Expired - Fee Related
-
2003
- 2003-12-15 EP EP03809986A patent/EP1573793A2/fr not_active Withdrawn
- 2003-12-15 WO PCT/FR2003/050173 patent/WO2004057658A2/fr active Application Filing
- 2003-12-15 US US10/539,928 patent/US20070001239A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
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FR2848726A1 (fr) | 2004-06-18 |
FR2848726B1 (fr) | 2005-11-04 |
EP1573793A2 (fr) | 2005-09-14 |
WO2004057658A3 (fr) | 2004-08-19 |
US20070001239A1 (en) | 2007-01-04 |
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