TWI736300B - 射頻積體電路及其製造方法 - Google Patents

射頻積體電路及其製造方法 Download PDF

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TWI736300B
TWI736300B TW109118286A TW109118286A TWI736300B TW I736300 B TWI736300 B TW I736300B TW 109118286 A TW109118286 A TW 109118286A TW 109118286 A TW109118286 A TW 109118286A TW I736300 B TWI736300 B TW I736300B
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林鴻志
黃宇安
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國立陽明交通大學
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Abstract

一種射頻積體電路，包括：一CMOS矽基板，其內埋置有至少一CMOS元件；以及至少一薄膜電晶體，其形成在該CMOS矽基板上並用作一射頻元件。該薄膜電晶體包括一T形閘極電極。一種用於製造該射頻積體電路的方法亦被提出。

Description

射頻積體電路及其製造方法
本發明是有關於一種積體電路，特別是指一種射頻積體電路及其製造方法。
在傳統的積體電路中，射頻元件和CMOS(Complementary Metal-Oxide-Semiconductor，互補式金屬氧化物半導體)元件同時內建於矽基材中，並且例如在水平方向上彼此隔開。由於這樣的積體電路並非以精巧的(compact)方式設計，所以具有較大的電路面積以及相對較高的製造成本。
因此，本發明的一目的，即在提供一種射頻積體電路，其具有相對精巧的結構，以及相對較小的電路面積。
於是，本發明所提供的一種射頻積體電路包含一 CMOS矽基板、及至少一薄膜電晶體。該CMOS矽基板埋置有至少一CMOS元件在其中。該至少一薄膜電晶體形成在該CMOS矽基板上並用作一射頻元件，該薄膜電晶體包括一T形閘極電極。
本發明的積體電路中，該薄膜電晶體具有一半導體通道。
本發明的積體電路中，該半導體通道是由選自多晶矽、ZnO、IGZO和ZnON的材料製成。
本發明的積體電路中，還包含一保護層，該保護層是形成在該CMOS矽基板上以覆蓋該T形閘極電極並使得在該T形閘極電極的兩個翼部下方分別形成兩個空氣邊襯。
本發明的積體電路中，該T形閘極電極包括n+摻雜多晶矽下電極部分和硼摻雜多晶矽上電極部分，該硼摻雜多晶矽上電極部分具有該等翼部並且較寬於該n+摻雜多晶矽上電極部分。
因此，本發明的另一目的，即在提供一種用於製造一射頻積體電路的方法，包含以下步驟：(A)在一矽基材中形成至少一CMOS元件；(B)在該矽基材上形成一層間介電層，以覆蓋該至少一CMOS元件；(C)在該層間介電層上形成一圖案化主動區；(D)在該層間電介質層上形成一閘極絕緣層，以覆蓋該圖案化主動區；(E)在該閘極絕緣體層上形成一導電層，該導電層包括一貼附至該閘極絕緣體層的下導電子層、及一堆疊在該下導電子層 上的上導電子層，該上導電子層是由不同於該下導電子層的材料製成；(F)在該導電層上的對應於該圖案化主動區的位置形成一圖案化蝕刻罩；(G)對從該圖案化蝕刻罩暴露出的該導電層進行蝕刻，以形成一T形閘極電極；(H)在步驟(G)之後，除去該圖案化蝕刻罩；(I)將該閘極絕緣體層圖案化，以形成一介於該T形閘極電極和該圖案化主動區之間的圖案化閘極絕緣體層；及(J)將該T形閘極電極的一上電極部分摻雜，並將該圖案化主動區摻雜以便在其中且在該T形閘極電極的相對兩側形成一源極區和一汲極區，同時在該源極區和該汲極區之間且在該圖案化閘極絕緣體層的下方形成一通道區。
本發明的方法中，步驟(E)包含以下子步驟：(E1)在該閘極絕緣層上形成一n+摻雜多晶矽層，該n+摻雜多晶矽層具有一上部、及一作為該下導電子層的下部；及(E2)對該上部摻雜硼離子以形成該上導電子層。
本發明的方法中，步驟(G)包含以下子步驟：(G1)對從該圖案化蝕刻罩暴露出的該導電層異向性蝕刻，以在該圖案化蝕刻罩下方形成一圖案化上導電子層和一圖案化下導電子層；及(G2)在子步驟(G1)之後，對該圖案化上導電子層和該圖案化下導電子層進行同向性及側向蝕刻，以形成該T形閘極電極，其中對 於該圖案化下導電子層比對於該上導電子層和該閘極絕緣層具有更高的蝕刻選擇性。
本發明的方法中，子步驟(G1)是使用HBr/O2/Cl2電漿來實施，且子步驟(G2)是使用Cl2電將來實施。
本發明的方法中，在步驟(J)之後，還包含步驟：在該層間介電層上形成一保護層以覆蓋該T形閘極電極並使得在該T形閘極電極的兩個翼部下方分別形成兩個空氣邊襯。
本發明的方法中，該圖案化主動區是由選自多晶矽、ZnO,、IGZO及ZnON所組成之群組的材料製成。
本發明的方法中，該圖案化主動區是由多晶矽製成。
本發明之功效在於：由於射頻元件是在一縱向上堆疊在CMOS矽基板上以形成一相對精巧的結構，因此具有相對較小的電路面積以及相對較低的製造成本。
10:CMOS矽基板
1:CMOS元件
11:通道
12:通道
2:矽基材
3:層間介電層
4:圖案化主動區
41:源極區
42:汲極區
43:半導體通道/通道區
5:閘極絕緣層
51:圖案化閘極絕緣層
6:導電層
61:下導電子層
61’:圖案化下導電子層
61”:n+摻雜多晶矽下電極部分
62:上導電子層
62’:圖案化上導電子層
62”:硼摻雜多晶矽上電極部分
63:T形閘極電極
64:空氣邊襯
600:n+摻雜多晶矽層
601:下部
602:上部
7:圖案化蝕刻罩
8:保護層
9:薄膜電晶體
101-1010:步驟
本發明之其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中：圖1至圖9是示意圖，繪示出分別與本發明實施例用於製造一射頻積體電路的方法的連續步驟相對應的半導體結構；及圖10是一流程圖，說明該實施例中所執行的步驟。
在本發明被詳細描述之前，應當注意在以下的說明內容中，類似的元件是以相同的編號來表示。
參閱圖8和圖9，顯示出根據本發明實施例的射頻積體電路，該射頻積體電路包括一CMOS矽基板(Silicon CMOS Substrate)10和至少一薄膜電晶體9。
該CMOS矽基板10包含至少一個埋置於其中的CMOS(互補金屬-氧化物-半導體)元件1。在圖9所示的實施例中，該CMOS矽基板10例如包括一矽基材2、至少一個形成在該矽基材2中的CMOS元件1，以及一形成在該矽基材2上以覆蓋該至少一CMOS元件1的層間介電層3。
該薄膜電晶體9形成在該CMOS矽基板10上並且用作一射頻元件。該薄膜電晶體9包括一T形閘極電極63。
在圖9所示的實施例中，該薄膜電晶體9具有一半導體通道43，該半導體通道43可以由選自由多晶矽、ZnO、IGZO和ZnON組成的群組中的材料製成。
在圖9所示的實施例中，該射頻積體電路還可以包括一保護層8，該保護層8形成在該CMOS矽基板10上以覆蓋該T形閘極電極63，使得在該T形閘極電極63的兩個翼部下方分別形成兩個空 氣邊襯(Air Spacers)64。
在圖8和圖9所示的實施例中，該T形閘極電極63包括一n+摻雜多晶矽下電極部分61”和一具有該等翼部並且比該n+摻雜多晶矽下電極部分61”更寬的硼摻雜多晶矽上電極部分62”。
如圖10所示，一種用於製造該射頻積體電路的方法包括步驟101至步驟1010。
在步驟101中，如圖1所示，該至少一CMOS元件1形成在該矽基材2中。該CMOS元件1可以具有兩個通道11、12，其中每一者可以包含單晶矽，或者包含矽和鍺。由於形成該CMOS元件1的程序在本領域中是眾所周知的，因此為了簡潔起見省略其細節。
在步驟102中，該層間介電層3形成在該矽基材2上以覆蓋該至少一CMOS元件1(見圖1)。該層間介電層3可以通過使用電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition，以下簡稱PECVD)來沉積一二氧化矽層，然後進行化學機械磨光來形成。
在步驟103中，一圖案化主動區4形成在該層間介電層3上。該圖案化主動區4可以通過使用化學氣相沉積來沉積一材料層，隨後進行微影製程和乾蝕刻來形成。該圖案化主動區4(該材料層)可以由一選自由多晶矽、ZnO、IGZO和ZnON組成的群組的材料製成。在一個實施例中，該圖案化主動區4由多晶矽製成。
在步驟104中，一閘極絕緣層5形成在該層間介電層3上，以覆蓋該圖案化主動區4(見圖2)。該閘極絕緣層5可以通過使用PECVD或原子層沉積來沉積閘極氧化物(SiO2)來形成。
在步驟105中，一導電層6形成在該閘極絕緣體層5上(見圖3)。該導電層6包括一貼附至該閘極絕緣體層5的下導電子層61、及一堆疊在該下導電子層61上並且由不同於該下導電子層61的材料製成的上導電子層62。
在圖2和圖3所示的實施例中，步驟105可以包括以下第一子步驟及第二子步驟，在其中的第一子步驟中，一n+摻雜多晶矽層600形成在該閘極極絕緣層5上，該n+摻雜多晶矽層600具有一上部602、及一作為該下導電子層61的下部601，該n+摻雜多晶矽層600可以使用PECVD或低壓化學氣相沉積來形成，而在其中的第二子步驟中，在上部602摻雜有硼離子以形成該上導電子層62。該硼離子可以是BF2+離子。
在本實施例中，該下導電子層61和該上導電子層62是通過摻雜該n+摻雜多晶矽層600的上部602而形成。在其他實施例中，該下導電子層61和該上導電子層62亦可以通過兩個不同材料的沉積來形成。
在步驟106中，一圖案化蝕刻罩7形成在該導電層6上且在一對應於該圖案化主動區4的位置(見圖4)。
在步驟107中，從該圖案化蝕刻罩7暴露出的該導電層6被蝕刻以形成該T形閘極電極63(見圖4至圖6)。
在圖4至圖6所示的實施例中，步驟107可以包括以下在前的第一子步驟，以及在後的第二子步驟，在其中的第一子步驟中，從該圖案化蝕刻罩7暴露出的該導電層6接受異向性蝕刻，以在該圖案化蝕刻罩7的下方形成一圖案化上導電子層62'及一圖案化下導電子層61'(見圖4和圖5)，而在其中的第二子步驟中，該圖案化上導電子層62'和該圖案化下導電子層61'接受同向性和側向蝕刻，以形成該T形閘極電極(圖6)，其中對於該圖案化下導電子層61’比對於該上導電子層62’和該閘極絕緣層5具有更高的蝕刻選擇性。在一個實施例中，第一子步驟可以使用HBr/O2/Cl2電漿來實現，且第二子步驟可以使用Cl2電漿來實現。
請注意，用於形成該T形閘極電極63的導電層6具有連續的結晶相，因此該T形閘極電極63在使用一段時間後不太可能變形。
在步驟107之後執行步驟108。在步驟108中，該圖案化蝕刻罩7被除去。
在步驟109中，該閘極絕緣體層5進行圖案化，以形成一介於該T形閘極電極63和該圖案化主動區4之間的圖案化閘極絕緣體層51(見圖7)。在一個實施例中，步驟109可以使用基於異向性 氟的乾刻蝕來實現。
在步驟1010中，該T形閘極電極63的上電極部分被摻雜而形成該硼摻雜多晶矽上電極部分62”，並且該圖案化主動區4被摻雜以便在其中且在該T形閘極電極63的相對兩側形成一源極區41和一汲極區42，同時在該源極區41和該汲極區42之間且在該圖案化閘極絕緣體層51的下方形成一通道區43(即，上述半導體通道43)。步驟1010可以通過在一個傾斜角度的As+離子植入來實現。
在一個實施例中，該方法可以在步驟1010之後進一步包括一步驟(圖未示)。在此步驟中，該保護層8形成在該層間介電層3上以覆蓋該T形閘極電極63，使得兩個空氣邊襯64分別形成在該T形閘極電極63的兩個翼部下方。該保護層8可以通過SiO2的濺射或化學氣相沉積來形成。
綜上所述，由上述方法製造的射頻積體電路不僅可以具有精巧的結構，而且具有相對較小的電路面積，以及相對較低的製造成本。另外，該薄膜電晶體9的T形閘極電極63具有連續的結晶相而不易變形。
惟以上所述者，僅為本發明之實施例而已，當不能以此限定本發明實施之範圍，凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。
10:CMOS矽基板
1:CMOS元件
2:矽基材
3:層間介電層
4:圖案化主動區
41:源極區
42:汲極區
43:半導體通道/通道區
51:圖案化閘極絕緣層
63:T形閘極電極
64:空氣邊襯
8:保護層
9:薄膜電晶體

Claims (10)

  1. 一種射頻積體電路，包含：一CMOS矽基板，其中埋置有至少一CMOS元件；至少一薄膜電晶體，形成在該CMOS矽基板上並用作一射頻元件，該薄膜電晶體包括一T形閘極電極；及一保護層，形成在該CMOS矽基板上以覆蓋該T形閘極電極並使得在該T形閘極電極的兩個翼部下方分別形成兩個空氣邊襯；其中，該T形閘極電極包括n+摻雜多晶矽下電極部分和硼摻雜多晶矽上電極部分，該硼摻雜多晶矽上電極部分具有該等翼部並且較寬於該n+摻雜多晶矽下電極部分。
  2. 如請求項1所述的射頻積體電路，其中，該薄膜電晶體具有一半導體通道。
  3. 如請求項2所述的射頻積體電路，其中，該半導體通道是由選自多晶矽、ZnO、IGZO和ZnON的材料製成。
  4. 一種用於製造一射頻積體電路的方法，包含以下步驟：(A)在一矽基材中形成至少一CMOS元件；(B)在該矽基材上形成一層間介電層，以覆蓋該至少一CMOS元件；(C)在該層間介電層上形成一圖案化主動區；(D)在該層間電介質層上形成一閘極絕緣層，以覆蓋該圖案化主動區；(E)在該閘極絕緣體層上形成一導電層，該導電層包括一貼附至該閘極絕緣體層的下導電子層、及一堆疊在該 下導電子層上的上導電子層，該上導電子層是由不同於該下導電子層的材料製成；(F)在該導電層上的對應於該圖案化主動區的位置形成一圖案化蝕刻罩；(G)對從該圖案化蝕刻罩暴露出的該導電層進行蝕刻，以形成一T形閘極電極；(H)在步驟(G)之後，除去該圖案化蝕刻罩；(I)將該閘極絕緣體層圖案化，以形成一介於該T形閘極電極和該圖案化主動區之間的圖案化閘極絕緣體層；及(J)將該T形閘極電極的一上電極部分摻雜，並將該圖案化主動區摻雜以便在其中且在該T形閘極電極的相對兩側形成一源極區和一汲極區，同時在該源極區和該汲極區之間且在該圖案化閘極絕緣體層的下方形成一通道區。
  5. 如請求項4所述的方法，其中，步驟(E)包含以下子步驟：(E1)在該閘極絕緣層上形成一n+摻雜多晶矽層，該n+摻雜多晶矽層具有一上部、及一作為該下導電子層的下部；及(E2)對該上部摻雜硼離子以形成該上導電子層。
  6. 如請求項5所述的方法，其中，步驟(G)包含以下子步驟：(G1)對從該圖案化蝕刻罩暴露出的該導電層進行異向性蝕刻，以在該圖案化蝕刻罩下方形成一圖案化上導電子層和一圖案化下導電子層；及(G2)在子步驟(G1)之後，對該圖案化上導電子層和該圖案化下導電子層進行同向性及側向蝕刻，以形成該T 形閘極電極，其中對於該圖案化下導電子層比對於該上導電子層和該閘極絕緣層具有更高的蝕刻選擇性。
  7. 如請求項6所述的方法，其中，子步驟(G1)是使用HBr/O2/Cl2電漿來實施，且子步驟(G2)是使用Cl2電將來實施。
  8. 如請求項4所述的方法，在步驟(J)之後，還包含步驟：在該層間介電層上形成一保護層以覆蓋該T形閘極電極並使得在該T形閘極電極的兩個翼部下方分別形成兩個空氣邊襯。
  9. 如請求項4所述的方法，其中，該圖案化主動區是由選自由多晶矽、ZnO，、IGZO及ZnON所組成之群組的材料製成。
  10. 如請求項4所述的方法，其中，該圖案化主動區是由多晶矽製成。
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