Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/64—Impedance arrangements
  • H01L23/66—High-frequency adaptations
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
  • H01P3/00—Waveguides; Transmission lines of the waveguide type
  • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L2223/64—Impedance arrangements
  • H01L2223/66—High-frequency adaptations
  • H01L2223/6605—High-frequency electrical connections
  • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
  • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
  • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
  • H01L2224/241—Disposition
  • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01078—Platinum [Pt]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
  • H01L2924/097—Glass-ceramics, e.g. devitrified glass
  • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1903—Structure including wave guides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board

Definitions

• This invention relates generally to electronics, and relates more particularly to electronic components having current-carrying structures and methods of manufacture.
• Electrically conductive materials such as copper, gold, aluminum, tin, and silver are characterized by high conductivity and low loss of electron flow. Such electrically conductive materials are thus often selected as the material for current-carrying structures such as interconnect structures within electronic components, interconnect structures between electronic components, and passive devices within electronic components. Examples of interconnect structures within an electronic component include single-level metal systems and multi-level metal systems. Examples of interconnect structures between electronic components include wire bonds, and examples of passive devices include inductors, resistors, and transformers.
• Current-carrying structures are often operated at high frequencies of greater than approximately one gigahertz (GHz). At these high frequencies, however, the distribution of current or electron transmission through a current-carrying structure is compromised by a skin effect.
• the skin effect crowds the electrons toward an outside skin of the current- carrying structure and effectively decreases a cross-sectional current-carrying area of the current-carrying structure. The skin effect thus acts as a drag on energy efficiency and electron transmission in current-carrying structures.
• wire bonds have an inductive loss and an impedance.
• a high loss in a wire bond significantly affects the ability of the wire bond to carry a signal, particularly at high frequencies. Therefore, a wire bond with high loss greatly limits the distance across which the wire bond may be used as an interconnect structure between components.
• multiple ground wire bonds may be added to an electronic component, the impedance of a wire bond with such multiple ground wire bonds is not easy to control.
• the above-described skin effect and impedance problems may be reduced by increasing a surface area per unit of distance in current-carrying structures, thus increasing a current-carrying cross-section in such structures and planar controlled impedance configurations.
• a wider metal layer can be used to achieve this increase in current-carrying cross section, but at a significant cost of increased component size, particulai y a larger footprint. Therefore, a need exists for an electronic component having a current-carrying structure with an increased current-carrying cross-section while a footprint of the electronic component does not increase in size.
• FIG. 1 is an isometric view of a cross section of a portion of a current-carrying structure according to an embodiment of the present invention
• FIG. 2 is an isometric view of a cross section of a portion of a current-carrying structure according to another embodiment of the present invention
• FIG. 3 is an isometric view of a cross section of a portion of a current-carrying structure according to another embodiment of the present invention.
• FIG. 4 is an isometric view of a cross section of a portion of a transmission line according to another embodiment of the present invention.
• FIG. 5 is a cross-sectional view of a portion of a component-carrying structure having a current-carrying structure coupling together two chip components according to another embodiment of the present invention
• FIG. 6 is a flow chart illustrating a method of manufacturing an electronic component according to an embodiment of the present invention
• FIG. 7 is an isometric view of a cross section of a portion of ,a current-carrying structure according to another embodiment of the present invention.
• FIG. 8 is an isometric view of a cross section of a portion of a current-carrying structure according to another embodiment of the present invention.
• the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention.
• elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention.
• the same reference numerals in different figures denote the same elements.
• a current-carrying structure comprises a first electrically conductive layer and a second electrically conductive layer in contact with the first electrically conductive layer along substantially the entire length of the first electrically conductive layer.
• the second electrically conductive layer is above the first electrically conductive layer.
• a non-electrically conductive layer is in contact with the first electrically conductive layer and the second electrically conductive layer along substantially the entire length of the first and second electrically conductive layers.
• a current travels simultaneously through the first electrically conductive layer and the second electrically conductive layer.
• an electronic component configured according to an embodiment of the invention comprises a current-carrying structure 100 comprising an electrically conductive layer 110 and an electrically conductive layer 120 above electrically conductive layer 110.
• This stacked configuration permits current-carrying structure 100 to have an increased current-carrying cross section by increasing the surface area of current-carrying structure 100 without increasing a footprint of current-carrying structure 100 over its supporting substrate.
• Current-carrying structure 100 may be used to form inter-chip as well as intra-chip connections, and may be formed over a wafer, including silicon and gallium arsenide (GaAs) wafers, or over a module or substrate such as that formed by high-density interconnect (HDI) organic, glass, ceramic, and Chip- Inlay surface structures.
• a Chip-Inlay surface structure is illustrated in FIG. 5.
• Current-carrying structure 100 may also be formed on a printed circuit board. The formation may be accomplished by known processes, including sputter and/or evaporative depositions with photolithographic and etch processing, stencil printing, and electroplating.
• Electrically conductive layer 110 may be comprised of one or more first electrically conductive materials
• electrically conductive layer 120 may be comprised of one or more second electrically conductive materials.
• the first and second electrically conductive materials may comprise the same or different conductive materials.
• electrically conductive layers 110 and 120 may comprise copper, gold, silver, aluminum, tin and/or another metal. Alternatively, they may comprise doped silicon or electrically conductive adhesive.
• electrically conductive material for electrically conductive layers 110 and 120 may be chosen based on, among other factors, the environment in which electrically conductive layers 110 and 120 will be placed.
• electrically conductive layer 110 may be adjacent to a first layer having adhesion properties different from those characterizing a second layer adjacent to electrically conductive layer 120.
• the material forming electrically conductive layers 110 and 120 could be chosen so as to represent a good match, both in terms of adhesion and other properties, with their respective adjacent layers.
• Electrically conductive layer 120 is electrically coupled to electrically conductive layer 110.
• electrically conductive layer 120 can be contiguous with and contacts electrically conductive layer 110 along substantially the entire length of electrically conductive layer 110.
• a conductor-conductor boundary 150 between electrically conductive layer 110 and electrically conductive layer 120 comprises a substantially smooth and continuous boundary with substantially no gaps therewithin.
• Electrically conductive layer 110 is a symmetric structure, and electrically conductive layer 120 is also a symmetric structure.
• a non-electrically conductive layer 130 is contiguous with and contacts electrically conductive layer 110 and electrically conductive layer 120.
• electrically conductive layer 120 forms a concave structure defining a cavity 140 within electrically conductive layer 120.
• Non-electrically conductive layer 130 is located within cavity 140, placing it between electrically conductive layer 110 and electrically conductive layer 120.
• a conductor-dielectric boundary 160 is located between non-electrically conductive layers 130 and electrically conductive layers 110 and 120, and conductor- dielectric boundary 160 provides additional electrically conductive surface area for current- carrying structure 100. The amount of electrically conductive surface area is greater than that which would be available in a conventional, conductor-only configuration for a current- carrying structure.
• conductor-dielectric boundary 160 comprises a substantially smooth and continuous boundary with substantially no gaps therewithin.
• non-electrically conductive layer 130 may comprise one or more non-electrically conductive materials, whether or not the materials are also dielectric materials.
• non-electrically conductive layer 130 may comprise silicon dioxide, silicon nitride, tetraethylorthosilicate, silicon oxynitride, or other low dielectric materials, such as polytetrafluoroethylene, polyimide, benzocyclobutene (BCB), and epoxy.
• Current-carrying structure 100 carries a single current or signal at a time. The current passing through current-carrying structure 100 travels along a long dimension or a length of current-carrying structure 100, as represented by direction "x" in FIG. 1.
• a first portion of the current or signal travels through electrically conductive layer 110 while a second portion of the current or signal travels through electrically conductive layer 120 such that the first and second portions of the current or signal arrive at the same predetermined destination at an end of current-carrying structure 100 at substantially the same time. Accordingly, the current or signal passes or travels simultaneously through electrically conductive layer 110 and electrically conductive layer 120.
• the current or signal passing through a given point in electrically conductive layer 110 passes through a corresponding point in electrically conductive layer 120 at substantially the same time. Furthermore, the current or signal passes through every set of corresponding points within electrically conductive layers 110 and 120 in substantially the same manner.
• Corresponding points in electrically conductive layers 110 and 120 are those points that are substantially equidistant from the location of electrically conductive layers 110 and 120 at which the current was introduced into electrically conductive layers 110 and 120.
• the simultaneous current or signal passage described above is to be distinguished from what is referred to herein as sequential current flow, defined in this description of the invention as a situation in which current does not pass simultaneously through corresponding points of first and second electrically conductive layers.
• Electrically conductive layer 120 comprises a side portion 170 and a side portion 180
• electrically conductive layer 110 comprises a side portion 190 and a side portion 195.
• side portion 170 is contiguous with and contacts side portion 190 along substantially the entire length of electrically conductive layers 110 and 120.
• side portion 180 is contiguous with and contacts side portion 195, also along substantially the entire length of electrically conductive layers 110 and 120.
• a current-carrying structure 200 comprises an electrically conductive layer 210 in addition to electrically conductive layer 110 and electrically conductive layer 120. Electrically conductive layer 210 is separated from electrically conductive layer 120 by a conductor-conductor boundary 250, and is located above electrically conductive layer 120 so as to preserve the benefits realized by maintaining a minimal footprint for current-carrying structure 200. Electrically conductive layer 210 is a symmetric structure and has a cavity 240.
• Current-carrying structure 200 further comprises a non-electrically conductive layer 230 in cavity 240, in contact with electrically conductive layers 210 and 120, and forming a conductor-dielectric boundary 260 between non- electrically conductive layer 230 and electrically conductive layers 120 and 210.
• Non-electrically conductive layer 230 may comprise the same or a different material(s) as the material for non-electrically conductive layer 130, and electrically conductive layer 210 may comprise the same or a different material(s) as the material for electrically conductive layers 110 and/or 120.
• Conductor-conductor boundary 250 and conductor-dielectric boundary 260 are substantially similar to conductor-conductor boundary 150 and conductor-dielectric boundary 160, respectively.
• current- carrying structure 200 may comprise additional electrically conductive layers and non- electrically conductive layers, not shown, for various applications. Considerations such as cost, vertical or height constraints, and manufacturing capabilities, among others, may determine the number of electrically conductive layers and non-electrically conductive layers in a current-carrying structure of an electronic component.
• FIG. 3 depicts an alternate embodiment of a current-carrying structure.
• a current- carrying structure 300 in FIG. 3 comprises electrically conductive layers 310 and 320 in contact with a non-electrically conductive layer 330 and forming conductor-conductor boundary 350 and conductor-dielectric boundary 360.
• Non-electrically conductive layer 330 is located in a recess 340 of electrically conductive layer 320.
• Electrically conductive layer 310 is symmetric, while electrically conductive layer 320 is asymmetric to form a backwards "C" shape for current-carrying structure 300.
• Electrically conductive layer 310 includes side portions 390 and 395, and electrically conductive layer 320 includes side portions 370 and 380.
• Side portion 370 is contiguous with and contacts side portion 390 along substantially the entire length of electrically conductive layers 310 and 320.
• Side portions 380 and 395 are not contiguous with each other and do not contact each other, but each of side portions 380 and 395 are contiguous with and contact non-electrically conductive layer 330 along substantially the entire length of electrically conductive layers 310 and 320.
• current-carrying structure 300 could comprise additional electrically conductive and non-electrically conductive layers to form an "S" or “Z” shape, or current-carrying structure 300 could form other shapes.
• the "S" and “Z” shape embodiments are illustrated in FIGS. 7 and 8, respectively. It will also be understood that in an embodiment with three or more electrically conductive layers and two or more non- electrically conductive layers, each non-electrically conductive layer may extend to either side of the current-carrying structure, without regard for the side to which any other non- electrically conductive layer extends.
• non-electrically conductive layer 330 could extend to the other side of current- carrying structure 300, placing it between side portions 370 and 390 rather than side portions 380 and 395.
• current-carrying structures 100, 200, and 300 in FIGs. 1, 2, and 3, respectively, can be formed upside-down relative to the illustrated orientations.
• FIG. 4 depicts a transmission line 400 according to an embodiment of the invention.
• Transmission line 400 comprises current-carrying structure 300, which serves as a signal line for transmission line 400.
• the current-carrying structure of transmission line 400 can be similar to current-carrying structure 100 or 200 in FIGs. 1 and 2, respectively.
• Transmission line 400 in FIG. 4 further comprises ground lines 440, which in the illustrated embodiment comprises a pair of solid, electrically conductive structures located on both sides of current-carrying structure 300 in a horizontal plane.
• ground lines 440 may comprise a single solid, electrically conductive structure located above, below, or to either side of current- carrying structure 300.
• ground lines 440 may also be similar to current- carrying structures 100, 200, or 300 in FIGs. 1, 2, and 3, respectively.
• the embodiment of transmission line 400 illustrated in FIG. 4, wherein ground lines 440 are located on both sides of current-carrying structure 300 in a horizontal plane, will be referred to herein as a ground-signal-ground structure.
• transmission line 400 may also comprise structures other than the ground-signal-ground structure.
• transmission line 400 in one embodiment, may comprise a current-carrying structure and a single ground line located side-by-side in a horizontal plane.
• transmission line 400 may comprise a current- carrying structure located above a ground line in a vertical plane. This structure is referred to herein as a microstrip configuration.
• Other embodiments of transmission line 400 may also be possible.
• the current-carrying structure of FIGs. 1, 2, 3, and 4 may also be incorporated, individually or collectively, into a multi-level interconnect system used, for example, in conjunction with an integrated circuit (IC).
• IC integrated circuit
• only the uppermost level of the multi-level interconnect system will comprise a current-carrying structure similar to that described with reference to FIGs. 1, 2, 3, or 4.
• this uppermost level is comprised of longer electrically conductive segments than are in the lower levels, increasing the need for an increased current-carrying cross-section.
• additional levels or all the levels of a multi-level interconnect system may comprise such current-carrying structures.
• the current-carrying structures of FIGs. 1, 2, 3, and 4 may additionally be used to form a current-carrying ribbon such as that used in tape automated bonding (TAB).
• TAB tape automated bonding
• an electronic component 500 comprises a device or electronic component 510 and a device or electronic component 520 coupled together by current-carrying structure 100.
• Electronic component 500 is an example of what is referred to herein as a Chip-Inlay surface structure.
• Current-carrying structure 100 may be coupled to bonding pads 560 attached to electronic components 510 and 520. It will be understood that electronic component 510 and electronic component 520 could, in alternate embodiments, be coupled together by a current-carrying structure having any of the other configurations described herein, including those depicted in FIGs. 1, 2, 3, and 4. Multiple current-carrying structures may be formed simultaneously over component-carrying structure 530.
• electronic component 500 further comprises a substrate or component-carrying structure 530, which comprises a recess 540 and a recess 550. Electric component 510 is located in recess 540, and electronic component 520 is located in recess
• electronic components 510 and 520 can be considered to be "in” component-carrying structure 530.
• electronic components 510 and 520 may each be packaged or unpackaged semiconductor chips.
• electronic component 510 can have an integrated circuit 511 formed in and over a semiconductor substrate, where integrated circuit 511 includes devices such as transistors and also includes a multi -level interconnect system 512.
• electronic component 520 can have an integrated circuit 521 formed in and over a semiconductor substrate, where integrated circuit 521 includes devices such as transistors and also includes a multi-level interconnect system 522.
• Multi-level interconnect systems 512 and 522 can each have one or more of the current-carrying structures of FIGs. 1, 2, 3, and 4. The current-carrying structures of FIGs.
• the inductor formed with the current-carrying structure of FIGs. 1, 2, or 3 need not have the conventional inductor metal layer thickness of approximately ten micrometers. Instead, a conventional metal layer thickness of one or two micrometers may be used.
• FIG. 6 contains a flowchart illustrating a method 600 for manufacturing an electronic component having a current-carrying structure according to an embodiment of the present invention.
• a first step 610 of method 600 is to form a device in a substrate.
• a second step 620 is to form a first electrically conductive layer over the substrate and electrically coupled to the device.
• a third step 630 of method 600 is to form a non-electrically conductive layer in contact with the first electrically conductive layer.
• a fourth step 640 of method 600 is to pattern the non-electrically conductive layer to expose a portion of the first electrically conductive layer.
• a fifth step 650 of method 600 is to form a second electrically conductive layer in contact with the first electrically conductive layer along substantially the entire length of the first electrically conductive layer.
• Method 600 may be applied at various levels of electronic component manufacture.
• method 600 may be applied at the wafer level, which includes silicon and GaAs photoresist processing.
• Method 600 may also be applied at the substrate level, which includes organic, ceramic, glass, and Chip-Inlay surfaces, using, among others, plating, stencil printing, and photoresist processes.
• a current-carrying structure 700 comprises electrically conductive layers 310 and 320 in contact with non-electrically conductive layer 330 and forming conductor-conductor boundary 350 and conductor-dielectric boundary 360.
• Current- carrying structure 700 further comprises an electrically conductive layer 710 in contact with a non-electrically conductive layer 730 and forming a conductor-conductor boundary 750 and a conductor-dielectric boundary 760.
• non- electrically conductive layer 330 and non-electrically conductive layer 730 are located at opposite sides of current-carrying structure 700. Accordingly, as illustrated in FIG. 7, electrically conductive layers 310, 320, and 710 form an "S" shape when current-carrying structure 700 is seen in cross section. Electrically-conductive layer 310 is symmetric, and electrically-conductive layers 320 and 710 are asymmetric. Referring now to FIG. 8, a current-carrying structure 800 comprises a mirror image of current-carrying structure 700 of FIG. 7. Accordingly, electrically conductive layers 310, 320, and 710 form a "Z" shape when current-carrying structure 800 is seen in cross section.
• conductor- conductor boundary 150 and conductor-dielectric boundary 160 in FIG. 1, conductor- conductor boundary 250 and conductor-dielectric boundary 260 in FIG. 2, and conductor- conductor boundary 350 and conductor-dielectiic boundary 340 in FIG. 3 can be discontinuous and can have gaps therewithin. Accordingly, the disclosure of embodiments of the invention is intended to be illustrative of the scope of the invention and is not intended to be limiting.

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• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
• Parts Printed On Printed Circuit Boards (AREA)

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• 2002
  • 2002-09-26 US US10/256,789 patent/US6841736B2/en not_active Expired - Lifetime
• 2003
  • 2003-09-26 AU AU2003277778A patent/AU2003277778A1/en not_active Abandoned
  • 2003-09-26 WO PCT/US2003/030253 patent/WO2004032205A2/en not_active Ceased
  • 2003-09-26 KR KR1020057005264A patent/KR20050065558A/ko not_active Ceased
  • 2003-09-26 CN CNB038229692A patent/CN1307653C/zh not_active Expired - Fee Related
  • 2003-09-26 JP JP2004541739A patent/JP2006501682A/ja active Pending
  • 2003-09-26 TW TW092126666A patent/TW200409147A/zh unknown

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