Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
  • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
  • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
  • H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
  • H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
  • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K7/00—Modulating pulses with a continuously-variable modulating signal
  • H03K7/08—Duration or width modulation ; Duty cycle modulation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/04—Differential modulation with several bits, e.g. differential pulse code modulation [DPCM]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/351—Pulse width modulation being used in an amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
  • H03M1/504—Analogue/digital converters with intermediate conversion to time interval using pulse width modulation

Definitions

• the invention relates generally to the field of digital amplifiers. More particularly, the invention relates to the processing of pulse modulated signals.
• audio amplifiers have operated in the analog domain. These amplifiers tend to have low power conversion efficiency, and consequently have large size and weight. With the advent of digital technology, particularly digital audio sources, audio amplification began being performed in the digital domain.
• Digital audio amplifiers using pulse width modulation have a higher power conversion efficiency than analog amplifiers, and have a fixed switched frequency.
• PWM pulse width modulation
• digital PWM is quantized and generated by counting cycles of a high speed clock.
• PWM noise shaping loops are used to improve the in-band signal-to-noise ratio (SNR) of quantized PWM signals by forcing the noise produced from quantizing a duty ratio signal to fall out of the frequency band of interest.
• Pulse width modulation based switching amplifiers are often used in full bridge applications with four switches. In such applications, single-sided PWM processing can be utilized and the resulting signal then inverted to create the pair of signals necessary to drive the full bridge power stage.
• U.S. Pat. No. 6,414,613 is one such example.
• a method for full bridge integral noise shaping comprises: receiving a first and a second reference PWM signal; summing the first and second reference PWM signals with a quantization error correction; quantizing the sum into a first and a second output PWM signal; differentially integrating the first and second reference PWM signals and the first and second output PWM signals according to a full bridge integral noise shaping algorithm to obtain the quantization error correction.
• an apparatus for performing a full bridge integral noise shaping quantization of a pulse modulated signal includes: a single-ended to differential conversion circuit; and a full bridge INS quantizer circuit, coupled to the single-ended to differential conversion circuit.
• FIG. 1 is a circuit diagram of a full bridge power stage of an amplifier.
• FIG. 2 is a block diagram of a PWM processing scheme.
• FIG. 3 is a timing diagram of a PWM INS quantization process.
• FIG. 4 is a block diagram of a full bridge INS quantization scheme, representing an embodiment of the invention.
• FIG. 5 is a detailed block diagram of a full bridge INS quantization scheme, representing an embodiment of the invention.
• FIG. 6 is a timing diagram of a vector full bridge INS process, representing an embodiment of the invention.
• FIG. 7 is a simulated power spectral density graph of a vector full bridge INS output signal, representing an embodiment of the invention.
• FIG. 8 is a simulated power spectral density graph with 0.3% mismatch of a vector full bridge INS output signal, representing an embodiment of the invention.
• FIG. 9 is a timing diagram of a complementary full bridge INS process, representing an embodiment of the invention.
• FIG. 10 is a simulated power spectral density graph of a complementary full bridge INS output signal, representing an embodiment of the invention.
• FIG. 11 is a simulated power spectral density graph with 0.3% mismatch of a complementary full bridge INS output signal, representing an embodiment of the invention.
• FIG. 12 is a simulated power spectral density graph with 1% mismatch of a complementary full bridge INS output signal, representing an embodiment of the invention.
• FIG. 13 is a timing diagram of a shifted reference full bridge INS process operating at twice the switching frequency, representing an embodiment of the invention.
• FIG. 14 is a simulated power spectral density graph of a shifted reference full bridge INS output signal operating at twice the switching frequency, representing an embodiment of the invention.
• FIG. 15 is a timing diagram of a shifted reference full bridge INS process operating at four times the switching frequency, representing an embodiment of the invention.
• FIG. 16 is a simulated power spectral density graph of a shifted reference full bridge INS output signal operating at four times the switching frequency, representing an embodiment of the invention.
• FIG. 17 is a simulated output spectrum graph of a single-ended INS output signal.
• FIG. 18 is a simulated output spectrum graph of a full bridge INS output signal, representing an embodiment of the invention.
• FIG. 1 a circuit diagram of a prior-art full bridge power stage 100 amplifier is depicted.
• FET field effect transistors
• PWM pulse width modulated
• PDM pulse density modulated signals
• PWM processing includes quantization and noise shaping. In the prior art, this processing is done based on a single-sided or halfbridge application. In a typical full bridge application, single-sided PWM processing is utilized and the resulting signal is then inverted, thereby creating the two differential driving signals necessary to drive the pair of inputs to the full bridge power stage.
• FIG. 2 a block diagram of a prior art PWM processing scheme is depicted.
• An unquantized PWM signal 200 is processed by an integral noise shaping (INS) quantizer 201, yielding a quantized PWM signal 202.
• the quantized PWM signal 202 is further processed by a single-ended to differential conversion block 203, outputting a pair of differential quantized full bridge PWM signals 204, which can together drive the full bridge power stage 100 coupled to the load 106.
• INS integral noise shaping
• the INS quantizer 201 includes PWM noise shaping loops which are used to improve the in-band signal-to-noise ratio of quantized PWM signals.
• the input to the loop is a high resolution digital signal which represents a series of duty ratios.
• the output of the loop is a lower resolution digital signal representing a similar series of duty ratios.
• a noise shaping loop can force the noise (error) produced from quantizing the duty ratio signal to remain outside of the spectrum of interest.
• Noise shaping can provide a data directed adjustment to the quantized output sample based on a previously accumulated quantization error.
• FIG. 3 a timing diagram 300 of a prior art PWM INS quantization process is depicted.
• the unquantized PWM signal X(t) 200 is integral noise shaped by the INS quantizer 201 detailed in FIG. 2, yielding the quantized PWM signal Y(t) 202.
• Times of interest include: (n-l)Ts, (n-l/2)Ts, nTs, (n+l/2)Ts, and (n+l)Ts, where Ts is a switching period and n is an integer.
• an INS algorithm can compute an integral feedback of the noise between quantized Y(t) 202 and unquantized X(t) 200 PWM signals.
• An integral term is used to shape the quantization noise. It is possible to integrate PWM waveforms analytically to any order and to quantize rising and falling edges of PWM using the same integral loop. For example, a fourth order system can be used to integrate the error between input X(t) 200
• Equations 1-4 compute the first through fourth order integrals of the error due to quantization of the PWM signal, which can be split into a left half-cycle (/) and a right half- cycle (r). Still referring to FIG. 3, the integrals (Ii, I 2 , 1 3 , and Lt) are defined at discrete time intervals and may be computed analytically.
• Equations 5-8 compute the first through fourth order integrals of the error due to quantization for the left half-cycle of the PWM signal.
• Equations 9-12 compute the first through fourth order integrals of the error due to quantization for the right half-cycle of the
• K values correspond to weighting factors of the multiple integrators of noise shaping filters.
• the present invention includes a method and/or apparatus for full bridge integral noise shaping (INS) for quantization of PWM.
• the invention includes a family of INS algorithms that quantize PWM signals to produce two distinct PWM waveforms.
• full bridge PWM processing may improve signal-to-noise ratio (SNR) and reduce the requirements for the crystal reference clock frequency, output LC filtering, matching in the power stage, and matching in the reference path. It may also allow a lower switching frequency.
• SNR signal-to-noise ratio
• FIG. 4 a block diagram of a full bridge INS quantization scheme is depicted according to one embodiment of the invention.
• the unquantized signal 200 is processed by the single-ended to differential conversion block 203, yielding a first and a second reference (differential unquantized) PWM signal 401 and 402.
• the single-ended to differential conversion block 203 may also suppress a carrier signal if one is present in unquantized signal 200.
• the pair of reference signals 401 and 402 is further processed by a
• full bridge INS quantizer block 403 yielding a first and a second quantized full bridge PWM signal 404 and 405, which may drive the full bridge power stage 100 coupled to the load 106.
• each of the pair of reference signals 401 and 402 may be quantized by a distinct INS operation, resulting in the pair of distinct quantized full bridge
• the pair of PWM signals provide additional switching edges which provide additional samples, and thus the opportunity to increase performance.
• the invention provides a pair of distinct quantized full bridge PWM signals 404 and 405 which have complementary duty ratios.
• the invention provides a method and apparatus for performing an INS operation at least twice each switching period.
• a pulse code modulated (PCM) signal 500 is input into a natural sampler 501, which outputs the single-ended PWM signal 200.
• the single-ended PWM signal 200 is
• the single-ended to differential converter 203 may also suppress a carrier if necessary.
• the pair of reference PWM signals 401 and 402 is further processed by a summation and quantization block 502 of the full bridge INS quantizer 403, resulting in the first output PWM signal 404 and the second output
• the pair of output PWM signals 404 and 405 may be used to drive the first and second sides of a full bridge power stage 100.
• a differential integration block 503 of the full bridge INS quantizer 403 receives the pair of reference PWM signals 401 and 402 and the pair of output PWM signals 404 and 405, calculates a quantization error correction 504, and feeds it to the summation and quantization block 502. Still referring to FIG. 5, the differential integration block 503 may perform independent differential integration operations utilizing the first and second reference PWM signals 401 and 402, and the first and second output PWM signals 404 and 405. The differential integration block 503 may also calculate quantization error correction values 504, which are added to the first and second reference PWM signals 401 and 402 by the summation and quantization block 502 to reduce quantization noise.
• two output PWM signals 404 and 405 are produced as a function of two reference PWM signals 401 and 402 through the operation of summation and quantization block 502 and differential integration block 503 using quantization error correction 504 through an algorithm referred to herein as a full bridge integral noise shaping algorithm.
• a full bridge integral noise shaping algorithm Specific examples of the full bridge integral noise shaping algorithm are presented below with reference to examples 1-4.
• a vector full bridge INS algorithm produces a first and second output PWM signals which are allowed to be completely different from each other.
• Each output full bridge PWM signal may drive one side of the full bridge power stage 100 detailed in FIG. 1, i.e., independent duty ratios can be applied to each half of the full bridge power stage 100.
• FIG. 6 a timing diagram of a vector full bridge INS process 600 is depicted.
• the vertical axis represents the signals 401A, 402A, 404A, and 405A, while the horizontal axis represents time. Times of interest include (2n-l)Ts/2, (2n)Ts/2, and
• the pair of reference PWM signals 401A and 402A is applied to the full bridge INS quantizer 403 detailed in FIG. 4, which outputs the pair of output PWM signals 404A and 405A.
• the negative reference signal 402A is a delayed and inverted version of positive reference signal 401A.
• the vector full bridge INS algorithm is as follows:
• z 2 xr 2 - (k x I x + k 2 I 2 + k 3 I 3 + k 4 ) + (y x - z x ) Equ. 2 1
• Equations 17 and 18 establish a relationship between right half-cycles of the pair of reference PWM signals 401A and 402A.
• Equations 19 and 21 define corrected duty ratios for the pair of output PWM signals 404A and 405A as a function of both reference PWM signals 401A and 402A, wherein k values correspond to weighting factors.
• the operations indicated by equations 19-22 are performed by the differential integration block 503 and the summation and quantization block 502, both detailed in FIG.5.
• I x I X +(l-y 1 )-(l-xr 1 )-(l-y 2 ) + (l-jcr 2 ) Equ.26
• Equations 27 and 28 establish a relationship between left half-cycles (/) of the pair of
• I 3 I 3 +I 2 + /, ( ' 2 ) 3 ⁇ + , (y 2 ⁇ + , • ) 3 (? ⁇ )
• a computer simulated power spectral density graph 700 of a vector full bridge INS output signal is depicted.
• the input is a 15 kHz full scale tone.
• Graph 700 is the result of a vector full bridge INS application with no mismatch between the two sides of the power stage 100 as detailed in FIG. 1.
• the vertical axis represents the magnitude (dB) of the differential signal applied to the load 106, and the horizontal axis represents frequency (xlO 4 ) of the signal.
• FIG. 8 a computer simulated power spectral density graph with 0.3% mismatch 800 of a vector full bridge INS output signal is depicted.
• Graph 800 is the result of another vector full bridge INS application, now with 0.3% mismatch between the two sides of the power stage 100, as detailed in FIG. 1.
• the vertical axis represents the magnitude (dB) of the differential signal applied to the load 106, and the horizontal axis represents frequency (xlO Hz) of the signal. Note that the noise level is significantly elevated compared to that of FIG. 7.
• a mismatch of 0.3% is representative of what one might find in an integrated power stage.
• Complementary Full Bridge INS describes an alternate embodiment that is more tolerant of power stage mismatch.
• a complementary full bridge INS algorithm produces a first and second output PWM signals which have complementary duty ratios.
• Each output full bridge PWM signal may drive one side of a full bridge power stage 100 detailed in FIG. 1, i.e., complementary duty ratios can be applied to each half of the full bridge power stage 100.
• FIG. 9 a timing diagram of a complementary full bridge INS process 900 is depicted.
• the vertical axis represents the signals 401B, 402B, 404B, and 405B, while the horizontal axis represents time. Times of interest include (2n-l)Ts/2, (2n)Ts/2, and (2j ⁇ +l)Ts/2, where n is an integer and Ts is the switching period.
• the pair of reference PWM signals 401B, 402B is applied to the full bridge INS quantizer 403 detailed in FIG. 4, which outputs the pair of output PWM signals 404B and 405B.
• a reference to a double-sided ramp sampling signal 910 used within a natural sampling circuitry 501 detailed in FIG.5 is made.
• the complementary full bridge INS algorithm is as follows:
• Equations 37 and 38 establish a relationship between right half-cycles of the pair of
• Equation 39 defines corrected duty ratio for the
• Equations 46 and 47 establish a relationship between left half-cycles of the pair of reference PWM signals 401B and 402B.
• Equ.54 The integrals depicted in equations 51-54 are performed by the differential integrator 503 detailed in FIG. 5, and provide quantization error correction 504. Referring to FIGS.
• Graph 1000 refers to a complementary full bridge INS application with no mismatch between the two sides of the
• Graph 1100 refers to a complementary full bridge INS application with 0.3% mismatch between the two sides of the power stage. Note that the degradation in signal-to-noise due to 0.3% mismatch is not significant.
• Graph 1200 refers to a complementary full bridge INS application with 1% mismatch between the two sides of the power stage. In this case the signal- to-noise ratio degradation due to mismatch is increased, but the result may still be acceptable for many applications.
• a shifted full bridge INS algorithm sampling at twice the switching frequency produces a first and second output PWM signals.
• Each output full bridge PWM signal may have an independent duty ratio, and each can drive one side of a full bridge power stage 100 detailed in FIG. 1.
• a timing diagram of a shifted full bridge INS process 1700 is depicted.
• the vertical axis represents the signals 401C, 402C, 404C, and 405C, while the horizontal axis represents time. Times of interest include (2n-l)Ts/2, (2n-l+xr)Ts/2, (2n)Ts/2, (2n+l-xl)Ts/2, and (2n+l)Ts/2; where n is an integer and Ts is the switching period.
• the first reference PWM signal 401C is advanced by dTs/2 relative to the single-ended PWM signal 200, and the second reference PWM signal 402C is delayed by dTs/2 relative to the single-
• PWM signal 200 where d is a constant. Note that, at the times of interest, PWM signals 404C and 405C will not go through a switching transition for all possible inputs. Within each switching period Ts there exists four such times. In the previous examples there are only two such times in a switching period Ts.
• the pair of reference PWM signals 401C and 402C is applied to the full bridge INS quantizer 403 detailed in FIG. 4, which outputs the pair of output PWM signals 404C and 405C. Reference to a double-sided ramp sampling signal 1710 used within a natural sampling circuitry 501 detailed in FIG. 5 is made.
• Equations 55 and 56 establish a relationship between right half-cycles of the pair of reference PWM signals 401C and 402C.
• Equation 57 defines corrected duty ratio for the output PWM signal 404C as a function of one of the pair of reference PWM signals 401C and 402C, wherein k values correspond to weighting factors.
• Equations 64 and 65 establish a relationship between left half-cycles of the pair of reference PWM signals 401C and 402C.
• a simulated power spectral density graph 1800 of a shifted reference full bridge INS signal at twice the switching frequency is depicted.
• the vertical axis represents the magnitude (dB) of the differential signal applied to the load 106 detailed in FIG. 1, and the horizontal axis represents frequency (xlO Hz) of the signal.
• the noise floor of graph 1800 is somewhat elevated compared to that of graph 1000 in FIG. 10.
• a shifted full bridge INS algorithm sampling at four times the switching frequency produces a first and second output PWM signals.
• Each output full bridge PWM signal has a completely independent duty ratio, and each may drive one side of a full bridge power stage 100 detailed in FIG. 1.
• a timing diagram of a shifted full bridge INS process 1900 is depicted.
• the vertical axis represents the signals 401D, 402D, 404D, and 405D, while the horizontal axis represents time.
• Times of interest include (2n-l)Ts/2, (2n-l+xr)Ts/2, (2n)Ts/2, (2n+l- ⁇ l)Ts/2, and (2n+l)Ts/2; where n is an integer and Ts is the switching period.
• the first reference PWM signal 401D is advanced by dTs/2 relative to the single-ended PWM signal 200, and the second reference PWM signal 402D is delayed by dTs/2 relative to the single-
• PWM signal 200 where d is a constant.
• the pair of reference PWM signals 401D and 402D is applied to the full bridge INS quantizer 403 detailed in FIG.4, which outputs the pair of output PWM signals 404D and 405D.
• Reference to a double-sided ramp sampling signal 1910 used within a natural sampling circuitry 501 detailed in FIG.5 is made.
• a third- order shifted full bridge INS algorithm sampling at four times the switching frequency is as follows:
• I T2 I T2 + . I /x (xr ⁇ ) + ⁇ (xr-xr) 2 Equ.77
• I x I +(l-xl 2 )-(l ⁇ y 2 ) Equ.96
• Equations 74, 80, 86, and 92 define corrected duty ratio for the output PWM signal
• equations 73-75, 79-81, 85-87, and 91-93 are performed by the differential integration block 503 and the summation and quantization block 502, both detailed in FIG.5.
• the integrals depicted in equations 76-78, 82-84, 88-90, and 94-96 are performed by the differential integrator 503, also detailed in FIG.5 and provide quantization and error correction 504..
• FIG.16 a simulated power spectral density graph 2000 of a third-order shifted reference full bridge INS signal at four times the switching frequency is depicted. Note that for the third-order example illustrated in FIG.16, the noise spectrum has nulls at dc and 16 kHz. The input is a full scale tone at 14 kHz. By sampling at four times the switching frequency, this algorithm allows one to lower the switching frequency without degrading performance.
• FIG. 17 a simulated output spectrum graph of a prior-art single-ended INS output signal 2100 is depicted. This simulation corresponds to the block diagram detailed in FIG. 2.
• FIG. 18 a simulated output spectrum graph of a full bridge INS output signal 2200 according to one aspect of the invention is depicted. This simulation corresponds to the block diagram detailed in FIG. 4, utilizing a Complementary Full Bridge INS algorithm of fourth order such as the one detailed in example 2.
• the vertical axis shows the magnitude of the output signal in dB and the horizontal axis shows the frequency of the signal up to 500kHz.
• the passband is from dc to 20kHz and the noise has been minimized in this region.
• the signal is a full scale signal at 15kHz.
• the switching frequency is 375kHz. Still referring to FIGS. 17
• the full bridge INS output signal 2200 was obtained under the same conditions as the prior-art single-ended INS output signal 2100, but the full scale tone at the switching frequency has been suppressed.
• This improvement over the prior art allows reducing the requirements for a passive L-C low pass filter, which is usually utilized between the power stage and the load.
• the invention includes a method and/or apparatus for full bridge integral noise shaping for quantization of PWM signals.
• the invention includes a plurality of algorithms for performing full bridge integral noise shaping operations.
• the methods contained herein may be implemented via hardware (for example, via an application specific integrated circuit), or via software.
• Certain embodiments of the invention allow the sample rate to be at least doubled, thus allowing higher performance and/or lower switching frequency.
• the invention includes applications ranging from non-audio amplifiers to motion control.
• a or an, as used herein, are defined as one or more than one.
• the term plurality, as used herein, is defined as two or more than two.
• the term another, as used herein, is defined as at least a second or more.
• the terms including and/or having, as used herein, are defined as comprising (i.e., open language).
• the term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
• program or software, as used herein, is defined as a sequence of instructions designed for execution on a computer system.
• a program, or computer program may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.
• the phrase any integer derivable therein, as used herein, is defined as an integer between the corresponding numbers recited in the specification, and the phrase any range derivable therein is defined as any range within such corresponding numbers.

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• 2002
  • 2002-09-26 US US10/255,213 patent/US7142597B2/en not_active Expired - Fee Related
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