WO2004029982A3 - Beschleunigung der programmierung eines speicherbausteins mit hilfe eines boundary scan (bscan)-registers - Google Patents

Beschleunigung der programmierung eines speicherbausteins mit hilfe eines boundary scan (bscan)-registers Download PDF

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Publication number
WO2004029982A3
WO2004029982A3 PCT/DE2003/002932 DE0302932W WO2004029982A3 WO 2004029982 A3 WO2004029982 A3 WO 2004029982A3 DE 0302932 W DE0302932 W DE 0302932W WO 2004029982 A3 WO2004029982 A3 WO 2004029982A3
Authority
WO
WIPO (PCT)
Prior art keywords
write
enable signal
bscan
memory module
low
Prior art date
Application number
PCT/DE2003/002932
Other languages
English (en)
French (fr)
Other versions
WO2004029982A2 (de
Inventor
Karlheinz Krause
Elke Tiemeyer
Original Assignee
Siemens Ag
Karlheinz Krause
Elke Tiemeyer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Karlheinz Krause, Elke Tiemeyer filed Critical Siemens Ag
Priority to US10/529,331 priority Critical patent/US7173840B2/en
Priority to EP03798062A priority patent/EP1543528A2/de
Publication of WO2004029982A2 publication Critical patent/WO2004029982A2/de
Publication of WO2004029982A3 publication Critical patent/WO2004029982A3/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

Landscapes

  • Read Only Memory (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Zur Programmierung eines Speicherbausteins (104) werden einzelne seiner Eingänge (CS, OE, WR, ADDR, DATA) über interne Speicherzellen (103) eines sogenannten Boundary Scan (BSCAN)-Registers (102) stimuliert, welches als IC bzw. ASIC realisiert ist. Zur Aktivierung bzw. Deaktivierung einer Schreiboperation wird dabei ausschließlich der für die Generierung eines WRITE ENABLE-Signals (301d) zuständige Steuersignaleingang (WR) des Speicherbaussteins (104) angesteuert. Das Umschalten des WRITE ENABLE-Signals (301d) von 'LOW'- auf 'HIGH'-Potenzial und umgekehrt erfolgt dabei in Abhängigkeit von zwei JTAG-Instruktionen (WR L, WR H) einer Instruktionssequenz (301a), welche am Setzsignal- bzw. Rücksetzsignaleingang eines Update-Flipflops (108) der für die Generierung des WRITE ENABLE-Signals zuständigen Speicherzelle (103) für die Erzeugung eines 'LOW'- bzw. eines 'HIGH'-Pegels sorgt. Durch eine geeignete Modifikation der Steuereinheit (106) und der BSCAN-Zelle (103), die das WRITE ENABLE-Signal (301d) am WR-Eingang des Speicherbausteins (104) stimuliert, kann die Programmierung beschleunigt werden, ohne die Schnittstelle zwischen Steuereinheit (106) und BSCAN-Register (102) auf Board- und Equipment-Ebene erweitern zu müssen. In einem weiteren Ausführungsbeispiel der vorliegenden Erfindung wird von einer Steuereinheit (106) das Umschalten des WRITE ENABLE-Signals (301d) von 'LOW'- auf 'HIGH'-Potenzial bzw. von 'HIGH'- auf 'LOW'-Potenzial zu einem geeigneten, ggf. programmierbaren Zeitpunkt automatisch vorgenommen, indem das Update-Flipflop (108) der für die Erzeugung des WRITE ENABLE-Signals zuständigen Speicherzelle (103) gesetzt bzw. rückgesetzt wird.
PCT/DE2003/002932 2002-09-26 2003-09-03 Beschleunigung der programmierung eines speicherbausteins mit hilfe eines boundary scan (bscan)-registers WO2004029982A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/529,331 US7173840B2 (en) 2002-09-26 2003-09-03 Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register
EP03798062A EP1543528A2 (de) 2002-09-26 2003-09-03 Beschleunigung der programmierung eines speicherbausteins mit hilfe eines boundary scan (bscan)-registers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10244977A DE10244977B4 (de) 2002-09-26 2002-09-26 Beschleunigung der Programmierung eines Speicherbausteins mit Hilfe eines Boundary Scan (BSCAN)-Registers
DE10244977.5 2002-09-26

Publications (2)

Publication Number Publication Date
WO2004029982A2 WO2004029982A2 (de) 2004-04-08
WO2004029982A3 true WO2004029982A3 (de) 2004-05-27

Family

ID=32038185

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/002932 WO2004029982A2 (de) 2002-09-26 2003-09-03 Beschleunigung der programmierung eines speicherbausteins mit hilfe eines boundary scan (bscan)-registers

Country Status (4)

Country Link
US (1) US7173840B2 (de)
EP (1) EP1543528A2 (de)
DE (1) DE10244977B4 (de)
WO (1) WO2004029982A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100591773B1 (ko) * 2004-12-20 2006-06-26 삼성전자주식회사 불휘발성 반도체 메모리 장치 및 그것을 위한 전압 발생회로
US7685380B1 (en) * 2005-06-29 2010-03-23 Xilinx, Inc. Method for using configuration memory for data storage and read operations
KR100746228B1 (ko) * 2006-01-25 2007-08-03 삼성전자주식회사 반도체 메모리 모듈 및 반도체 메모리 장치
KR101593603B1 (ko) * 2009-01-29 2016-02-15 삼성전자주식회사 반도체 장치의 온도 감지 회로

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19833970A1 (de) * 1998-07-28 1999-12-02 Siemens Ag Schnelle Programmierung von Speicherbausteinen über Boundary Scan
US6356107B1 (en) * 1998-05-21 2002-03-12 Lattice Semiconductor Corporation Method and structure dynamic in-system programming

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805794A (en) * 1996-03-28 1998-09-08 Cypress Semiconductor Corp. CPLD serial programming with extra read register
US5841867A (en) * 1996-11-01 1998-11-24 Xilinx, Inc. On-chip programming verification system for PLDs
US7127708B2 (en) * 2002-03-28 2006-10-24 Lucent Technologies Inc. Concurrent in-system programming of programmable devices
DE10244757B3 (de) * 2002-09-25 2004-07-29 Siemens Ag Programmierung eines Speicherbausteins über ein Boundary Scan-Register

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6356107B1 (en) * 1998-05-21 2002-03-12 Lattice Semiconductor Corporation Method and structure dynamic in-system programming
DE19833970A1 (de) * 1998-07-28 1999-12-02 Siemens Ag Schnelle Programmierung von Speicherbausteinen über Boundary Scan

Also Published As

Publication number Publication date
US20060041801A1 (en) 2006-02-23
DE10244977B4 (de) 2004-08-12
US7173840B2 (en) 2007-02-06
DE10244977A1 (de) 2004-04-22
WO2004029982A2 (de) 2004-04-08
EP1543528A2 (de) 2005-06-22

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