WO2004021358A1 - Ensemble memoire, procede de fonctionnement d'un ensemble memoire et procede de fabrication d'un ensemble memoire - Google Patents

Ensemble memoire, procede de fonctionnement d'un ensemble memoire et procede de fabrication d'un ensemble memoire Download PDF

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Publication number
WO2004021358A1
WO2004021358A1 PCT/DE2003/002559 DE0302559W WO2004021358A1 WO 2004021358 A1 WO2004021358 A1 WO 2004021358A1 DE 0302559 W DE0302559 W DE 0302559W WO 2004021358 A1 WO2004021358 A1 WO 2004021358A1
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WO
WIPO (PCT)
Prior art keywords
memory
value
storage
areas
way
Prior art date
Application number
PCT/DE2003/002559
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German (de)
English (en)
Inventor
Franz Hofmann
Michael Specht
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2004021358A1 publication Critical patent/WO2004021358A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Definitions

  • Memory arrangement Method for operating a memory arrangement and method for producing a memory arrangement
  • the invention relates to a memory arrangement, a method for operating a memory arrangement and a method for producing a memory arrangement.
  • a non-volatile memory using Ge x Sb y Te z as a memory area is known from [1], [2]. With the material Ge x Sb y Te z , a phase change can take place between an amorphous and a crystalline phase. With this conversion, the electrical resistance of the
  • FIG. 6 shows a memory cell 600 known from the prior art based on the principle described.
  • Electrode 602 is an arrangement of a heating element 603 and a Ge x Sb y Te z layer 604.
  • a programmable region 605 of the Ge x Sb y Te z layer 604 can be heated to such an extent that a conversion between an amorphous and a crystalline phase is made possible.
  • the programmable area 605 is brought into a crystalline state; if a sufficiently short and strong pulse is applied, the programmable area 605 is brought into an amorphous state. Since the amorphous state has a significantly higher electrical resistance than the crystalline state, by applying a small reading current between the electrodes 601, 602 it can be scanned in which state the programmable area 605 is located as a memory area.
  • the invention is based on the problem of creating a memory cell arrangement with memory cells with variable electrical resistance, in which the integration density is increased and simultaneously sufficiently safe programming is made possible.
  • the memory arrangement according to the invention contains a substrate and a plurality of storage areas formed on and / or in the substrate, each of which is set up in such a way that the electrical resistance of the respective storage area can be selectively adjusted to a first value or to a second value by means of thermal treatment is greater than the first value. Furthermore, the storage arrangement according to the invention has a heat dissipation structure arranged between the storage areas for dissipating heat supplied to one of the storage areas.
  • the invention provides a method for operating a memory arrangement with the features described above, an electrical write signal being applied in accordance with the method, which is set up in such a way that the value of its electrical resistance to the first or the second value is set.
  • Method applied an electrical read signal which is set up in such a way that for a respective Memory area the value of its electrical resistance is detectable.
  • a plurality of memory areas are formed on and / or in a substrate, each of which is set up in such a way that the electrical resistance of the respective memory area is selectively adjusted to a first value or to a second value by means of thermal treatment is adjustable, which is greater than the first value.
  • a heat dissipation structure for dissipating heat supplied to one of the storage areas is arranged between the storage areas.
  • a basic idea of the invention is to arrange a sufficiently good heat-conducting structure between the memory areas of the memory arrangement according to the invention, and thus to prevent undesired heat transfer to a memory cell adjacent to a memory cell to be programmed (or read). This ensures according to the invention that information can be stored or read out sufficiently securely in a memory cell, and that the other memory cells are simultaneously protected against an undesired change in the memory content during a programming or reading process.
  • the heat dissipation structure is clearly a heat bath with a sufficiently large heat capacity so that a high one
  • the storage arrangement according to the invention has the advantage that it can be scaled with increasing integration density, since the energy to be injected is proportional to the volume of a storage area. Furthermore, very good write and read times can be achieved with the memory arrangement, for example much better than with flash memories. Furthermore, very low write and read voltages (of the order of one volt) are sufficient, whereas high voltages of typically 10 volts and more are required for flash memories. This saves energy, the waste heat is reduced and sensitive integrated components are protected against unwanted influences by high electrical voltages.
  • the memory arrangement of the invention can be set up in such a way that an electrical write signal can be selectively applied to each of the storage areas, which is set up in such a way that the value of its electrical resistance for the respective storage area is set to the first or the second value , Alternatively, an electrical read signal can be applied which is set up in such a way that the value of its electrical resistance can be detected for a respective memory area. Particularly when an electrical write signal is applied, sufficiently high electrical currents are required to reprogram the memory content of a memory area. Due to the use of the heat dissipation structure according to the invention, however, memory areas adjacent to a programmable memory area are protected against undesired reprogramming during programming.
  • the heat dissipation structure can be set up in such a way that when the write signal is applied to a respective memory area for setting the value of an electrical resistance, the heat resulting from the write signal is dissipated in such a way that the other memory areas result from a change in their electrical resistance of the write signal are protected.
  • the write signal can be, in particular, an electric current with a predeterminable strength, which can be applied to a respective memory area for a predefinable time.
  • At least some of the storage areas are preferably at least partially surrounded by a heat insulation structure, which is set up in such a way that they have the
  • the heat insulation structure can prevent or at least reduce the heat dissipation from a respective storage area.
  • the amount of heat in the memory area to be reprogrammed is located with sufficient certainty so that the memory area to be reprogrammed can be safely reprogrammed and adjacent memory areas are protected against unwanted programming.
  • the thermal insulation structure due to the functionality of the thermal insulation structure, with short heating pulses (typically 5ns), as are required to generate the state of the storage area with a high electrical resistance, almost all of the heat remains within the selected storage area. With longer heating pulses (typically 100 ns), as are often required to convert the storage area into a state with the low electrical resistance, part of the heat is given off to the heat dissipation structure, the heat structure preferably being set up in such a way that it is only slightly warmed up.
  • short heating pulses typically 5ns
  • 100 ns as are often required to convert the storage area into a state with the low electrical resistance
  • the memory arrangement can be set up in such a way that each of the memory areas can be switched between an amorphous and a crystalline phase (ie in particular a lattice structure), the memory area having the first value in the crystalline phase and the second value of the electrical resistance in the amorphous phase ,
  • the memory areas of the memory arrangement are preferably set up in such a way that the crystalline phase can be set for a first time interval by applying the write signal and that the amorphous phase can be set for a second time interval by applying the write signal, the first time interval being greater than the second time interval.
  • the crystalline phase of the storage area is clearly generated by heating by applying a heating signal for a sufficiently long time (or by cooling it slowly enough).
  • An amorphous phase can be generated by exposing the storage area to a brief heating signal (or cooling it down sufficiently quickly).
  • the storage areas preferably have a chalcogenide material, in particular an alloy Ge x Sb y Te z (germanium, antimony, tellurium). Such materials have the advantage that they can be reprogrammed using sufficiently small electrical currents with short programming times (5ns or 100ns). The difference in the electrical resistances in the two phase states is significant, so that programming and reading of memory information that is robust in error is made possible.
  • typical Values of the electrical resistances of chalcogenide storage areas are in the range of lk ⁇ for the crystalline phase and in the range of lOOk ⁇ for the amorphous phase.
  • any other material can be used, which can be selectively converted into an amorphous or crystalline state by means of tempering.
  • the material combination of crystalline silicon / amorphous silicon is to be mentioned as an example of a further suitable material, which is particularly advantageous for the integrability of the memory arrangement according to the invention into silicon microtechnology.
  • the material of the heat dissipation structure is preferably a metal, polycrystalline silicon or an aluminate (in particular aluminum oxide, Al0 3 ).
  • a metal the advantageous effect can be used that metals typically have a thermal conductivity which is a factor of a hundred greater than that under typical conditions
  • the insulation structure can be set up such that it electrically decouples the associated memory area from the other memory areas.
  • the heat insulation structure can be set up and function not only for heat insulation, but also for electrical decoupling.
  • the thermal insulation structure can be a cavity or it can be made of an electrically insulating material.
  • the heat insulation structure can be made from silicon oxide (Si0 2 ) or silicon nitride (Si 3 N).
  • the storage areas are preferably arranged in a matrix on and / or in the substrate.
  • the heat dissipation structure can surround the storage areas essentially in a lattice shape. Alternatively, the heat dissipation structure can also surround the storage areas in a zigzag, meandering, or other functionally suitable form.
  • a substrate is particularly suitable as a substrate, furthermore in particular a silicon substrate.
  • any other substrate for example glass, ceramic can also be used.
  • At least a part of the storage areas can have a heating element which is thermally conductively coupled to the respective storage area and by means of which the heating element can be coupled
  • Storage area thermal energy can be supplied.
  • a heating element preferably made of a material with a sufficiently high ohmic resistance
  • the heating element can have tungsten and / or polycrystalline silicon.
  • FIG. 1A to 1E layer sequences to different
  • FIG. 2 shows a layout view of a memory arrangement according to the first exemplary embodiment of the invention
  • FIG. 3 shows a cross-sectional view of a memory arrangement according to the first exemplary embodiment of the invention
  • FIG. 4 shows a cross-sectional view of a memory arrangement according to a second exemplary embodiment of the invention
  • Figure 5A is a schematic cross-sectional view of a
  • FIG. 5B shows another schematic cross-sectional view of a memory area of a memory arrangement according to the invention
  • Figure 6 shows a memory cell according to the prior art.
  • FIGS. 1A to 1E A method for producing a memory arrangement according to a first exemplary embodiment of the invention is described below with reference to FIGS. 1A to 1E.
  • This method shows a 6F 2 cell field based in part on the DRAM technology.
  • any other cell array from DRAM technology can be used to apply the invention to this technology.
  • n + -doped regions 102 to 104 are formed in a silicon substrate 101 as first to third source / drain regions. Furthermore, first and second silicon oxide regions 105, 106 are formed in surface regions of the silicon substrate by etching trenches and filling the trenches with silicon oxide material. An electrical decoupling of different memory cells of a memory arrangement to be formed is clearly realized by means of the silicon oxide regions 105, 106. Furthermore, first and second word lines 107, 108 are made of an electrically conductive material on the substrate 101 in regions between the first source / drain region 102 and the second source / drain region 103 and between the second
  • Source / drain region 103 and the third source / drain region 104 are formed, a thin silicon oxide film being formed as a gate insulating layer between the substrate 101 and the word lines 107, 108.
  • a common source / drain region 103 At the second source / drain region 103, a common
  • First and second auxiliary structures 109, 110 are constructed like the word lines 107, 108 and serve to set a self-aligned contact between the lines 108, 110 and 109, 107.
  • the control line 111 can be generated in a self-aligned manner between the word lines 107, 108.
  • the layer sequence thus obtained is encapsulated with silicon oxide material, whereby a silicon oxide encapsulation 112 is formed.
  • a lithography and an etching Process trenches 121 etched into silicon encapsulation 112, thereby exposing the first and third source / drain regions 102, 104. Furthermore, doped polysilicon material is introduced into the trenches 121 and etched back, as a result of which first heating element components 122 are formed. Subsequently, tungsten material is deposited in the trenches 121 on the first heating element components 122, as a result of which second heating element components 123 are formed.
  • chalcogenide material (Ge x Sb y Te z ) is deposited on the surface of the layer sequence 120 and a part of the chalcogenide material is etched back, whereby chalcogenide structures 141 are formed. Silicon oxide material of silicon oxide encapsulation 112 is also etched back.
  • the exposed chalcogenide structures 141 are surrounded by lateral silicon oxide spacers 161 by means of deposition and etching back of silicon oxide material. Furthermore, copper material or aluminum material is deposited on the surface of the layer sequence thus obtained and etched back, as a result of which a copper-metal grid 162 (alternatively an aluminum-metal grid), embedded between adjacent ones, is electrically and thermally conductive from the surroundings by means of the silicon oxide spacers 161 largely decoupled chalcogenide structures 141, is formed. Furthermore, additional silicon oxide material is deposited on the surface of the layer sequence obtained in this way and planarized using a CMP process ("chemical mechanical polishing").
  • CMP process chemical mechanical polishing
  • metal material is deposited on the layer sequence 160 and structured to form a bit line 181 using a lithography and an etching method.
  • the functionality of the memory arrangement 180 according to the first exemplary embodiment of the invention is described below with reference to FIG. 1E.
  • the memory information of the respective memory cell is clearly stored in the phase state of the chalcogenide structures 141.
  • the memory arrangement 180 from FIG. 1E shows two memory cells, belonging to the two chalcogenide structures 141.
  • the chalcogenide structures 141 can each be in a crystalline state in which the electrical resistance of the chalcogenide structures 141 is lower than in an amorphous one Status.
  • a selected chalcogenide structure 141 supported by the heating element components 122, 123, is heated so strongly that depending on the length of the application of the pulse (or depending on the cooling rate and the strength of the pulse) Chalcogenide structures 141 can be selectively brought into the crystalline or amorphous state.
  • the chalcogenide structure 141 By applying a sufficiently long heating signal (typically 100ns), the chalcogenide structure 141 is brought into the crystalline state, by applying a sufficiently short heating signal (typically 5ns), the respective chalcogenide structure 141 is brought into the amorphous state.
  • a sufficiently long heating signal typically 100ns
  • a sufficiently short heating signal typically 5ns
  • the chalcogenide structures 141 are surrounded with the silicon oxide spacers 161 as thermal and electrical insulators. If, which can occur in particular in the case of a longer heating pulse, part of the heat of the chalcogenide structures 141 can pass through the associated silicon oxide spacer 161, this heat is released to the metallic grid 162, which heats up only slightly.
  • the left chalcogenide structure 141 is first selected as the memory cell of the memory arrangement 180 by applying an electrical voltage to the first word line 107, clearly the gate region of a selection transistor, such that the region of the substrate 101 (channel Region) between the first and the second source / drain regions 102, 103 is electrically conductive.
  • the electrical heating signal is conducted through the channel region via the heating element components 122, 123 into the left chalcogenide structure 141, as a result of which the chalcogenide structure 141 is strongly heated.
  • the chalcogenide structure 141 is converted into an amorphous state with a high electrical resistance by means of a sufficiently short heating pulse; with a sufficiently long heating pulse, the chalcogenide structure 141 is converted into a crystalline state with a low ohmic resistance.
  • the heating element components 122, 123 are formed from a sufficiently high-resistance material so that ohmic heat resulting from the heating signal is generated in the heating element components 122, 123, which heat heats the associated chalcogenide structure 141.
  • the crystalline state of the chalcogenide structure 141 with the low value of the ohmic resistance can be assigned a logic value "1"
  • the amorphous state of the chalcogenide structure 141 with the high value of the ohmic resistance can be assigned a logic value "0" be assigned.
  • an electrical voltage is again applied to the first word line 107. that the common drive line 111 is coupled to the bit line 181 via the chalcogenide structure 141. If an electrical read signal (for example a sufficiently small electrical current that does not change the state of the associated chalcogenide structure) is now applied, it flows depending on whether the chalcogenide structure 141 is in the amorphous state with the high ohmic resistance or in the crystalline state State with the low ohmic resistance is on the bit line 181, a large or a smaller electrical current that is detected. In this way, the storage information can be read out.
  • an electrical read signal for example a sufficiently small electrical current that does not change the state of the associated chalcogenide structure
  • FIG. 2 shows that the 6F 2 memory cells 200 of the memory arrangement 180 are arranged in a matrix.
  • F is the minimum structural dimension that can be achieved in a technology generation.
  • the bit lines 181 run along a first direction, whereas the word lines 107, 108 run along a direction orthogonal thereto.
  • the silicon oxide spacers 161 and the metal grid 162 are not shown in FIG.
  • a sectional view 300 of the memory arrangement 180 along a section line I-I 'shown in FIG. 1E is described below with reference to FIG.
  • the memory arrangement 180 contains memory cells with a space requirement of 6F 2 per memory cell, each of the memory cells, as shown in FIG. 3, having a chalcogenide structure 141 and a silicon oxide spacer 161 surrounding them. Each of the memory cells is embedded in the grid-shaped metal grid 162 as a heat dissipation structure.
  • the silicon oxide spacers 161 serve as a heat insulation structure. Particularly in areas 301 of the memory arrangement 180, in which adjacent memory cells are arranged closely adjacent, the provision of the heat dissipation structure and the heat insulation structure is decisive in order to prevent thermal crosstalk between adjacent memory cells.
  • a memory arrangement 400 according to a second exemplary embodiment of the invention is described below with reference to FIG.
  • the memory arrangement 400 essentially corresponds to the memory arrangement 180, but is designed as a memory arrangement with an area requirement of 4F 2 per memory cell, that is to say with an even greater integration density than the memory arrangement 180.
  • the individual memory cells each having a chalcogenide structure 141 and a silicon oxide spacer 161 surrounding them, are in turn embedded in a grid-shaped metal structure 162.
  • the memory cells in the storage arrangement 400 are regularly arranged in a lattice shape, that is to say in the horizontal direction or in the vertical direction at a fixed distance from one another in each case.
  • FIG. 5A shows a cross-sectional view 500
  • FIG. 5B shows a top view 501 of the structure.
  • the height of the cylindrical chalcogenide structure 141 or of the hollow cylindrical silicon oxide spacer 161 is assumed to be 100 nm
  • the diameter of the chalcogenide structure 141 is assumed to be 50 nm
  • the thickness of the hollow cylinder wall of the silicon oxide spacer 161 is assumed to be 10 nm.
  • the volume of the chalcogenide cylinder 141 is 2-10 _22 m 3 .
  • a thickness of the silicon oxide spacers 161 of 10 nm is sufficient for good insulation, since the heat removed in 5 ns is smaller than the heat produced.
  • a programming current of approximately 0.2 mA or more is a good choice.
  • the heating of the surrounding metal 162 is calculated. Under typical operating conditions, metal conducts approximately 100 times better than silicon dioxide. Therefore, a volume roughly 100 times larger than the volume of the chalcogenide structure 141 and the silicon oxide spacer 161 is heated within 100 ns by:
  • a metal absorbs most of the energy without being significantly heated, provided that for each cell to be programmed a metal volume of approximately 100 times the volume of the cell is provided.
  • each cell has a metal volume of approximately 700 times the volume of a cell volume.
  • the proposed layout therefore helps to dissipate the energy from the programming cell into the surrounding area without significantly heating up neighboring cells.

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Abstract

L'invention concerne un ensemble mémoire, un procédé de fonctionnement d'un ensemble mémoire et un procédé de fabrication d'un ensemble mémoire. Cet ensemble mémoire comprend un substrat et une pluralité de zones de mémoire formées sur et/ou dans ce substrat, chacune de ces zones de mémoire étant disposée, de sorte que la résistance électrique de la zone de mémoire respective peut être réglée de manière sélective sur une première valeur ou sur une deuxième valeur supérieure à la première par le biais d'un traitement thermique. De plus, une structure d'évacuation de la chaleur, servant à évacuer une chaleur conduite aux zones de mémoire, est placée entre lesdites zones de mémoire.
PCT/DE2003/002559 2002-08-08 2003-07-30 Ensemble memoire, procede de fonctionnement d'un ensemble memoire et procede de fabrication d'un ensemble memoire WO2004021358A1 (fr)

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DE10236439A DE10236439B3 (de) 2002-08-08 2002-08-08 Speicher-Anordnung, Verfahren zum Betreiben einer Speicher-Anordnung und Verfahren zum Herstellen einer Speicher-Anordnung
DE10236439.7 2002-08-08

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Cited By (4)

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WO2006121473A1 (fr) * 2005-05-06 2006-11-16 International Business Machines Corporation Procede et structure pour memoire a changement de phase controlee de peltier
EP1729355A1 (fr) * 2005-06-03 2006-12-06 STMicroelectronics S.r.l. Procédé auto-aligné de fabrication des cellules de mémoire à changement de phase
US11587890B2 (en) 2020-07-20 2023-02-21 International Business Machines Corporation Tamper-resistant circuit, back-end of the line memory and physical unclonable function for supply chain protection
US11748524B2 (en) 2020-07-20 2023-09-05 International Business Machines Corporation Tamper resistant obfuscation circuit

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DE102005001460B4 (de) * 2005-01-12 2010-01-14 Qimonda Ag Speichervorrichtung und Herstellungsverfahren
US7214958B2 (en) 2005-02-10 2007-05-08 Infineon Technologies Ag Phase change memory cell with high read margin at low power operation
US7348590B2 (en) 2005-02-10 2008-03-25 Infineon Technologies Ag Phase change memory cell with high read margin at low power operation
US7361925B2 (en) 2005-02-10 2008-04-22 Infineon Technologies Ag Integrated circuit having a memory including a low-k dielectric material for thermal isolation
US7601995B2 (en) 2005-10-27 2009-10-13 Infineon Technologies Ag Integrated circuit having resistive memory cells
US7714315B2 (en) 2006-02-07 2010-05-11 Qimonda North America Corp. Thermal isolation of phase change memory cells
DE102006011976A1 (de) * 2006-03-15 2007-09-20 Infineon Technologies Ag Verfahren zum Bilden einer Speichervorrichtung mit einer Vielzahl von Speicherzellen, insbesondere Phasenwechselspeicherzellen, und Speichervorrichtung
EP1845567A1 (fr) * 2006-04-11 2007-10-17 STMicroelectronics S.r.l. Dispositif de mémoire à changement de phase et procédé associé
US7538411B2 (en) 2006-04-26 2009-05-26 Infineon Technologies Ag Integrated circuit including resistivity changing memory cells
US7453081B2 (en) 2006-07-20 2008-11-18 Qimonda North America Corp. Phase change memory cell including nanocomposite insulator
DE102007021761B4 (de) * 2007-05-09 2015-07-16 Adesto Technology Corp., Inc. Widerstandsschaltelement, Speicherbauelemente, Speichermodul, Verfahren zur Herstellung eines resistiven Schaltelements und Verfahren zur Herstellung eines resistiven Speicherbauelements

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WO1998058385A1 (fr) * 1997-06-19 1998-12-23 Energy Conversion Devices, Inc. Element de memoire a mecanisme de regulation d'energie
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006121473A1 (fr) * 2005-05-06 2006-11-16 International Business Machines Corporation Procede et structure pour memoire a changement de phase controlee de peltier
EP1729355A1 (fr) * 2005-06-03 2006-12-06 STMicroelectronics S.r.l. Procédé auto-aligné de fabrication des cellules de mémoire à changement de phase
US7422926B2 (en) 2005-06-03 2008-09-09 Stmicroelectronics S.R.L. Self-aligned process for manufacturing phase change memory cells
US11587890B2 (en) 2020-07-20 2023-02-21 International Business Machines Corporation Tamper-resistant circuit, back-end of the line memory and physical unclonable function for supply chain protection
US11748524B2 (en) 2020-07-20 2023-09-05 International Business Machines Corporation Tamper resistant obfuscation circuit

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TW200405533A (en) 2004-04-01

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