WO2004019606A1 - ビットリダクション装置 - Google Patents
ビットリダクション装置 Download PDFInfo
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- WO2004019606A1 WO2004019606A1 PCT/JP2003/010155 JP0310155W WO2004019606A1 WO 2004019606 A1 WO2004019606 A1 WO 2004019606A1 JP 0310155 W JP0310155 W JP 0310155W WO 2004019606 A1 WO2004019606 A1 WO 2004019606A1
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- WIPO (PCT)
- Prior art keywords
- circuit
- output
- bit
- bit reduction
- bits
- Prior art date
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- 238000007493 shaping process Methods 0.000 claims abstract description 13
- 238000012937 correction Methods 0.000 claims description 30
- 238000000926 separation method Methods 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 238000007689 inspection Methods 0.000 claims 1
- 238000012545 processing Methods 0.000 abstract description 19
- 238000010586 diagram Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 235000019557 luminance Nutrition 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/405—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
- H04N1/4055—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels producing a clustered dots or a size modulated halftone pattern
- H04N1/4057—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels producing a clustered dots or a size modulated halftone pattern the pattern being a mixture of differently sized sub-patterns, e.g. spots having only a few different diameters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0428—Gradation resolution change
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
- H04N21/4318—Generation of visual interfaces for content selection or interaction; Content or additional data rendering by altering the content in the rendering process, e.g. blanking, blurring or masking an image region
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/202—Gamma control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/57—Control of contrast or brightness
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/66—Transforming electric information into light information
Definitions
- the present invention relates to a bit reduction device that reduces the number of bits while maintaining the gradation of a video signal.
- FIG. 5 As an even more general circuit, a bit number reduction circuit using an adder and a delay unit for noise shaving is often used.
- This prior art will be described as a conventional example with reference to FIGS. 5, 6, and 7.
- FIG. 5 This prior art will be described as a conventional example with reference to FIGS. 5, 6, and 7.
- FIG. 5 is a block diagram showing a configuration of a conventional example.
- an image quality correction circuit 500 performs various digital signal processing on an m-bit (m is an integer) input signal applied via an input terminal 520.
- bit processing is performed according to the content of the signal processing so as not to impair the bit precision of the input signal composed of m bits.
- a noise shaving circuit 510 composed of an adder 511 and a delay unit 512 reduces the number of bits, and converts the signal composed of m bits into n bits (where n is an integer). , A value smaller than m).
- Figure 6 shows the situation at that time.
- m 10 and ⁇ is 8 in FIG.
- the value 600 represents the output of the image quality correction circuit 500, and It is assumed that the output of the image quality correction circuit 500 is 30 F in hexadecimal. If the hexadecimal number 30 F is represented by the decimal number, it is 78 3
- the noise shaving circuit 510 converts the lost 2-bit component into a pulse width modulation (PWM) and adds it to the upper bits, thereby reproducing the information of the lower bits in a pseudo manner by the integration effect. Things.
- PWM pulse width modulation
- the adder 511 adds the lower 2 bits of the output of the delay unit 512 to the output of the m-bit image quality correction circuit 500 and then inputs the result to the delay unit 5122.
- PWM processing of the lower bits becomes possible.
- a limiter is generally provided in the subsequent stage because overflow occurs in the adder 5 12.
- the value 6001 shows the evening timing chart after the number of bits is converted to 8 bits by the noise shaving circuit 510.
- the value 6 0 2 is the value
- the value 603 is a timing chart in the next scanning period after the value 602, and the value 604 is a timing chart in the next scanning period after the value 603.
- the 10-bit, 30-F signal is converted to C3, C4, C4, C4, C3, C4, C4, C4, and so on.
- C 3 is 195 in decimal and C 4 is 196. Integrating C3, C4, C4, and C4 yields 19.5.75, which indicates that a precision of 10 bits is simulated.
- FIG. 7 shows a state of an image displayed on the display when the above processing is performed.
- a scanning line 702 is a scanning line next to the scanning line 701
- a scanning line 703 is a scanning line next to the scanning line 702
- Reference numeral 704 denotes a scanning line next to the scanning line 703.
- the value 6 0 1 is the scan line 7 0 1
- the value 6 0 2 is the scan line 7 0 2
- the value 6 0 3 is the scan line 7 0 3
- Numeral 4 denotes scanning lines 704, each of which is displayed.
- the black squares indicate pixels with value “C 3”
- the white squares indicate pixels with value “C 4”. Therefore, pixels having slightly different luminances are mixed. In some cases, the mixed pattern does not change much and approaches a fixed state.
- one pixel such as a large, low-resolution liquid crystal panel, for example, a 20 V type VGA (640 ⁇ 480 dots) resolution is used. If it is large, the PWM component will be seen as beat noise or vertical noise.
- a video signal is a signal that changes every moment, and the PWM component is not so noticeable.
- the PWM component is not so noticeable.
- DC-like "0" is black, which is usually inconspicuous even if noise is added.
- an offset is added to the video signal by the image quality correction circuit 500 (the black level must be increased by user adjustment). Has a problem that the PWM component is visually recognized as noise. Disclosure of the invention
- the bit reduction device is a bit reduction device
- An image quality correction circuit for correcting the image quality of the input video signal
- a first bit reduction section for reducing the number of output bits of the image quality correction circuit
- a second pitch reduction section for reducing the number of bits of the output of the image quality correction circuit
- a discrimination circuit that generates a discrimination signal by using at least a detection result of the synchronization signal of the input video signal as one of the judgment factors
- a first selector which is controlled by the determination circuit and selects one of an output of the first bit reduction unit and an output of the second bit reduction unit
- the first bit reduction unit has a first noise shaving circuit for noise shaving the output of the image quality correction circuit and reducing the number of pits.
- FIG. 1 is a block diagram of the bit reduction device of the present invention.
- FIG. 2 is a block diagram showing a detailed configuration example of the bit reduction device of the present invention.
- FIG. 3 is a block diagram showing another configuration example of a portion for reducing the number of bits in the present invention.
- FIG. 4 is a block diagram showing still another configuration example of a portion for reducing the number of bits in the present invention.
- FIG. 5 is a block diagram showing an example of a conventional bit reduction device.
- FIG. 6 is a timing chart showing the operation of the bit reduction device.
- Fig. 7 shows an image displayed on the display when a conventional bit reduction device is used.
- the bit reduction device of the present invention switches the bit reduction operation based on at least one of the state of the input signal, the setting state of the user, and the setting state of the device. By doing so, the bit reduction device of the present invention can secure the gradation and prevent the occurrence of beat noise, and can solve the above-mentioned problems in the conventional method.
- FIG. 1 is an example of a configuration diagram of a bit reduction device of the present invention.
- an image quality correction circuit 100 corrects the image quality of an input video signal input via a terminal 150.
- the output of the image quality correction circuit 100 is divided into a first noise shaving circuit 110 (hereinafter referred to as a noise shaping circuit 110), which is a first bit reduction unit, and a second bit reduction circuit.
- a noise shaping circuit 110 hereinafter referred to as a noise shaping circuit 110
- the second bit reduction unit 120 is An example is described in which each is configured by a first upper bit selection circuit 122 (hereinafter referred to as an upper bit selection circuit 122).
- the adder 111 adds a predetermined lower-order bit of the output of the delay unit 112 to the output of the image quality correction circuit 100.
- the delay unit 1 1 2 delays the output of the adder 1 1 1.
- the first selector 130 (hereinafter, referred to as a selector 130) uses a predetermined upper bit of the output of the delay unit 112 as a first input, and selects an upper bit selection circuit 1 2 The output of 1 is used as the second input, and either one is selected.
- the discrimination circuit 140 detects the presence / absence of a synchronization signal of the video signal input via the terminal 160, and controls the selector 130 based on the detection result and the like.
- FIG. 1 shows an example in which the discrimination circuit 140 is constituted by a synchronization detection circuit 122.
- the image quality correction circuit 100 executes various digital signal processing on an input signal composed of m bits (m is an integer). At this time, bit processing is performed according to the content of the signal processing so as not to impair the bit precision of the m-bit input signal. For example, when adjusting the black level of an input signal, the black level is adjusted by adding a certain value to the input video signal. It is assumed that the output of the image quality correction circuit 100 maintains the same m-bit accuracy as the input signal.
- the output of the selector 130 is supplied to the subsequent stage via the terminal 170.
- the column is, for example, a liquid crystal panel. If the number of bits that can be obtained is n bits (n is an integer and a value smaller than m), it is necessary to reduce the number of bits somewhere. Therefore, bit reduction is performed by the noise shaving circuit 110 composed of the adder 111 and the delay unit 112 and the upper bit selection circuit 121. That is, a signal composed of m bits is converted into a signal composed of n bits. Since the first bit reduction section 110 is constituted by a noise shaving circuit, it also performs noise shaping. This noise shaving will be described with reference to FIGS.
- m 10 and n is 8, and it is assumed that the output of the image quality correction circuit 100 is 30F in hexadecimal.
- the output of the image quality correction circuit 100 has a value of 600, and the hexadecimal number 30 F is represented by a decimal number of 783. Converting this to 8 bits gives 19.55.75.
- the value 6 0 1, 6 0 2, 6 0 3, 6 0 4 in FIG. 6 has 8 bits due to the noise shaving circuit 1 10 composed of the adder 1 1 1 and the delay 1 1 2.
- the evening timing chart after conversion into bits is shown. Similar to the conventional method described in FIG. 5, the 10-bit, 30-F signal is represented by C3, C4, C4, C4, C3, C4, C4, C4,. It has been converted. That is, the output of the noise shaving circuit 110 is accompanied by the PWM already described.
- C 3 is 1 95 in decimal and C 4 is 196.
- C3, C4, C4, and C4 are integrated, the result is 19.5.75, which indicates that a precision of 10 bits is simulated.
- the input signal is not fixed at 30 F, but changes successively depending on the image content.
- the signal input to the image quality correction circuit 100 includes a quantization error when analog-to-digital conversion is performed, and the input signal is constantly changing. On the other hand, if there is no input signal, it is equivalent to inputting a completely digital "0" signal. If the image quality correction circuit 100 adjusts the black level at this time and outputs 3 OF, the output of the image quality correction circuit 100 is always fixed at 30 F, and the signal after noise shaving is output. Will repeat C 3 and C regularly, in which case it will stand out as noise.
- the synchronization detection circuit 141 constituting the discriminator 140 detects whether there is no input by detecting the presence or absence of synchronization.
- the discriminator 140 controls the selector 130 so that the selector 130 selects the output of the second bit reduction unit 120.
- the second bit reduction section 120 is composed of an upper bit selection circuit 121 that selects only the upper pits of the output of the image quality correction circuit 100. That is, the selector 130 outputs a signal that is not subject to noise shaping. With this configuration, it is possible to achieve both noise at the time of no input and gradation at the time of normal operation.
- FIG. 2 shows a more detailed configuration example of the embodiment of the present invention shown in FIG.
- the portions denoted by the same reference numerals as in FIG. 1 are the same as those in FIG.
- the composite video signal input via terminal 150 is converted to a digital signal by an analog-to-digital converter 210 (referred to as AZD in Fig. 2 and hereinafter referred to as AZD converter 210).
- AZD analog-to-digital converter
- the video decoder 220 converts a digital signal of a composite video signal output from the A / D converter 210 into a digital signal of a component video signal.
- FIG. 2 shows an example in which the image quality correction circuit 100 includes a resolution converter 101, a contrast / brightness adjuster 102, and a key corrector 103.
- the resolution converter 101 converts the resolution of the output of the A / D converter 210.
- the processing includes converting the number of pixels existing in a horizontal scanning period (the number of horizontal pixels) and the number of scanning lines existing in one screen (the number of vertical pixels). This process is necessary to match the configuration of the number of pixels required in the subsequent stage.
- the resolution converter 101 often performs a filtering process in order to prevent image quality degradation as much as possible. In this way, the output of the A / D converter 210 can be adjusted to the number of horizontal pixels and the number of vertical pixels that can be handled by a subsequent circuit, display, or the like.
- the contrast / brightness adjuster 102 converts the value of the video data from the resolution converter 101 to adjust the contrast, brightness, saturation, and the like of the video displayed on the display.
- the key corrector 103 applies key correction to the video data from the contrast / brightness adjuster 102, and corrects the linearity of luminance and saturation of the video displayed on the display.
- the resolution converter 101, the contrast / brightness adjuster 102, and the ⁇ corrector 103 correct the image quality of the image displayed on the subsequent display.
- the combo video signal input via the terminal 150 is also input to the discrimination circuit 140.
- FIG. 2 shows an example in which the discrimination circuit 140 is composed of the synchronization separation circuit 142, the microcomputer 144, and the memory 144.
- the sync separation circuit 144 separates the sync signal from the composite video signal input via the terminal 150 and outputs the separated sync signal to the microcomputer 144 and the second selector 250 (hereinafter referred to as a second selector). , Selector 250).
- the microcomputer 144 is supplied with the synchronization signal separated by the synchronization separation circuit 142 and the setting information input by the user via the setting input terminal 270. Further, the memory 144 is connected to the microcomputer 144.
- the microcomputer 1443 determines the discrimination signal based on the state of the input synchronization signal, the setting information input through the setting input terminal 270, and the data stored in the memory 144. Generate. Stored in memory 1 4 4 The stored data includes various setting information of the image quality correction circuit 100, various setting values of the user already input from the setting input terminals, and information on the judgment algorithm of the microcomputer 144. ing.
- the discrimination circuit 140 controls the contrast / brightness adjuster 102, the selector 140, and the selector 250.
- the free-running synchronization signal generation circuit 240 generates a free-running synchronization signal.
- the synchronization signal generated by the free-running synchronization signal generation circuit 240 is input to one input terminal of the selector 250, and the synchronization signal separated by the synchronization separation circuit 142 is input to the other input terminal.
- the selector 250 is controlled by the microcomputer 144, and selects the synchronizing signal when the synchronizing signal is output from the synchronizing signal separating circuit.
- the selector 250 is controlled by the microcomputer 144, and selects the synchronization signal from the free-running synchronization signal generation circuit 240 when no synchronization signal is output from the synchronization signal separation circuit.
- FIG. 2 shows a liquid crystal panel module 260 as an example of the display.
- the image data from the selector 140 and the synchronization signal from the selector 250 are input to the liquid crystal panel module 260.
- the display of the liquid crystal panel module 260 is synchronized with the synchronizing signal from the selector 250, and receives the video data from the selector 140 to display the video.
- the setting conditions of the user, the setting conditions of the image quality correction circuit 100, various information stored in the memory 14, the synchronization signal separation result, and the like are used.
- the selector 140 is controlled. That is, control on a pixel basis, control based on the properties of an image, and control based on the setting status of signal processing are possible. As a result, an adaptive and high-quality bit reduction device can be realized.
- the embodiment of the present invention shown in FIG. 2 even when a video signal is not input to the terminal 150 or a video signal accompanied by a poor-quality synchronization signal is input, The synchronization signal is supplied to the liquid crystal panel module 260. Therefore, it is possible to realize a bit reduction device capable of stably performing the scanning operation of the liquid crystal panel module 260.
- FIG. 3 is a block diagram showing another configuration example of the second bit reduction unit 120 in the bit reduction device shown in FIG. 1 and FIG.
- the portions having the same numbers as those in FIG. 1 or FIG. 2 are the same as those in FIG. 1 or FIG.
- the output of the image quality correction circuit 110 is input via a terminal 330 to a noise shaving circuit 110 serving as a first bit reduction unit and a second bit reduction unit 120.
- the second bit reduction section 120 has a second noise shaving circuit 122 (hereinafter referred to as a noise shaping circuit 122) and a second upper bit selection circuit 123 (hereinafter referred to as a noise shaping circuit 122). , The upper bit selection circuit 123).
- the selector 140 receives the output of the noise shaving circuit 110 and the output of the upper bit selection circuit 123, selects one of them, and outputs it through the terminal 170.
- the video signal input to the terminal 330 is 10 bits, and is output from the terminal 170 in 6 bits. That is, assume that m is 10 and n is 6.
- the noise shaving circuit 110 performs a noise shaving process on the 10-bit signal, and supplies a signal whose number of bits has been reduced to 6 bits to the selector 140.
- the noise shaving circuit 122 performs a noise shaving process on the input 10-bit signal and supplies a signal in which the number of bits is reduced to 8 bits to the upper bit selector 123.
- the upper pit selector 1 2 3 The lower 2 bits of the output signal of the path 122 are discarded and the upper 6 bits are supplied to the selector 170.
- the noise shaving circuit 122 Since the noise shaving circuit 122 reduces the number of bits to 8 bits, PWM is generated at a value corresponding to the least significant bit, that is, at a level of 1/256 of the dynamic range. .
- the lower two bits of this signal are deleted by the upper bit selector 123.
- the output of the noise shaving circuit 122 is accompanied by PWM, but if the lower two bits of the output signal fluctuate between 1 and 0 and are accompanied by PWM, the most significant bit is output.
- the sixth bit also fluctuates to 1 and 0 from the MSB (Most Significant Bit). Therefore, in such a case, the PWM of the output of the upper bit selector 123 is generated at the value corresponding to the sixth bit, that is, at the level of 1/6 of the dynamic range.
- the sixth bit does not change. The output does not involve PWM.
- FIG. 4 is a block diagram showing still another configuration example of the second bit reduction unit 120 in the bit reduction device shown in FIGS. 1 and 2.
- the portions having the same numbers as those in FIG. 1 or 2 are the same as those in FIG.
- the output of the image quality correction circuit 110 is input to a noise shaving circuit 110 serving as a first bit reduction unit and a second bit reduction unit 120 via a terminal 330.
- the second bit reduction section 120 is provided with a third upper bit selection circuit 124 (hereinafter, upper It is composed of a cascade connection of a bit selection circuit 124 and a third noise shaving circuit 125 (hereinafter referred to as a noise shaving circuit 125).
- the selector 140 receives the output of the noise shaving circuit 110 and the output of the noise shaving circuit 125, selects one of them, and outputs it through the terminal 170.
- the video signal input to the terminal 330 is 10 bits and is output from the terminal 170 as 6 bits. That is, assume that m is 10 and n is 6.
- the noise shaving circuit 110 performs a noise shaving process on the 10-bit signal, and supplies a signal whose bit number is reduced to 6 bits to the selector 140.
- the upper bit selection circuit 124 discards the lower two bits of the 10-bit video signal input to the terminal 330 and supplies only the upper eight bits to the noise shaving circuit 125. Pay.
- the noise shaving circuit 125 performs noise shaving processing on the input 8-bit signal, reduces the number of bits to 6 bits, and supplies the signal to the selector 140.
- the noise shaving circuit 110 Since the noise shaving circuit 110 performs the noise shaping operation using the least significant bit (LSB: MostLeastBit) up to the 10th bit, it can perform fine processing. In other words, the noise shaving circuit 110 generates a PWM by a calculation including the value corresponding to the least significant bit, that is, the level of 1/24 of the dynamic range. Output.
- LLB least significant bit
- MostLeastBit the least significant bit
- the noise shaving circuit 125 reduces the number of bits of the upper 8-bit signal to 6 pits.
- the noise shaving circuit 125 cannot use the 9th bit and the 10th bit, and performs the noise shaping operation using up to the 8th bit.
- the noise shaving circuit 125 has a value corresponding to the 8th bit from the MSB, that is, the dynamic range. PWM is generated by the calculation including the level of 1 / 5.6. Therefore, the noise shaving circuit 110 can perform more detailed processing than the noise shaving circuit 125.
- fine noise shaping is performed in the first bit reduction section 110, and fine noise shaping is performed in the second bit reduction section 120 from the first bit reduction section 110. Also, coarse noise shaping is performed.
- the bit reduction device of the present invention switches the bit reduction operation based on at least one of the state of the input signal, the setting state of the user, and the setting state of the device.
- the bit reduction device of the present invention can secure the gradation and prevent the occurrence of beat noise, and can solve the problems of the conventional method.
- the bit reduction device can secure gradation and prevent the occurrence of beat noise. Further, the bit reduction device according to the present invention can prevent visual recognition as bit noise or vertical noise due to the PWM component even when the input signal has a constant luminance.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Picture Signal Circuits (AREA)
- Controls And Circuits For Display Device (AREA)
- Image Processing (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003254900A AU2003254900A1 (en) | 2002-08-20 | 2003-08-08 | Bit reduction device |
JP2004530548A JP3801189B2 (ja) | 2002-08-20 | 2003-08-08 | ビットリダクション装置 |
EP03792662A EP1460834A4 (en) | 2002-08-20 | 2003-08-08 | DEVICE FOR REDUCING BITS |
US10/503,103 US7496139B2 (en) | 2002-08-20 | 2003-08-08 | Bit reduction apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-239131 | 2002-08-20 | ||
JP2002239131 | 2002-08-20 |
Publications (1)
Publication Number | Publication Date |
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WO2004019606A1 true WO2004019606A1 (ja) | 2004-03-04 |
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ID=31943854
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Application Number | Title | Priority Date | Filing Date |
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PCT/JP2003/010155 WO2004019606A1 (ja) | 2002-08-20 | 2003-08-08 | ビットリダクション装置 |
Country Status (7)
Country | Link |
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US (1) | US7496139B2 (ja) |
EP (1) | EP1460834A4 (ja) |
JP (1) | JP3801189B2 (ja) |
KR (1) | KR100688748B1 (ja) |
CN (1) | CN1326387C (ja) |
AU (1) | AU2003254900A1 (ja) |
WO (1) | WO2004019606A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012521727A (ja) * | 2009-03-25 | 2012-09-13 | アッコ セミコンダクター インコーポレイテッド | 短縮化処理を有するシグマデルタ変調器及びその適用 |
JP2014022906A (ja) * | 2012-07-18 | 2014-02-03 | Asahi Kasei Electronics Co Ltd | デルタシグマ変調器 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008158732A (ja) * | 2006-12-22 | 2008-07-10 | Matsushita Electric Ind Co Ltd | 画像処理装置 |
JP2012044382A (ja) * | 2010-08-18 | 2012-03-01 | Sony Corp | 映像データ処理装置、コントラスト補正方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000224047A (ja) * | 1999-02-03 | 2000-08-11 | Matsushita Electric Ind Co Ltd | ディジタル信号処理回路 |
JP2003219323A (ja) * | 2002-01-28 | 2003-07-31 | Matsushita Electric Ind Co Ltd | ビットリダクション装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3338369C1 (de) * | 1983-10-21 | 1985-09-26 | Nyby Uddeholm Powder AB, Torshälla | Verfahren zur Herstellung pulvermetallurgischer Gegenstaende |
US4875095A (en) * | 1987-06-30 | 1989-10-17 | Kokusai Denshin Denwa Kabushiki Kaisha | Noise-shaping predictive coding system |
US5347621A (en) * | 1990-09-19 | 1994-09-13 | Sony Corporation | Method and apparatus for processing image data |
JPH08237669A (ja) * | 1995-02-28 | 1996-09-13 | Sony Corp | 画像信号処理装置、画像信号処理方法および画像信号復号化装置 |
US6195393B1 (en) * | 1998-07-06 | 2001-02-27 | General Instrument Corporation | HDTV video frame synchronizer that provides clean digital video without variable delay |
JP2000209553A (ja) * | 1998-11-13 | 2000-07-28 | Victor Co Of Japan Ltd | 情報信号記録装置及び再生装置 |
JP2000224407A (ja) * | 1999-01-29 | 2000-08-11 | Canon Inc | 画像形成装置、画像形成方法及び記憶媒体 |
GB9919805D0 (en) * | 1999-08-21 | 1999-10-27 | Univ Manchester | Video cording |
JP3657191B2 (ja) * | 2000-12-07 | 2005-06-08 | シャープ株式会社 | アップ/ダウングレーコードカウンタおよびこれを備えた固体撮像装置 |
-
2003
- 2003-08-08 EP EP03792662A patent/EP1460834A4/en not_active Withdrawn
- 2003-08-08 US US10/503,103 patent/US7496139B2/en not_active Expired - Fee Related
- 2003-08-08 AU AU2003254900A patent/AU2003254900A1/en not_active Abandoned
- 2003-08-08 WO PCT/JP2003/010155 patent/WO2004019606A1/ja active Application Filing
- 2003-08-08 CN CNB038179601A patent/CN1326387C/zh not_active Expired - Fee Related
- 2003-08-08 JP JP2004530548A patent/JP3801189B2/ja not_active Expired - Fee Related
- 2003-08-08 KR KR1020057002758A patent/KR100688748B1/ko not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000224047A (ja) * | 1999-02-03 | 2000-08-11 | Matsushita Electric Ind Co Ltd | ディジタル信号処理回路 |
JP2003219323A (ja) * | 2002-01-28 | 2003-07-31 | Matsushita Electric Ind Co Ltd | ビットリダクション装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1460834A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012521727A (ja) * | 2009-03-25 | 2012-09-13 | アッコ セミコンダクター インコーポレイテッド | 短縮化処理を有するシグマデルタ変調器及びその適用 |
JP2014022906A (ja) * | 2012-07-18 | 2014-02-03 | Asahi Kasei Electronics Co Ltd | デルタシグマ変調器 |
Also Published As
Publication number | Publication date |
---|---|
JP3801189B2 (ja) | 2006-07-26 |
JPWO2004019606A1 (ja) | 2005-12-15 |
CN1326387C (zh) | 2007-07-11 |
AU2003254900A1 (en) | 2004-03-11 |
KR100688748B1 (ko) | 2007-03-02 |
CN1672400A (zh) | 2005-09-21 |
EP1460834A1 (en) | 2004-09-22 |
US20050083434A1 (en) | 2005-04-21 |
EP1460834A4 (en) | 2009-09-16 |
US7496139B2 (en) | 2009-02-24 |
KR20050050087A (ko) | 2005-05-27 |
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