WO2004017437A1 - Contact modifie pour dispositifs programmables - Google Patents

Contact modifie pour dispositifs programmables Download PDF

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Publication number
WO2004017437A1
WO2004017437A1 PCT/US2002/025895 US0225895W WO2004017437A1 WO 2004017437 A1 WO2004017437 A1 WO 2004017437A1 US 0225895 W US0225895 W US 0225895W WO 2004017437 A1 WO2004017437 A1 WO 2004017437A1
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WO
WIPO (PCT)
Prior art keywords
contact
ions
opening
memory
programmable
Prior art date
Application number
PCT/US2002/025895
Other languages
English (en)
Inventor
Stephen J. Hudgens
Tyler A. Lowrey
Original Assignee
Ovonyx, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ovonyx, Inc. filed Critical Ovonyx, Inc.
Priority to CN02829457.2A priority Critical patent/CN1650442A/zh
Priority to GB0501969A priority patent/GB2407706A/en
Priority to DE10297772T priority patent/DE10297772T5/de
Priority to JP2004529027A priority patent/JP2005536052A/ja
Priority to AU2002368177A priority patent/AU2002368177A1/en
Priority to PCT/US2002/025895 priority patent/WO2004017437A1/fr
Publication of WO2004017437A1 publication Critical patent/WO2004017437A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/52—Structure characterized by the electrode material, shape, etc.

Definitions

  • FIELD Programmable devices including phase change memory devices, having a compositionally modified contact, that can be programmed by changing the state of a phase change material.
  • RAM random access memory
  • ROM read-only memory
  • Typical memory technologies include dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM).
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • Solid state memory devices typically employ micro-electronic circuit elements for each memory bit (e.g., one to four transistors per bit) in memory applications. Since one or more electronic circuit elements are required for each memory bit, these devices may consume considerable chip "real estate" to store a bit of information, which limits the density of a memory chip.
  • the primary "non- volatile" memory element of these devices such as an EEPROM, typically employ a floating gate field effect transistor device that has limited re-programmability and which holds a charge on the gate of field effect transistor to store each memory bit. These classes of memory devices are also relatively slow to program.
  • Phase change memory devices use phase change materials, i.e., materials that can be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application.
  • phase change materials i.e., materials that can be electrically switched between a generally amorphous and a generally crystalline state
  • One type of memory element originally developed by Energy Conversion Devices, Inc. of Troy, Michigan utilizes a phase change material that can be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states.
  • These different structured states have different values of resistivity, and therefore different electrical read-out.
  • Typical materials suitable for such application include those utilizing various chalcogenide elements.
  • phase change memory materials represent a significant improvement in non-volatile memory.
  • phase change memory devices One characteristic common to solid state and phase change memory devices is significant power consumption particularly in setting or reprogramming memory elements. Power consumption is important, particularly in portable devices that rely on power cells (e.g., batteries). It would be desirable to decrease the power consumption of a memory device.
  • Another characteristic common to solid state and phase change memory devices is limited reprogrammable cycle life from/to an amorphous and crystalline state. Further, over time the phase change material can fail to reliably reprogram from/to an amorphous and a crystalline state. It would be desirable to increase the programmable cycle life of the phase change memory material.
  • Fig. 1 is a schematic diagram of an embodiment of an array of memory elements
  • Fig. 2 schematically illustrates a cross-sectional planar side view of a portion of a semiconductor substrate having dielectric trenches formed therein defining a z-direction thickness of a memory cell in accordance with one embodiment of forming a memory element on a substrate;
  • Fig. 3 depicts the structure of Fig. 2, through the same cross-sectional view, after the introduction of dopants to form an isolation device for a memory element;
  • Fig. 4 depicts the structure of Fig. 3 after forming trenches;
  • Fig. 5 depicts a schematic top view of the structure of Fig. 4;
  • Fig. 6 depicts the structure of Fig.4 after forming contacts;
  • Fig. 7 depicts the structure of Fig. 6, through the same cross-sectional view, after forming a masking material and a dielectric material;
  • Fig. 8 depicts another cross-section view of the structure of Fig. 7, after forming an opening through the dielectric exposing the contact;
  • Fig. 9 depicts the structure of Fig. 8, through the same cross-sectional view, illustrating an angled modification of the contact;
  • Fig. 10 depicts another cross-sectional view of the structure of Fig. 9 illustrating an area of modification to the contact;
  • Fig. 11 depicts the structure of Fig. 8, through the same cross-sectional view, after conformally forming a spacer within the opening;
  • Fig. 12 depicts the structure of Fig. 9, through the same cross-sectional view, after etching the spacer;
  • Fig. 13 depicts the structure of Fig. 12, through the same cross-sectional view, illustrating a self-aligned modification of the contact;
  • Fig. 14 depicts the structure of Fig. 12, through the same cross-sectional view, illustrating an angled modification of the contact;
  • Fig. 15 depicts another cross-sectional view of the structure of Fig. 14 illustrating an area of modification to the contact
  • Fig. 16 depicts the same cross-sectional view of the structure of Fig. 12, after forming programmable material, a barrier and a conductor;
  • Fig. 17 depicts the same cross-sectional view of the structure of Fig. 16, after patterning the programmable material, barrier and conductor;
  • Fig. 18 depicts another cross-sectional view of the structure of Fig. 17;
  • Fig. 19 depicts the same cross-sectional view of the structure of Fig. 18, after forming a dielectric material and a signal line;
  • Fig. 20 depicts one method of forming a memory device.
  • Fig. 21 depicts one system embodiment including a memory having a structure similar to that described by Fig. 19.
  • a memory device utilizing programmable material (e.g. phase change) to determine the state of memory elements of the device is described.
  • the programmable material reprograms to an amorphous and crystalline state with improved (generally lower) power consumption relative to previous devices, achieved in part by modifying the resistivity of a contact, hi an embodiment, the resistivity of the contact is increased, increasing power dissipation in the contact and increasing heat transferred from the contact to the programmable material, thereby reducing the required programming current and improving reprogramming reliability.
  • an improved (generally less) chemically reactive contact is described.
  • a programmable material having improved adherence (e.g. less delamination) to a contact is described.
  • a method of modifying the resistivity of a contact is described.
  • the contact can be modified by at least one of implanting ions into the contact, depositing material on the contact, and treating the contact with plasma.
  • Implanting of ions can be performed at normal incidence to a surface of the contact exposed to the opening, and also at an angle to the surface of the contact exposed to the opening.
  • the described memory device and method provides lower programming current requirements, improved device reliability, improved programmable cycle life, and lower cost and scalability relative to previous devices. Further, in an embodiment, the apparatus is manufacturable with conventional process toolsets and facilities.
  • Fig. 1 shows a schematic diagram of an embodiment of a memory array comprised of a plurality of memory elements presented and formed in the context of the description provided herein.
  • the circuit of memory array 5 includes an xy grid with memory elements 30 electrically interconnected in series with isolation devices 25 on a portion of a chip.
  • Address lines 10 e.g., columns
  • 20 e.g., rows
  • One purpose of the xy grid array of memory elements in combination with isolation devices is to enable each discrete memory element to be read and written without interfering with the information stored in adjacent or remote memory elements of the array.
  • a memory array such as memory device 5 of Fig. 1 can be formed in a portion, including the entire portion, of a substrate.
  • a typical substrate includes a semiconductor substrate such as a silicon substrate.
  • Other substrates including, but not limited to, substrates that contain ceramic material, organic material, or glass material as part of the infrastructure are also suitable.
  • memory array 5 can be fabricated over an area of the substrate at the wafer level and then the wafer reduced through singulation into discrete die or chips, some or all of the die or chips having a memory array formed thereon. Additional addressing circuitry (e.g., decoders, etc.) can be formed as known to those of skill in the art.
  • Figs. 2-14 illustrate an embodiment of the fabrication of representative memory element 15 of Fig. 1.
  • Fig. 2 depicts a portion of substrate 100 that is, for example, a semiconductor (e.g., silicon) substrate.
  • a P-type dopant such as boron is introduced in portion 110.
  • a suitable concentration of P-type dopant is on the order of about 5x10 to 1x10 atoms per cubic centimeters (atoms/cm ) rendering portion 110 of substrate 100 representatively P "1-1" .
  • the dopant concentration is on the order of about 10 16 to 10 17 atoms/cm 3 .
  • Fig. 2 also depicts shallow trench isolation (STI) structures 130 formed in epitaxial portion 120 of substrate 100.
  • STI structures 130 serve, in one aspect, to define the z-direction thickness of a memory cell, with at this point only the z-direction thickness of a memory cell defined.
  • memory cell z-direction regions 135A and 135B are patterned as strips with the x-direction dimension greater than the z-direction dimension.
  • STI structures 130 serve to isolate individual memory elements from one another as well as associated circuit elements (e.g., transistor devices) formed in and on the substrate.
  • Current state of the art photolithography techniques utilized to pattern STI structures define the z-direction thickness of memory cell regions 135 A and 135B can produce feature sizes (z-direction thickness) as small as 0.25 microns ( ⁇ m).
  • Fig. 3 depicts the structure of Fig. 2 after further fabrication operations in memory cell regions 135 A and 135B.
  • first conductor or signal line material 140 is N-type doped silicon formed by the introduction of, for example, phosphorous or arsenic to a concentration on the order of about 10 18 to 10 19 atoms/cm 3 (e.g., N 1" silicon).
  • first conductor or signal line material 140 serves as an address line, a row line (e.g., row line 20 of Fig. 1).
  • first conductor or signal line material 140 Overlying first conductor or signal line material 140 is an isolation device (e.g., isolation device 25 of Fig. 1).
  • the isolation device is a PN diode formed of N-type silicon portion 150 (e.g., dopant concentration on the order of about 10 14 to 10 18 atoms/cm 3 ) and P-type silicon portion 160 (e.g., dopant concentration on the order of about 10 19 to 10 20 atoms/cm 3 ).
  • PN diode is shown, it is to be appreciated that other isolation structures are similarly suitable.
  • Such devices include, but are not limited to, metal oxide semiconductor (MOS) devices.
  • Fig. 4 depicts the structure of Fig. 3 from an xy perspective after forming trenches 190 in epitaxial portion 120 of substrate 100.
  • Trenches 190 are formed, in this example, orthogonal to STI structures 130.
  • Trenches 190 define the x-direction thickness of a memory cell. According to current photolithographic techniques, a suitable feature size for the x-direction thickness is as small as 0.25 ⁇ m.
  • Fig. 4 also depicts memory cells 145A and 145B separated by trenches 190, having a z-direction thickness defined by STI structures 130 and an x-direction thickness defined by trenches 190.
  • the definition of the x-direction thickness involves, in one embodiment, an etch to the conductor or signal line 140 of the memory line stack to define memory cells 145 A and 145B of memory cell region 135A.
  • the etch proceeds through the memory line stack to, in this example, a portion of conductor or signal line 140.
  • a timed etch can be utilized to stop an etch at this point.
  • N-type dopant is introduced at the base of each trench 190 to form pockets 200 having a dopant concentration on the order of about 10 to 10 atoms/cm (e.g., 1ST region) between memory cells 145 A and 145B.
  • a dielectric material such as silicon dioxide is introduced in trenches 190 to form STI structures 132.
  • the superior surface (as viewed) may then be planarized with, for example, a chemical-mechanical polish.
  • Fig. 5 depicts an xz perspective of the structure of Fig. 4 with memory cells (e.g., memory cells 145A and 145B) separated by STI structures 130 and 132.
  • Fig. 6 depicts the structure of Fig.
  • Contact 170 serves as a low resistance material in the fabrication of peripheral circuitry (e.g., addressing circuitry) of the circuit structure on the chip.
  • peripheral circuitry e.g., addressing circuitry
  • Fig. 7 depicts the structure of Fig. 6 after the introduction of masking material 180.
  • masking material 180 serves, in one sense, as an etch stop for a subsequent etch operation.
  • a suitable material for masking material 180 is a dielectric material such as silicon nitride (Si 3 N 4 ).
  • Fig. 7 also depicts dielectric material 210 introduced over the structure to a thickness on the order of lOOA to 50,000A sufficient to blanket memory cells 145 A and 145B.
  • dielectric material 210 is SiO 2 .
  • dielectric material 210 is a material selected for its reduced thermal conductivity, K, preferably a thermal conductivity less than K S J O2 , more preferably three to 10 times less ⁇ sio 2 -
  • K reduced thermal conductivity
  • K preferably a thermal conductivity less than K S J O2 , more preferably three to 10 times less ⁇ sio 2 -
  • K reduced thermal conductivity
  • K preferably a thermal conductivity less than K S J O2
  • SiO 2 and Si 3 N 4 have K values on the order of 1.0.
  • suitable materials for dielectric material 210 include those materials that have K values less than 1.0.
  • Certain high temperature polymers having K values less than 1.0 include carbide materials, Aerogel, Xerogel (K on the order of 0.1
  • Fig. 8 depicts the structure of Fig. 7, through the same cross-sectional view, after forming openings 220 through dielectric 210 and masking material 180, exposing contact 170.
  • openings 220 are formed by patterning of circular holes etched through dielectric 210 and masking material 180, using conventional photolithography and dry etching techniques. In terms of state of the art photolithography techniques, circular openings as small as 0.25 ⁇ m in diameter can be patterned. It is to be appreciated that, in addition to circular openings, other openings such as rectangular openings could alternatively be employed.
  • Fig. 9 depicts the structure of Fig. 8, through the same cross-sectional view, illustrating an angled modification of contact 170.
  • the modification of contact 170 can also be accomplished in a non-angled manner.
  • angled it is meant that, for example, the direction of ion implantation is not parallel to the illustrated y-axis depicted in Fig. 9.
  • Fig. 9 illustrates ion implantation
  • other methods of modification can be employed including, but not limited to, depositing material onto contact 170 and treating contact 170 with plasma, thereby increasing the resistivity of contact 170.
  • contact 170 is modified by implanting ions 175 into contact 170.
  • Ion implantation provides positional control precision and avoids side diffusion issues. Impact damage to contact 170 from ion implantation results in partial or complete amo hization, increasing the resistivity of contact 170 and increasing the ability of contact 170 to form chemical compounds with atoms introduced by ion implantation or other methods. Ions that are capable of forming compounds with CoSi 2 and thereby increase the resistivity of contact 170 can be utilized, including oxygen ions, nitrogen ions and carbon ions.
  • contact 170 is composed of CoSi 2
  • implanting oxygen ions within the CoSi causes the formation of insulator regions of SiO 2 within contact 170, thereby increasing the resistivity of contact 170.
  • nitrogen ions are implanted into contact 170 (composed of CoSi 2 )
  • insulator regions of Si 3 N 4 are formed within contact 170.
  • Ion implantation provides precision in that the number of ions specified can be correspondingly implanted. Further, the depth of ion implantation can be selected using conventionally known published tables and considering factors including ion mass, ion energy, and composition and thickness of contact 170.
  • dielectric 210 serves as an ion implantation mask allowing ions to be implanted in contact 170 or in a portion of contact 170.
  • Most films employed in the semiconductor process can be used to block an ion beam, including SiO 2 , silicon nitride, aluminum, and other thin metal films.
  • contact 170 is modified by depositing a resistive material on contact 170.
  • the resistive material has a resistivity of one of 0.001 ohm-cm to 0.5 ohm-cm.
  • the resistivity is selected by specifying a resistive material film thickness, specifying a target programming current, specifying a voltage budget for the memory device and utilizing conventional calculations.
  • contact 170 has a series resistance of one of 200 ohms to 2000 ohms.
  • the resistive material is formed on contact 170 or on a portion of contact 170. Although resistive material is also formed on the walls of openings 220, significant current is not shunted away from programmable material 404, given a sufficiently high resistivity of the resistive material.
  • contact 170 is modified by plasma treatment by exposing contact 170 within openings 220 to at least one of activated nitrogen, activated oxygen and ammonia.
  • the plasma chemically reacts with, and increases the resistivity of, contact 170.
  • the resistivity of contact 170 can be modified using one of any, a combination of any, and all of the above referenced methods.
  • Fig. 10 depicts another cross-sectional view of the structure of Fig. 9 illustrating an area of modification to contact 170 by implanting ions 175 at an angle to the y-axis.
  • the area of contact 170 that is modified is depicted as modified area 172 shown on the perimeter of contact 170, within opening 220.
  • modified area 172 is higher in resistivity than the remainder of contact 170.
  • programmable material 404 that undergoes a phase change is positioned on contact 170, but not on modified area 172. Less programmable material that undergoes a phase change is therefore utilized, resulting in less power consumption and improved programming reliability.
  • modified area 172 includes the entire exposed surface area of contact 170 within openings 220, and programmable material 404 that undergoes a phase change is formed on all of modified area 172.
  • Fig. 11 depicts the structure of Fig. 8, through the same cross-sectional view, after forming spacer material 402 within openings 220 and on dielectric 210.
  • spacer material 402 is conformally formed, for example by chemical vapor deposition of tetra-ethyl-ortho-silicate (TEOS) on the substrate. At this point of fabrication, spacer material covers contact 170 within openings 220.
  • TEOS tetra-ethyl-ortho-silicate
  • Fig. 12 depicts the structure of Fig. 11 after spacer material 402 is etched to form dielectric spacers (spacer material portions 402A) inside openings 220.
  • spacer material 402 is anisotropically etched using a timed etch. In one aspect, that will become more clear later, spacer material 402 serves to reduce the quantity of programmable material 404 (Fig. 16) on contact 170.
  • Fig. 13 depicts the structure of Fig. 12, through the same cross-sectional view, illustrating a self-aligned modification of contact 170.
  • the modification is self- aligned by spacers 402A that act as an ion implantation mask. It is to be appreciated that modification of contact 170 can be performed either before or after (or both before and after) spacers 402A are formed. Further, while Fig.13 shows modification of contact 170 by implanting ions 175, additional methods of modification are available including depositing a material on contact 170 and exposing contact 170 to plasma.
  • ions are implanted at an angle to the walls of openings 220.
  • Fig. 14 depicts the structure of Fig. 12, through the same cross- sectional view, illustrating an angled modification of contact 170 by implanting ions 175. Again, it is to be appreciated that additional methods of modification are available including depositing a material on contact 170 and exposing contact 170 to plasma.
  • Fig. 15 depicts another cross-sectional view of the structure of Fig. 14 illustrating an area of modification to contact 170, namely modified area 173.
  • programmable material 404 that undergoes a phase change is positioned on contact 170, but riot on modified area 172. Less programmable material that undergoes a phase change is therefore utilized, resulting in less power consumption and improved programming reliability.
  • Fig. 16 depicts the structure of Fig. 13 after introducing programmable material 404 within openings 220, on contact 170 and on dielectric 210.
  • programmable material 404 a phase change material that has a property such that a physical state (e.g., crystalline, amorphous) can be modified with the application of an amount of energy (e.g., electrical energy, thermal energy).
  • Chalcogenide materials having the general formula are known to be suitable for this purpose such that chalcogenide materials can be introduced on the substrate and on contact 170 by conventional deposition techniques.
  • barrier material 408 is formed on programmable material 404 and conductor 410 is formed on barrier material 408, in accordance with an embodiment.
  • Barrier material 408 serves, in an aspect, to prevent any chemical reaction between programmable material 404 and conductor 410.
  • programmable material 404, spacer 402, barrier material 408 and conductor 410 are formed using conventional patterning techniques.
  • barrier material 408 includes at least one of titanium and titanium nitride. Titanium and/or Titanium nitride coatings can be deposited uniformity on a substrate, showing good adhesion in that they resist flaking, blistering, chipping and peeling.
  • programmable material 404 includes a phase change material of a chalcogenide alloy and contact 170 includes CoSi 2 .
  • chalcogenide alloys suitable as programmable material 404 include at least one element from column VI of the Periodic Table Of The Elements.
  • Ge 2 Sb 2 Te 5 is utilized as programmable material 404.
  • chalcogenide alloys utilized as programmable material 404 include GaSb, InSb, InSe, Sb 2 Te 3 , GeTe, Ge 2 Sb 2 Te 5 , 1-nSbTe, GaSeTe, SnSb 2 Te 4 , InSbGe, AghiSbTe, (GeSn)SbTe, GeSb(SeTe), and Te 81 Ge 15 Sb 2 S 2 .
  • the contact area of programmable material 404 and contact 170 is minimized by the presence of spacer material portions 402A.
  • the dimensions of openings 220 expose a first contact area of contact 170.
  • a second contact area, less than the first contact area, is exposed by spacer material 402 and/or spacer material portions 402A.
  • Region 406 shown between spacer material portions 402 A, defines a limited and localized programming region of programmable material 404, adding to the programmable reliability from and to an amorphous and crystalline state of programmable material 404. In general, by localizing the phase change area, less current is required through programmable material 404 during programming and reading, and less power consumption results.
  • Fig. 17 depicts the structure of Fig. 16, from an xy perspective, after forming openings 412. Openings 412 serve, in one aspect, to define the x-direction thickness of programmable material 404, barrier material 408 and conductor 410. Openings 412 serve, in another aspect, to isolate individual memory elements from one another as well as associated circuit elements (e.g., transistor devices) formed on the substrate. In one embodiment, openings 412 are formed by patterning of openings through conductor 410, barrier material 408 and programmable material 404. The patterning can be accomplished using conventional photolithographic and etch techniques.
  • etching proceeds through conductor 410, barrier material 408 and programmable material 404, to the exclusion of dielectric 210.
  • a suitable feature size for the x- direction thickness of openings 412 include as small as 0.25 ⁇ m.
  • Fig. 18 depicts another cross-sectional view, from the yz perspective, of the structure of Fig. 17. [0038]
  • Fig. 19 shows the structure of Fig. 18 after forming dielectric material
  • Dielectric material 412 is, for example, SiO 2 or other suitable material that is formed on conductor 410 to electronically isolate conductor 410.
  • dielectric material 412 is planarized and a via is formed in a portion of the structure through dielectric material 412, dielectric material 210, and dielectric material 180 to contact 170.
  • the via is filled with conductive material such as tungsten (W) and a barrier material such as a combination of titanium (Ti) and titanium nitride (TiN).
  • mirror conductor line material 414 is formed and patterned to mirror that of conductor or signal line material 140 (e.g., row line) formed on substrate 100.
  • Mirror conductor line material 414 mirrors conductor or signal line material 140 and is coupled to conductor or signal line material 140 through the conductive via.
  • mirror conductor line material 414 serves, in one aspect, to reduce the resistance of conductor or signal line material 140 in a memory array, such as memory array 5 illustrated in Fig. 1.
  • a suitable material for mirror conductor line material 414 includes an aluminum material, such as an aluminum alloy.
  • Fig. 20 describes a method in forming a programmable memory device in accordance with an embodiment.
  • a memory array such as memory device 5
  • system 700 includes microprocessor 704, input/output (I O) port 706, and memory 702.
  • Microprocessor 704, I/O port 706, and memory 702 are connected by data bus 712, address bus 716 and control bus 714.
  • Microprocessor 704 fetches instructions or reads data from memory 702 by sending out an address on address bus 716 and a memory read signal on control bus 714.
  • Memory 702 outputs the addressed instruction or data word to microprocessor 704 on data bus 712.
  • Microprocessor 704 writes a data word to memory 702 by sending out an address on address bus 716, sending out the data word on data bus 712, and sending a memory write signal to memory 702 on control bus 714.
  • I O port 706 is utilized to couple to at least one of input device 708 and output device 710.

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Abstract

Cette invention concerne, dans une variante, un appareil qui sert à régler et à reprogrammer l'état de dispositifs programmables. Cette invention concerne, dans une variante, un procédé consistant à former une ouverture dans un diélectrique (210) exposant un contact (170) formé sur un substrat (110). La résistivité du contact est modifiée au moyen d'au moins un des procédés suivants, qui consistent : à implanter des ions (175) dans le contact ; à déposer un matériau sur le contact ; et à traiter le contact avec du plasma. Dans une variante, un élément de séparation (102) est formé dans l'ouverture et un matériau programmable (404), de préférence un chalcogénure, est formé dans l'ouverture et sur le contact modifié. Un conducteur (410) est formé sur le matériau programmable et le contact transmet à une ligne de signal.
PCT/US2002/025895 2002-08-14 2002-08-14 Contact modifie pour dispositifs programmables WO2004017437A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN02829457.2A CN1650442A (zh) 2002-08-14 2002-08-14 用于可编程器件的修改的触点
GB0501969A GB2407706A (en) 2002-08-14 2002-08-14 Modified contact for programmable devices
DE10297772T DE10297772T5 (de) 2002-08-14 2002-08-14 Modifzierter Kontakt für Programmierbare Bauelemente
JP2004529027A JP2005536052A (ja) 2002-08-14 2002-08-14 プログラム可能デバイスのためのコンタクト改善方法及び装置
AU2002368177A AU2002368177A1 (en) 2002-08-14 2002-08-14 Modified contact for programmable devices
PCT/US2002/025895 WO2004017437A1 (fr) 2002-08-14 2002-08-14 Contact modifie pour dispositifs programmables

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/025895 WO2004017437A1 (fr) 2002-08-14 2002-08-14 Contact modifie pour dispositifs programmables

Publications (1)

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WO2004017437A1 true WO2004017437A1 (fr) 2004-02-26

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PCT/US2002/025895 WO2004017437A1 (fr) 2002-08-14 2002-08-14 Contact modifie pour dispositifs programmables

Country Status (6)

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JP (1) JP2005536052A (fr)
CN (1) CN1650442A (fr)
AU (1) AU2002368177A1 (fr)
DE (1) DE10297772T5 (fr)
GB (1) GB2407706A (fr)
WO (1) WO2004017437A1 (fr)

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JP2006140464A (ja) * 2004-11-10 2006-06-01 Samsung Electronics Co Ltd ２成分系金属酸化膜をデータ保存物質膜として採用する交差点不揮発性記憶素子及びその製造方法
KR100694188B1 (ko) 2005-03-22 2007-03-14 한국표준과학연구원 메모리 및 그 제조 방법
KR100782496B1 (ko) 2006-11-09 2007-12-05 삼성전자주식회사 자기 정렬된 셀 다이오드를 갖는 반도체 소자의 제조방법및 이를 이용하는 상변화 기억소자의 제조방법
CN100389507C (zh) * 2004-12-07 2008-05-21 旺宏电子股份有限公司 硫属化合物随机存取内存及其制造方法
US8409961B2 (en) 2008-07-22 2013-04-02 Tokyo Electron Limited Alteration method and alteration apparatus for titanium nitride
US8604456B2 (en) 2008-08-06 2013-12-10 Hitachi, Ltd. Nonvolatile memory device and method of manufacturing the same

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US6849564B2 (en) * 2003-02-27 2005-02-01 Sharp Laboratories Of America, Inc. 1R1D R-RAM array with floating p-well
US7601995B2 (en) * 2005-10-27 2009-10-13 Infineon Technologies Ag Integrated circuit having resistive memory cells
US7479671B2 (en) * 2006-08-29 2009-01-20 International Business Machines Corporation Thin film phase change memory cell formed on silicon-on-insulator substrate
KR100764056B1 (ko) 2006-09-14 2007-10-08 삼성전자주식회사 상변화 기억 장치 및 그 제조 방법
DE102007021761B4 (de) * 2007-05-09 2015-07-16 Adesto Technology Corp., Inc. Widerstandsschaltelement, Speicherbauelemente, Speichermodul, Verfahren zur Herstellung eines resistiven Schaltelements und Verfahren zur Herstellung eines resistiven Speicherbauelements
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US20030001211A1 (en) * 2001-06-30 2003-01-02 Hudgens Stephen J. Modified contact for programmable devices

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140464A (ja) * 2004-11-10 2006-06-01 Samsung Electronics Co Ltd ２成分系金属酸化膜をデータ保存物質膜として採用する交差点不揮発性記憶素子及びその製造方法
CN100389507C (zh) * 2004-12-07 2008-05-21 旺宏电子股份有限公司 硫属化合物随机存取内存及其制造方法
KR100694188B1 (ko) 2005-03-22 2007-03-14 한국표준과학연구원 메모리 및 그 제조 방법
KR100782496B1 (ko) 2006-11-09 2007-12-05 삼성전자주식회사 자기 정렬된 셀 다이오드를 갖는 반도체 소자의 제조방법및 이를 이용하는 상변화 기억소자의 제조방법
US7541252B2 (en) 2006-11-09 2009-06-02 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device including a self-aligned cell diode
US8409961B2 (en) 2008-07-22 2013-04-02 Tokyo Electron Limited Alteration method and alteration apparatus for titanium nitride
US8604456B2 (en) 2008-08-06 2013-12-10 Hitachi, Ltd. Nonvolatile memory device and method of manufacturing the same

Also Published As

Publication number Publication date
AU2002368177A1 (en) 2004-03-03
DE10297772T5 (de) 2005-11-03
GB2407706A (en) 2005-05-04
CN1650442A (zh) 2005-08-03
JP2005536052A (ja) 2005-11-24
GB0501969D0 (en) 2005-03-09

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