WO2003094236A1 - Semiconductor device and radio communication apparatus - Google Patents

Semiconductor device and radio communication apparatus Download PDF

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Publication number
WO2003094236A1
WO2003094236A1 PCT/JP2002/004339 JP0204339W WO03094236A1 WO 2003094236 A1 WO2003094236 A1 WO 2003094236A1 JP 0204339 W JP0204339 W JP 0204339W WO 03094236 A1 WO03094236 A1 WO 03094236A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
semiconductor device
tab
circuit
sealing body
Prior art date
Application number
PCT/JP2002/004339
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
Tadatoshi Danno
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2002/004339 priority Critical patent/WO2003094236A1/ja
Priority to AU2003235967A priority patent/AU2003235967A1/en
Priority to KR1020087009547A priority patent/KR100993277B1/ko
Priority to KR1020087009552A priority patent/KR100993579B1/ko
Priority to CNB038096366A priority patent/CN100380651C/zh
Priority to CNA2009101340438A priority patent/CN101515579A/zh
Priority to CNA2009101340423A priority patent/CN101515578A/zh
Priority to JP2004502352A priority patent/JP4351150B2/ja
Priority to US10/512,459 priority patent/US7425756B2/en
Priority to CNB2007101273468A priority patent/CN100536123C/zh
Priority to PCT/JP2003/005475 priority patent/WO2003094232A1/ja
Priority to KR1020047017429A priority patent/KR100993276B1/ko
Publication of WO2003094236A1 publication Critical patent/WO2003094236A1/ja
Priority to US11/455,171 priority patent/US20060237831A1/en
Priority to US11/455,157 priority patent/US7312511B2/en
Priority to US12/032,690 priority patent/US7937105B2/en
Priority to US12/033,061 priority patent/US7777309B2/en
Priority to JP2009142145A priority patent/JP5080532B2/ja
Priority to US13/094,383 priority patent/US8126501B2/en
Priority to JP2012128107A priority patent/JP5473026B2/ja

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Definitions

  • the present invention relates to a semiconductor device and an electronic device.
  • the present invention relates to a high-frequency power module (semiconductor device) incorporating a high-frequency unit analog signal processing IC including a low noise amplifier (LNA) for amplifying a weak signal.
  • LNA low noise amplifier
  • wireless communication devices electronic devices
  • Mobile communication devices such as mobile phones are configured to be compatible with multiple communication systems. That is, a plurality of circuit systems are incorporated in a transceiver (front end) of a mobile phone so as to transmit and receive a plurality of communication systems.
  • a dual-band communication method is known as a method that enables communication between mobile phones (for example, cellular telephones) using different communication methods (systems).
  • GSM Global System for Mobile Communications
  • DCS with a carrier frequency band of 170 to 1785 MHz
  • the dual-band system using the 1800 (Digital Cellular System 1800) and the high-frequency power amplifier for the dual band.
  • RF Radio Frequency
  • MOS FET Metal Oxide Semiconductor Field-Effect-Transistor
  • the dual-band system processes signals of two communication systems, such as GSM and DCS 180, and the triple-band system uses GSM and DCS (Digital Cellular System) 180, and PCS 190. It processes signals of three communication systems such as the 00 system.
  • GSM Global System for Mobile Communications
  • GSM900 or GSM850 is incorporated.
  • the high-frequency power module includes an LNA, mixer, PLL (Phase-Locked Loop) synthesizer, PGA (Programmable Gain Amplifier) with auto-calibration, IQ modulator / demodulator, offset PLL, It incorporates a one-chip semiconductor device that monolithically integrates VC0 (Voltage-Controlled Oscillator) and the like.
  • S 0 N Small Outline Non-Leaded Package
  • QFN Quad Flat Non-Leaded Package
  • the resin-encapsulated semiconductor device described in this document has an island having a die pad for fixing a semiconductor chip and a wire bonding portion for connecting wires, and the semiconductor chip is fixed on the die pad.
  • Each of the electrode terminals of the semiconductor chip is connected to a wire bonding part of a lead or an island.
  • An air gap is provided between the die pad and the wire bonding part to prevent the bonded wire from coming off or cutting due to heat stress.
  • the island can be connected to a printed board or the like as a ground lead.
  • Japanese Patent Application Laid-Open No. H11-251514 describes a high-frequency device in which a lead structure used in a mobile phone or the like having a semiconductor element mounting portion as a ground is a gull-wing type. .
  • the electrode of the semiconductor element and the semiconductor element mounting portion are connected with a wire in order to use the die pad as a ground electrode ( Down bonding). Due to down bonding, the semiconductor element mounting part is larger than the semiconductor element, and in the mounted state, the periphery of the semiconductor element mounting part protrudes outside the semiconductor element, and a wire is connected to this part. Has become.
  • a high-frequency power module is incorporated in a non-lead type semiconductor device, and a ground terminal of each circuit part constituting a high-frequency power module is connected to a wire in order to stabilize a ground potential.
  • a method of electrical connection to the evening via the Internet By using down bonding, the number of external electrode terminals can be reduced and the package The size of the semiconductor device can be reduced eventually.
  • the signal captured by the antenna is amplified by a low noise amplifier (LNA), but the input signal is extremely weak.
  • LNA low noise amplifier
  • the potential of the common terminal that is, the ground potential fluctuates in accordance with the operation of each circuit section, especially the oscillator that operates periodically, and as a result, there is a possibility that the circuit section and the circuit section may be partially connected.
  • Crosstalk occurs and the output fluctuates, preventing good calls.
  • signal waveform distortion due to induced current due to inter-lead crosstalk or fluctuation in ground potential is output from the communication system, and this output signal enters the communication system in use and becomes noise.
  • Circuits that are susceptible to such fluctuations in ground potential and crosstalk include RF VCOs (high-frequency voltage controlled oscillators) that handle high frequencies in addition to low noise amplifiers (LNA).
  • RF VCOs high-frequency voltage controlled oscillators
  • LNA low noise amplifier
  • the present inventor has proposed that in a low-noise amplifier or RFVC0, among the electrode terminals of a semiconductor element, the ground terminal is not connected to a tab serving as a common terminal via a wire, but is connected to an independent lead terminal (external electrode).
  • the present invention has been made with the idea that the influence of the fluctuation of the ground potential at the time of turning on and off other circuit parts is reduced by connecting the terminal to the terminal via a wire.
  • An object of the present invention is to provide a down-bonded semiconductor device in which a ground potential in a specific circuit portion of a circuit formed in a semiconductor element is hardly affected by a ground potential in the remaining circuit portion. It is to provide a semiconductor device that can be used.
  • Another object of the present invention is to provide a high-frequency power module in which a circuit section such as a low-noise amplifier or RFVC0 is less likely to be affected by crosstalk due to fluctuations in the ground potential of other circuit sections in the high-frequency power module. To is there.
  • Another object of the present invention is to provide a wireless communication device capable of making a good call with less noise in a wireless communication system.
  • Another object of the present invention is to provide a wireless communication device capable of performing a good call with less noise in a wireless communication system having a plurality of communication systems.
  • a plurality of leads provided along the periphery of the sealing body and inside and outside the sealing body;
  • a tab having a main surface and a back surface
  • a semiconductor chip having a main surface and a back surface, a plurality of electrode terminals on the main surface, and a plurality of circuit portions each including a plurality of semiconductor elements;
  • a semiconductor device including a plurality of conductive wires connecting the plurality of electrode terminals and the main surface of the tab (for example, a non-leaded device) Semiconductor device)
  • the back surface of the semiconductor chip is fixed on the main surface of the tab,
  • the plurality of circuit units include a first circuit unit (specific circuit unit) and a second circuit unit,
  • the plurality of electrode terminals are a first electrode terminal for inputting an external signal to the first circuit unit, and a first potential (ground potential) for supplying the first circuit unit with the first potential.
  • the plurality of leads include a first lead (a signal lead), a second lead (a signal lead), and a third lead disposed between the first lead and the second lead.
  • the first electrode terminal is connected to the first lead via a conductive wire
  • the second electrode terminal is connected to the third lead via a conductive wire
  • the third electrode terminal is connected to the second lead via a conductive wire
  • the fourth electrode terminal is connected to a common ground via a conductive wire, as described above.
  • the third lead and the tab are electrically separated from each other
  • the first circuit unit is an amplifier circuit (low-noise amplifier: LAN) for amplifying an external signal input through the first lead and the first electrode terminal. This is a circuit for amplifying the electric signal converted through the circuit.
  • LAN low-noise amplifier
  • the second circuit unit processes the signal amplified by the first circuit unit. It has at least some of the functions to manage.
  • a plurality of communication circuits are formed in the high-frequency power module so as to be compatible with a plurality of communication systems.
  • Such a high-frequency power module is incorporated in a wireless communication device.
  • the electrode terminal of the semiconductor element is connected (down-bonded) to a tab serving as a common ground in addition to being connected to a lead via a wire.
  • the ground electrode terminal (electrode terminal of the semiconductor element) of the low-noise amplifier (specific circuit part) that amplifies a weak signal is not connected to the tab, but is connected to an independent lead terminal (lead for ground).
  • the ground potential is independent from other circuit sections, and the ground potential does not easily fluctuate even when the power of the other circuit section is turned on and off. Output fluctuations of the low-noise amplifier and distortion of the signal waveform are less likely to occur, and if incorporated in a wireless communication device, a good call without output fluctuations and distortion becomes possible.
  • the high-frequency power module is a bonded semiconductor device with a down-bonded structure that can be small, thin, and lightweight, and has a heat dissipation property because the tab is exposed on the back surface of the sealing body. Is good, and stable operation is possible. Therefore, by incorporating this high-frequency power module, it is possible to provide a small-sized and light-weight mobile phone having good call performance.
  • FIG. 1 is a schematic plan view in which a part of a sealed body of a high-frequency power module according to an embodiment (Embodiment 1) of the present invention is partially cut away.
  • FIG. 2 is a cross-sectional view of the high-frequency power module according to the first embodiment.
  • FIG. 3 is a schematic plan view of the high-frequency power module according to the first embodiment.
  • FIG. 4 is a schematic plan view schematically illustrating a circuit configuration of a semiconductor chip incorporated in the high-frequency power module according to the first embodiment.
  • FIG. 5 is a schematic plan view showing a connection state between external electrode terminals and respective circuit units such as a low-noise amplifier and a synthesizer of a semiconductor chip in the high-frequency power module of the first embodiment.
  • FIG. 6 is a flowchart showing a method of manufacturing the high-frequency power module according to the first embodiment.
  • FIG. 7 is a plan view of a lead frame used in manufacturing the high-frequency power module of the first embodiment.
  • FIG. 8 is a schematic plan view showing a unit lead frame pattern in the lead frame.
  • FIG. 9 is a schematic sectional view showing the lead frame on which a semiconductor chip is mounted.
  • FIG. 10 is a schematic sectional view showing the lead frame after wire bonding has been completed.
  • FIG. 11 is a schematic cross-sectional view showing the lead frame on which a sealing body is formed.
  • FIG. 12 is a block diagram showing a circuit configuration of a mobile phone in which the high-frequency power module of the first embodiment is incorporated.
  • FIG. 13 is a schematic cross-sectional view showing a mounting state of the high-frequency power module of the first embodiment in a mobile phone.
  • FIG. 14 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention, in which a part of a sealing body is cut away.
  • FIG. 15 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention, in which a sealing body is partially cut away.
  • FIG. 16 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 4) of the present invention, in which a part of a sealing body is cut away.
  • FIG. 17 is a schematic sectional view of the high-frequency power module according to the fourth embodiment.
  • FIG. 18 is a schematic cross-sectional view showing a modification of the high-frequency power module of the fourth embodiment.
  • FIGS. 1 to 13 are diagrams related to a semiconductor device (high-frequency power module) according to an embodiment (Embodiment 1) of the present invention and a wireless communication device incorporating the high-frequency power module.
  • 1 to 5 are diagrams relating to the high-frequency power module
  • FIGS. 6 to 11 are high-frequency power modules.
  • FIGS. 12 and 13 are diagrams relating to the wireless communication device.
  • the semiconductor device 1 constitutes, for example, a high-frequency power module.o
  • the QFN type semiconductor device 1 has a sealing body (package) 2 formed of a flat rectangular insulating resin.
  • a rectangular semiconductor element (semiconductor chip: chip) 3 is embedded in the sealing body 2.
  • the semiconductor chip 3 is fixed to the surface (principal surface) of the square cup 4 with an adhesive 5 (see FIG. 2).
  • the back surface (lower surface) of the sealing body 2 is the mounting surface side (mounting surface).
  • the tab 4 and the tab suspension lead 6 supporting the tab 4 and one surface (mounting surface 7a) of the lead (external electrode terminal) 7 are exposed.
  • the tab 4, the tab suspension lead 6 and the lead 7 are formed by a patterned metal (for example, copper) lead frame in the manufacture of the semiconductor device 1, and then cut and formed. You. Therefore, in the first embodiment, the tabs 4, the tab suspension leads 6, and the leads 7 have the same thickness. However, in the lead 7, since the inner end portion is formed thin by etching the back surface to a certain depth, the resin constituting the sealing body 2 enters under the thin lead portion. It is. This makes it difficult for the lead 7 to fall off the sealing body 2.
  • a patterned metal for example, copper
  • the tab 4 is supported by a tab suspension lead 6 having four narrow corners.
  • These evening suspension leads 6 are located on a diagonal line of the rectangular sealing body 2, and the outer end faces each corner of the rectangular sealing body 2.
  • Seal 2 is a flat square
  • the corners (corners) are chamfered to form slopes 2a (see Fig. 1).
  • the outer end of the evening suspension lead 6 slightly protrudes from this chamfered portion to 0.1 mm or less.
  • the protruding length is determined by the cutting type of the press machine used to cut the suspension lead in the lead frame state. For example, 0.1 mm or less is selected.
  • a plurality of leads 7 having an inner end facing the tab 4 are arranged at predetermined intervals along each side of the rectangular sealing body 2. .
  • the outer ends of the evening suspension leads 6 and 7 extend to the periphery of the sealing body 2. That is, the lead 7 and the tab suspension lead 6 extend inside and outside the sealing body 2.
  • the protruding length of the lead 7 from the sealing body 2 is determined by the cutting die of the press machine when cutting the lead in the state of the lead frame as in the case of the above-mentioned hanging suspension 6, for example, 0 Projects slightly less than 1 mm.
  • the side surface of the sealing body 2 is an inclined surface 2b (see FIG. 2).
  • the inclined surface 2b is formed on one surface of the lead frame to form the sealing body 2 on one side thereof, and then to facilitate removal when the sealing body 2 is removed from the mold mold cavity. This is due to the fact that the side surface of the cavity is inclined.
  • FIG. 1 is a schematic diagram in which the upper portion of the sealing body 2 is cut out so that the tab 4, the tab suspension lead 6, the lead 7, the semiconductor chip 3, and the like can be seen.
  • the exposed main surface of the semiconductor chip 3 is provided with an electrode terminal 9.
  • the electrode terminals 9 are provided on the main surface of the semiconductor chip 3 at substantially a predetermined pitch along each side of the square.
  • the electrode terminal 9 is connected to the inner end of the lead 7 via a conductive wire 10.
  • the head 4 is formed larger than the semiconductor chip 3, and the center of the main surface is formed.
  • a wire connection region is provided outside the semiconductor element fixing region, that is, on the peripheral portion of the tab 4.
  • the semiconductor chip 3 is fixed to the semiconductor element fixing region.
  • the other end of the conductive wire 10 whose one end is connected to the electrode terminal 9 of the semiconductor chip 3 is connected to the wire connection region.
  • the wire 10 connected to the tab 4 is called a down-bonding wire 10a. Since the wire bonding device performs wire bonding between the electrode terminal 9 and the lead 7 and wire bonding between the electrode terminal 9 and the tab 4, the wire 10 is also a down bonding wire 10a. Are also of the same material.
  • the purpose of adopting the down-bonding structure is to commonly use the tab to share the ground potential of each circuit section in the semiconductor chip.
  • the spark plug as a common ground terminal and connecting the spark plug and a number of electrode terminals to be the ground electrode terminals via wires, the external electrode terminals are lined up along the periphery of the sealing body.
  • the number of leads (pins) can be reduced, and the size of the sealing body can be reduced by reducing the number of leads. This leads to downsizing of the semiconductor device.
  • the sealing body 2 is provided between each lead 7 and the lead 7 and between the lead 7 and the tab suspension lead 6.
  • resin burrs generated during the formation. This resin burr portion is generated when the encapsulant 2 is formed in one side mode on one surface of the lead frame in the manufacture of the semiconductor device 1. After molding, the unnecessary lead frame is cut off, but when cutting the lead or tab hanging lead, the resin glue is also cut at the same time. Along with the edge of the lead 6, some resin burrs will remain between each lead 7 and the lead 7, and between the lead 7 and the tab suspension lead 6.
  • the back surface of the sealing body 2 has a structure that is recessed from the back surface (mounting surface) of the tab 4, the evening hanger lead 6, and the lead 7. This is because in a one-sided transfer molding mode, a resin sheet is placed between the upper and lower mold dies, and the mold is placed so that one side of the lead frame contacts this sheet. As a result, the sheet bites into the gap between the lead frames, so that the back surface of the sealing body 2 is retracted.
  • a plating film for surface mounting is formed on the surface of the lead frame. Therefore, the surfaces of the tab 4, the tab suspension lead 6, and the lead 7 exposed on the back surface of the sealing body 2 of the semiconductor device 1 have a plating film (not shown).
  • the back surface of the sealing body 2 is recessed, when the semiconductor device 1 is surface-mounted on a wiring board such as a mounting board, The feature is that the solder wet area is specified and the solder mounting is good.
  • the semiconductor device 1 includes a lead frame preparation (S101), a chip bonding (S102), a wire bonding (S103), and a sealing (S103). Mold: Manufactured through the following steps: S104), key processing (S105), and unnecessary lead frame cutting and removal (S106).
  • FIG. 7 is a schematic plan view of a lead frame 13 having a matrix configuration used when manufacturing the QFN type semiconductor device 1 according to the first embodiment.
  • unit read frame patterns 14 are arranged in 20 rows in the X direction and 4 columns in the Y direction, and one read frame 13 to 80 Semiconductor devices 1 can be manufactured.
  • Lee dofre Guide holes 15 a to 15 c used for transporting and positioning the lead frame 13 are provided on both sides of the frame 13.
  • an ejector pin hole 16 through which an ejector pin can be inserted is provided to separate the runner cured resin from the lead frame 13 by protruding the ejector bin.
  • the gate-hardened resin that has branched from this runner and hardened at the gate portion flowing into the cavity is peeled off from the lead frame 13 by protruding the ejector bin, the ejector pin hole 1 through which the ejector pin can penetrate 7 are provided.
  • FIG. 10 is a plan view showing a part of the unit lead frame pattern 14.
  • the unit lead frame pattern 14 is a pattern to be actually manufactured. May not always match.
  • the unit lead frame pattern 14 has a rectangular frame 18, and the tab suspension leads 6 extend from the four corners of the frame 18 to support the center tab 4. It has become.
  • a plurality of leads 7 extend inward from the inside of each side of the frame 18, and the inner ends thereof are close to the outer peripheral edge of the tab 4.
  • a plating film (not shown) is provided on the main surfaces of the tab 4 and the lead 7 for chip bonding and wire bonding.
  • the lead 7 has its backside on the tip side half-etched and thinned (see Fig. 2).
  • the leads 7 and the tabs 4 have a structure in which the periphery is formed so that the width of the main surface is wider than the width of the back surface, and is formed into an inverted trapezoidal cross section so that it is difficult to fall out of the sealing body 2. May be. It can also be manufactured by etching press.
  • -Also as shown in FIG. 10, on the main surface of the tab 4, the central rectangular area becomes the semiconductor element mounting portion 4a (the area surrounded by the two-dot chain line frame).
  • the outer area is the wire connection area 4b.
  • the semiconductor chip 3 is connected to the semiconductor element mounting portion 4 a of the unit 4 of the unit lead frame pattern 14 via the adhesive 5.
  • wire bonding is performed, and the electrode terminal of the semiconductor chip 3 and the tip of the lead 7 are connected with a conductive wire 10 while the predetermined electrode terminal and the tab 4 are connected.
  • the wire connection region 4b is connected by a conductive wire 10 (S103).
  • the wire connecting the electrode terminal and the wire connection area 4b of the tab 4 is particularly called a down-bonding wire 1Oa.
  • As the wire for example, a gold wire is used.
  • a sealing body 2 made of an insulating resin is formed on the main surface of the lead frame 13 (S104).
  • the sealing body 2 covers the semiconductor chip 3, the lead 7, and the like on the main surface side of the lead frame 13.
  • a portion indicated by a two-dot chain line frame is a region where the sealing body 2 is formed.
  • a masking process is performed (S105).
  • a plating film (not shown) is formed on the back surface of the lead frame 13.
  • This solder film is used as a bonding material when the semiconductor device 1 is surface-mounted, and is, for example, a solder plating film.
  • a Pd plating may be used on the entire surface of the lead frame 13 in advance, and in particular, a Pd plating lead frame 1 may be used.
  • the plating step after the sealing can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • an unnecessary lead frame portion is cut and removed (S106), and a semiconductor device 1 as shown in FIG. 1 is manufactured.
  • the thickness of the lead frame (evening 4, tab hanging lead 6, lead 7) is 0.2 mm, the thickness of chip 3 is 0.28 mm, and the thickness of semiconductor device 1 is 1.0 mm.
  • the width of the lead 7 is 0.2 mm, the length of the lead 7 is 0.5 mm, and the wire connection point (point) of the tab 4 is 1.0 mm from the end of the mounted chip 3.
  • the distance between lead and lead 7 is 0.2 mm.
  • the ground of the specific circuit portion is taken out as a ground electrode terminal, and connected to the lead via a wire. It is separated from the ground of the rest of the circuit.
  • the remaining circuit sections are connected to the common ground via wires as necessary, and are connected to leads as necessary.
  • the ground of the specific circuit portion and the ground of the other circuit portions are also insulated and separated from each other in the wiring in the semiconductor chip 3 by an interlayer insulating film or the like.
  • the crosstalk is caused by the fluctuation of the ground potential. This may cause output fluctuations and signal waveform distortions in the respective circuit sections.
  • high-frequency circuits with multiple communication circuits such as dual band and triple band
  • an induced current is generated in a communication circuit that is not operating in an operating communication circuit, and this induced current may enter the operating communication circuit as noise. Therefore, in the first embodiment, the ground electrode terminal (ground electrode terminal) of the specific circuit section is connected to an independent lead (ground lead) via a wire without being connected to the terminal.
  • crosstalk between input signal wirings may cause output fluctuations and signal waveform distortion in the respective circuit sections, especially in external signal input leads from antennas with small input signals. It is necessary to minimize the effects of crosstalk with the leads.
  • the semiconductor device 1 is a high-frequency power module for a triple band of a mobile phone.
  • L N A Because it is a triple band, three low-noise amplifiers (LNA) connected to the antenna are also arranged.
  • LNA low-noise amplifier
  • a single LNA is a specific circuit unit in a narrow sense in the present invention. That is, as shown in FIG. 5, there are two input signal wires from each LNA antenna. Then, in order to electromagnetically shield the two signal wires, the two signal leads are preferably placed between two signal leads and another signal lead, preferably on both sides of the two signal leads. Each has a ground lead.
  • each extended LNA is formed in a region of the semiconductor chip that is insulated and separated from other circuit sections.
  • the ground potential of each LNA is common.
  • FIG. 13 is a schematic cross-sectional view showing a mounting state of the semiconductor device (high-frequency power module) 1 of Embodiment 1 in a mobile phone.
  • the land 81 and the tab connected to the wiring correspond to the lead 7 and the tab 4 of the semiconductor device 1.
  • a fixed portion 82 is provided. Therefore, the semiconductor device 1 is positioned and mounted such that the leads 7 and the leads 4 of the semiconductor device 1 coincide with the land 81 and the fixed portion 82 and overlap with each other. Then, in this state, the solder plating film previously formed on the back surface of the lead 7 and the tab 4 of the semiconductor device 1 is temporarily melted (reflowed), and the lead 7 and the tab 4 are soldered with the solder 83. Connect (implement).
  • this mobile phone has a 900 MHz GSM communication system, a 800 MHz DCS 180 communication system, and a 900 MHz PCS 190 MHz communication system. 0 Signal processing of the communication system can be performed.
  • the block diagram in FIG. 12 shows the transmission system and the reception system connected to the antenna 20 via the antenna switch 21. Both the transmission system and the reception system are baseband chip chips. It is connected to 2 2.
  • the receiving system is composed of an antenna 20, an antenna switch 21, three band-pass filters 23 connected in parallel to the antenna switch 21, and the above-mentioned band-pass filter 23. Each has a low noise amplifier (LNA) 24 connected thereto, and a variable amplifier 25 connected to the three LNAs 24 and connected in parallel.
  • Each of these two variable amplifiers 25 has a mixer 26, a rover filter 27, a PGA 28, a one-pass filter 29, a PGA 30 and a one-pass filter 3, respectively.
  • 1, PGA 32, mouth-to-pass filter 33, and demodulator 34 are connected.
  • PGA 28, PGA 30, and PGA 32 are controlled by a control logic circuit section 35 for ADC / DAC & DC offset.
  • the two mixers 26 are controlled in phase by a 90-degree phase converter 40.
  • the I / Q modulator composed of the 90-degree phase converter 40 and the two mixers 26 corresponds to three LNAs in order to correspond to each band band. Each is provided, but in Figure 12 they are grouped together for simplicity.
  • the semiconductor chip 3 is provided with a synthesizer including an RF synthesizer 41 and an IF (Intermediate) synthesizer 42 as a signal processing IC.
  • the RF synthesizer 41 is connected to 11? 044 via a buffer 43, and controls the RFVC044 to output an RF local signal.
  • Two frequency dividers 37, 38 for the oral signal are connected in series to the knocker 43, and switches 48, 49 are connected to their output terminals. .
  • the RF local signal output from RFVC 04 is input to the 90-degree phase converter 40 by switching the switch 48.
  • the 90-degree phase converter 40 controls the mixer 26 by the RF signal.
  • the signal output mode of the RFVC044 When the signal output mode of the RFVC044 is in the Rx mode, it is 3780 to 3840 MHz for GSM, 3610 to 3760 MHz for DCS, and 3860 MHz for PCS. ⁇ 3980 MHz.
  • Tx mode is GSM It is 380 to 380 MHz, 380 to 3730 MHz for DCS, and 380 to 3980 MHz for PCS.
  • IF synthesizer 42 is connected to IFVC O (intermediate wave voltage controlled oscillator) 45 via frequency divider 46, and controls IFVC045 to output an IF local signal.
  • the frequency of the output signal according to IFVC045 is 640 MHz for each communication method.
  • the RF synthesizer 41 and the IF synthesizer 42 control VCXO (voltage controlled crystal oscillator) 50, output a reference signal, and send it to the baseband chip chip 22.
  • VCXO voltage controlled crystal oscillator
  • the IF signal is controlled by the synthesizer and the control logic circuit section 35 for ADCZ DAC & DC offset, and converted to baseband chip signals (I and Q signals) by the demodulator 34 and sent to the baseband chip 22.
  • the transmission system includes two mixers 61 that use the I and Q signals output from the baseband chip 22 as input signals, a 90-degree phase converter 62 that controls the phases of the two mixers 61, and An adder 63 that adds the outputs of the two mixers 61, a mixer 64 and a DPD (digital phase detector) 65 that both receive the output of the adder 63, and a mixer 64 and a DPD 65 that The output of the loop filter 66 and the output of the loop filter 66 and the two TXV COs (transmission voltage control oscillators) 67 and the outputs of the two TXV C06 7 It comprises a power module 68 and an antenna switch 21 both of which are inputs. Loop fill 6 6 is an external component.
  • a quadrature modulator is constituted by the mixers 61, 90-degree phase converter 62 and the adder 63.
  • the 90-degree phase converter 62 is connected to the frequency divider 46 via the frequency divider 47, and is controlled by the IF local signal output from the IFVC 045.
  • the outputs of the two TXVCs 067 are current sensed by the coupler 70. This detection signal is input to the mixer 72 via the amplifier 71.
  • the mixer 72 inputs the RF local signal output from the RFVC 044 via the switch 49.
  • the output signal of the mixer 72 is input to the mixer 64 and the DPD 65 together with the output signal of the adder 63.
  • the offset PLL Phase-Locked Loop
  • the frequency of the output signal from the mixer 72 is 80 MHz for each communication system.
  • the frequency of the output signal is 880 to 915 MHz.
  • the other TXVC 067 is for the DCS'PCS communication system, and the frequency of the output signal is 1710 to 1785 MHz, or 1850 to 1910 MHz.
  • the power module 68 incorporates a low-frequency power module and a high-frequency power module, and the low-frequency power module outputs a signal of 880 to 915 MHz.
  • the high-frequency power module receives a signal from the TXVC 067, which outputs a signal of 1710 to 1785 MHz or 1850 to 1910 MHz.
  • the signal is amplified and sent to antenna switch 21.
  • the logic circuit 60 is also formed monolithically in the semiconductor device 1 of the first embodiment, and sends an output signal to the paceband chip 22.
  • each circuit portion surrounded by a thick line in FIG. 12 is monolithically formed. Then, the three LNA 24 portions become the specific circuit portion 11 in the first embodiment (see FIGS. 4 and 5).
  • FIG. 4 and FIG. 5 are block plan views of the semiconductor chip 3 schematically showing part of each of these circuit portions.
  • Radio signals (radio waves) received by antenna 20 are converted into electrical signals, The signals are sequentially processed by each element of the receiving system and sent to the baseband chip 22.
  • the electric signal output from the baseband chip 22 is sequentially processed by each element of the transmission system and radiated from the antenna 20 as a radio wave.
  • FIG. 4 is a schematic layout diagram showing an arrangement of each circuit unit in the semiconductor chip 3.
  • electrode terminals (pads) 9 are arranged along the sides. Each circuit portion is arranged inside the electrode terminal 9 with a region divided.
  • a control logic circuit section 35 for ADC / DAC & DC offset is arranged in the center of the semiconductor chip 3, and mixers 26, 64 and three LNAs 24 are located on the left side thereof.
  • RFVC 044 is located on the upper side
  • RF synthesizers 41, VCX 050, IF synthesizer 42, IFV C045 are arranged on the right side from top to bottom
  • TXVC 06 7 is located on the lower side .
  • FIG. 5 shows the relationship between each circuit section (the first circuit section and the second circuit section) and its electrode terminal 9, and the connection state of the electrode terminal 9 and the lead 7 with the wire 10.
  • Wire 10 shows wire 10 connecting electrode terminal 9 and lead 7, and down-bonding wire 10a connecting electrode terminal 9 and tab 4.
  • Specific circuit section 1 1 first circuit Focusing on the three LNAs 24, the lead 7 to be connected to the bandpass filter 23, which is an external component, that is, the lead 7 described on the left with Signal, and the LNA 24 Signal electrode terminal 9 is connected via wire 10.
  • Two signal wirings from the electrode terminal 9 to the lead 7 via the wire 10 are provided, and on both sides of the two signal wirings, the ground electrode terminal 9 of the LNA 24, which is the specific circuit section 11, is provided.
  • a ground wire is formed by connecting to a ground lead 7 (GND and a lead 7 described on the left side in the figure) via a wire 10.
  • the other circuit section, at least the ground of each VC ⁇ and the ground of LNA 24 are insulated and separated, and the lead of other adjacent circuit section and LN 24 are separated. Electromagnetic shield between the leads of A24 is provided by ground lead 7. Adjacent LNAs 24 are also electromagnetically shielded by ground leads 7.
  • each circuit part of the transmission system that processes the electric signal output from the base chip chip 22 (for example, offset PLL, TXVC 0 67)), since the electrical signal is larger than the weak signal, it has a characteristic that it is more resistant to fluctuations in the ground potential and noise due to crosstalk. Therefore, the supply of the ground potential to the circuit section of the transmission system is made common to each VC ⁇ and the like via the tab 4, so that the number of leads 7 can be reduced. The size of the device can be reduced.
  • the LNA is a circuit that handles signals amplified by the LNA, such as a PGA, or a transmission circuit, for example, in order to prevent signal deterioration due to crosstalk between wirings formed on the main surface of the semiconductor chip 3. It is preferable to dispose it closer to the electrode terminal 9 so that the length of the wiring is shorter than that of the above.
  • the electrode terminal 9 of the semiconductor element (semiconductor chip) 3 is connected not only to the lead 7 via the wire 10 but also to the chip 4 ( Down-bonding).
  • the tab 4 becomes a common ground, so that the ground electrode terminal (electrode terminal of the semiconductor element) of the low-noise amplifier 24 which is the specific circuit section 11 is connected to the tab 4. Not connected, but connected to an independent lead terminal (ground lead).
  • the low-noise amplifier 24 Since the low-noise amplifier 24 amplifies a weak signal, the fluctuation of the ground potential causes the fluctuation of the output of the low-noise amplifier 24 and the signal waveform is distorted, but the ground of the low-noise amplifier 24 Circuit section of Since this is separated from the ground, fluctuations in the output of the low noise amplifier 24 and distortion in the signal waveform can be suppressed. As a result, by incorporating the wireless communication device into a wireless communication device, it is possible to perform a favorable call without output fluctuation or distortion.
  • the signal wiring from the electrode terminal 9 of the low-noise amplifier 24 to the lead 7 via the wire 10 is grounded on both sides thereof and is electromagnetically shielded. Therefore, the signal wiring is less susceptible to crosstalk.
  • the wireless communication device incorporating the high-frequency power module 1 can operate stably.
  • the high-frequency power module 1 is a non-lead type semiconductor device in which the lug 4 and the lead 7 are exposed on the back surface of the sealing body 2, the high-frequency power module 1 can be reduced in size and thickness. And lighter weight. Therefore, the wireless communication device incorporating the high-frequency power module 1 can be reduced in size and weight.
  • the high frequency power module 1 is connected to the electrode terminals 9 of the semiconductor chip 3. Down bonding where lead (pin) 7 is connected with wire 10 and tab 4 which is the ground potential and electrode terminal (ground electrode terminal) 9 of semiconductor chip 3 are connected with down bonding wire 10a. Because of this structure, the number of ground leads that become the external electrode terminals 7 can be reduced, the size of the sealing body 2 can be reduced by reducing the number of pins, and the size of the high-frequency power module 1 can be reduced. Can be achieved.
  • FIG. 14 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 2) of the present invention, in which a sealing body is partially cut away.
  • the RFVC044 that handles high frequencies is also a specific circuit unit 1 1 Therefore, all the ground electrode terminals 9 of the RFVC 04 4 are connected to the lead (ground lead) 7 via the wire 10, and are not connected to the tab 4 via the wire.
  • LNAs low-noise amplifiers
  • ground wiring is arranged on both sides of the two signal wirings of the RFVC044, and the signal wiring is shielded electromagnetically. I have.
  • the ground potential of the specific circuit unit 11 handling the high-frequency signal is insulated and separated from the ground potentials of the other circuit units, so that crosstalk does not occur.
  • FIG. 15 is a schematic plan view of a high-frequency power module according to another embodiment (Embodiment 3) of the present invention, in which a sealing body is partially cut away.
  • the third embodiment is an example in which the RFVC044 is an external component and is not formed monolithically on the semiconductor chip 3.
  • This dual-band communication method In the formula, the low noise amplifier, mixer, VCO, synthesizer, IQ modulator / demodulator, frequency divider, quadrature modulator, and other circuit sections are monolithically formed.
  • Each of the two mixers in the receiving system is controlled by a frequency divider, and this frequency divider converts the high-frequency signal output from the external component RFVC0 into a lower-frequency signal. It is a frequency conversion circuit.
  • the RFVC044 exists outside the semiconductor device 1, and the signal wiring of the RFVC044 is connected to the lead 7 of the two semiconductor devices 1. Is done. Then, the electrode terminals 9 on both sides of the two signal wires from the two leads 7 connected to the RFVC 0 4 to the electrode terminals 9 of the semiconductor chip 3 via the wires 10 and the leads 7 are connected to the wires 1 Connected via 0.
  • the electrode terminals 9 on both sides of the two signal wirings are ground electrode terminals, and the leads 7 connected to the ground electrode terminals via the wires 10 are also ground leads.
  • the signal wiring for handling the high-frequency signal is electromagnetically shielded, and the ground potential is independent of other circuit portions in the semiconductor chip 3. I have.
  • FIGS. 16 and 1 ⁇ relate to a high-frequency power module according to another embodiment (Embodiment 4) of the present invention.
  • FIG. 16 shows a part of a sealed body of the high-frequency power module.
  • FIG. 17 is a schematic cross-sectional view of the high-frequency power module.
  • a tab 4 serving as a common ground terminal and a lead 7 serving as a ground potential are electrically connected by a conductive wire 10b.
  • a conductive wire 10b are also used as ground external electrode terminals.
  • the tab 4 since the back surface of the tab 4 is exposed from the back surface (mounting surface) of the sealing body 2, the tab 4 can be used as an external electrode terminal for ground, and the wire 4 is connected to the tab 4.
  • the lead 7 connected via Ob can also be used as the ground external electrode terminal.
  • FIG. 18 shows a modification of the fourth embodiment. That is, in this modification, the back surface of the tab 4 is half-etched to be thin, so that the resin also wraps around the back surface of the tab 4 during the single-sided molding, as shown in FIG.
  • the backing 4 is completely buried in the sealing body 2 without its back surface also being exposed from the sealing body.
  • the lead 7 can be used as a ground external electrode terminal.
  • a structure in which the tab is embedded in the sealing body a structure in which the tab is bent one step higher in the middle of the tab suspension lead may be used.
  • the connection to the tab via the wire 10b is made.
  • the semiconductor device 1 in the present embodiment is mounted on the wiring board, the area under the semiconductor device 1 is also used for arranging the wiring on the wiring board because the semiconductor device 1 in this embodiment is covered with the sealing body 2. There is an advantage that it can be used as an area. Therefore, in the present embodiment, there is an advantage that the mounting density on the wiring board can be improved along with the miniaturization of the semiconductor device 1.
  • the present invention focuses on a power supply potential (first potential) suitable for applying the invention, for example, a power supply potential that can reduce the number of leads 7 by using a common electrode.
  • the present invention may be applied to the configuration of the electrode terminal 9 or the lead 7 for supplying the power supply potential.
  • the present invention is not limited to a non-lead type semiconductor device.
  • a QFP Quad Flat Package
  • SOP Silicon-Input Packet
  • a lead bent into a gull-wing shape protrudes along the periphery of the sealing body 2.
  • the same can be applied to a semiconductor device called (Small Outline Package) .However, compared to the QFP or SOP, a QFN type structure with a smaller lead protrusion around the encapsulation 2 is adopted. It is more preferable to achieve miniaturization of the equipment.
  • the semiconductor device of the present invention is used for a wireless communication device such as a mobile phone.
  • a wireless communication device such as a mobile phone.
  • the ground electrode terminal of the circuit section that processes an extremely weak input signal such as a low-noise amplifier is not connected to the common ground potential.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Amplifiers (AREA)
PCT/JP2002/004339 2002-04-30 2002-04-30 Semiconductor device and radio communication apparatus WO2003094236A1 (en)

Priority Applications (19)

Application Number Priority Date Filing Date Title
PCT/JP2002/004339 WO2003094236A1 (en) 2002-04-30 2002-04-30 Semiconductor device and radio communication apparatus
CNB2007101273468A CN100536123C (zh) 2002-04-30 2003-04-28 半导体器件和电子设备
PCT/JP2003/005475 WO2003094232A1 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
KR1020087009552A KR100993579B1 (ko) 2002-04-30 2003-04-28 반도체장치 및 전자 장치
CNB038096366A CN100380651C (zh) 2002-04-30 2003-04-28 半导体器件和电子设备
CNA2009101340438A CN101515579A (zh) 2002-04-30 2003-04-28 半导体器件和电子设备
CNA2009101340423A CN101515578A (zh) 2002-04-30 2003-04-28 半导体器件和电子设备
JP2004502352A JP4351150B2 (ja) 2002-04-30 2003-04-28 半導体装置及び電子装置
US10/512,459 US7425756B2 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
AU2003235967A AU2003235967A1 (en) 2002-04-30 2003-04-28 Semiconductor device and electronic device
KR1020087009547A KR100993277B1 (ko) 2002-04-30 2003-04-28 반도체장치 및 전자 장치
KR1020047017429A KR100993276B1 (ko) 2002-04-30 2003-04-28 반도체장치 및 전자 장치
US11/455,171 US20060237831A1 (en) 2002-04-30 2006-06-19 Semiconductor device and electronic device
US11/455,157 US7312511B2 (en) 2002-04-30 2006-06-19 Semiconductor device with electrically isolated ground structures
US12/032,690 US7937105B2 (en) 2002-04-30 2008-02-17 Semiconductor device and electronic device
US12/033,061 US7777309B2 (en) 2002-04-30 2008-02-19 Amplifier chip mounted on a lead frame
JP2009142145A JP5080532B2 (ja) 2002-04-30 2009-06-15 半導体装置
US13/094,383 US8126501B2 (en) 2002-04-30 2011-04-26 Semiconductor device and electronic device
JP2012128107A JP5473026B2 (ja) 2002-04-30 2012-06-05 半導体装置

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