Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
  • H01L21/67063—Apparatus for fluid treatment for etching
  • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
  • H01J37/32366—Localised processing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
  • H01L21/67063—Apparatus for fluid treatment for etching
  • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
  • H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

• This invention relates to a method and apparatus for shaping thin films on in-process semiconductor substrates. More particularly, this invention relates to a method and apparatus for shaping thin films in the near-edge regions of in-process semiconductor substrates employing plasma techniques.
• the invention provides an apparatus and method for shaping a thin film on a wafer.
• the apparatus of the invention employs a rotatable chuck for holding a wafer, a housing having a slot for receiving an edge of a wafer on the chuck, at least one plasma source mounted on the housing for generating a flow of reactive gas and a channel in the housing communicating with the plasma source to direct the flow of reactive gas toward the edge of the wafer in the slot of the housing.
• an exhaust plenum is disposed within the housing for receiving the reactive gas and an exhaust line communicates with and extends from the exhaust plenum for expelling reactive gas from the plenum.
• At least one additional channel in the housing radially within the first channel for directing a flow of diluent/quenching gas onto the wafer; and at least one exhaust channel in the housing between this additional channel and the first channel for exhausting the diluent/quenching gas and reactive gas therefrom.
• the housing is of semi-circular shape to receive a major portion of the wafer on the chuck in the slot but may be of any other suitable shape.
• the apparatus may also be constructed with multiple sets of the inlet channels and exhaust channel and a plurality of plasma sources, for example, three plasma sources spaced circumferentially of the housing, for selectively etching of a polymer on a wafer, etching of silicon dioxide on a wafer and depositing an encapsulating silicon dioxide layer on a wafer.
• a plurality of plasma sources for example, three plasma sources spaced circumferentially of the housing, for selectively etching of a polymer on a wafer, etching of silicon dioxide on a wafer and depositing an encapsulating silicon dioxide layer on a wafer.
• the method of the invention comprises the steps of mounting a wafer having a thin film on a rotatable chuck; directing a flow of diluent/quenching gas onto the wafer in a radially outward direction; exhausting the flow of diluent/quenching gas from the wafer downstream of the flow of diluent/quenching gas; directing a flow of reactive gases towards the wafer radially outward of the diluent/quenching gas to react with the wafer; and rotating the wafer relative to the flow of reactive gas to remove film fragments from the edge of the wafer or to deposit material on the wafer.
• the wafer is moved in a rectilinear direction relative to the flow of reactive gas to allow removal of material from the thin film normally on the wafer while shaping the thin film to a predetermined shape. Thereafter, a second flow of reactive gases can be directed towards the wafer radially outward of the diluent/quenching gas to react with the wafer to deposit material thereon while the wafer is rotated to deposit a thin protective film of the material on the shaped thin film on the wafer.
• the processing capability enabled by the method and apparatus described herein addresses both removal of the flaking films and control of the film shape that remains after processing.
• the film shaping capability allows for the use of conventional cleaning processes without particle trapping. Further, the process can also encapsulate the freshly processed surface with a thin film that prevents future flaking.
• an in-process semiconductor substrate wafer
• the platen is sufficiently smaller, in diameter, than the wafer, allowing access to all of the edge surfaces of the wafer.
• the platen is attached to a spindle, which, in- turn, is connected to a rotational electro-mechanical system.
• the electro-mechanical system enables computer control of the rotational movement of the wafer during processing.
• the entire platen assembly is mounted on a 3-axis (X, Y, Z) linear electro-mechanical positioning device.
• Plasma sources similar to one described in US Patent 5,961 ,772, are located in proximity to the edge surfaces of the wafer.
• the gaseous output-flow from the plasma source (the flame) is directed to impinge on the edge surfaces by means of gas flow hardware design and electro-mechanical positioning devices (X, Y and Z wafer motion axes).
• Proper selection of the input gases will determine the nature of the processing performed on the wafer. Certain gas mixtures will cause material on the wafer to react with the constituents in the flame such that the reaction by-products are volatile at the operating pressure. In such cases, the process is subtractive and is commonly referred to as etching. Other input gas mixtures will cause flame constituents to react with each other to deposit material onto the wafer. In such cases, the process is additive and is commonly referred to as chemical vapor deposition (CVD).
• CVD chemical vapor deposition
• the dwell time of the reactive gas flow on any one location of the wafer's edge surfaces shall be controlled via the computer controlled, electro-mechanical positioning devices.
• the flame shall be commanded to dwell for longer times on areas where large material removal is desired and dwell shorter times on areas where less material removal is desired.
• the flame shall be commanded to dwell longer times where thicker films are desired and shorter times where thinner films are desired.
• a flow of diluent and/or quenching gas shall be provided.
• the diluent and/or quenching gas flow is oriented to inhibit the diffusion of reactive gases from affecting areas on the wafer not intended for processing.
• adjustable exhaust ports will be employed to direct the reactive gas flow away from the areas not intended for processing.
• Fig. 1a illustrates a part cross-sectional view of a wafer having flaking film fragments in a peripheral edge region
• Fig. 1 b illustrates the wafer of Fig. 1a after application of a photoresist coating in accordance with a prior art technique to remedy flaking film;
• Fig. 1c illustrates the wafer of Fig. 1 b after exposure of the photoresist in accordance with the prior art technique
• Fig. 1d illustrates the wafer of Fig. 1c after development of the photoresist in accordance with the prior art technique
• Fig. 1e illustrates the wafer of Fig. 1d after a wet or dry thin film etch in accordance with the prior art technique
• Fig. 1f illustrates the wafer of Fig. 1e after a photoresist strip and cleaning in accordance with the prior art technique
• Fig. 2a illustrates a part cross-sectional view of a wafer having flaking film fragments in a peripheral edge region
• Fig. 2b illustrates a part cross-sectional view of the wafer of Fig. 2a after removal of the flaking film fragments and shaping of the remaining film topography in accordance with the invention
• Fig. 2c illustrates the wafer of Fig. 2b after encapsulation of the processed surface in accordance with the invention
• Fig. 3 illustrates a schematic side view of an apparatus for etching of the peripheral edge region of a wafer in accordance with the invention
• Fig. 4 illustrates a plan view of the apparatus of Fig. 3;
• Fig. 5 illustrates an enlarged view of a peripheral edge region of a wafer during etching in accordance with the invention.
• Fig. 6 illustrates a schematic side view of an apparatus for thin film deposition onto the peripheral edge region of a wafer in accordance with the invention
• Fig. 7 illustrates an enlarged view of a peripheral edge region of a wafer during thin film deposition in accordance with the invention.
• a previously known technique for edge bead removal frequently results in topography near the edge of a wafer 10 that is not readably cleanable and that traps particles.
• the wafer 10 is provided with a coating 11 of any suitable material.
• fragments 12 may break away in the form of thin film flakes.
• a photoresist coat 13 is applied. After the photoresist coating 13 is exposed using conventional techniques, as indicated in Fig. 1c, and subsequently developed as indicated in Fig. 1d, the coating 11 and flakes 12 at the peripheral edge of the wafer 10 are again exposed.
• a wet or dry thin film etch step may then be carried out to remove the coating 11 and flakes 12 at the peripheral edge of the wafer 10, as indicated in Fig. 1e (depicts a wet etch profile). Finally, the photoresist 13 is stripped and the surface is cleaned as indicated in Fig. 1f. However, small particles 14 may become trapped in the region where the coating 11 ends on the wafer 10.
• the invention proposes to process a coated wafer as shown in Fig. 2a by removing the flaking film fragments and shaping the remaining film topography in a manner as illustrated.
• the peripheral edge of the coating 11 is tapered radially outwardly to adjacent the outermost periphery of the wafer 10.
• the processed surface of the coating 11 is encapsulated within a layer 15.
• a wafer 10 is placed on a vacuum chuck 16 that is able to move horizontally in the X and Y axes and also vertically in the Z axis.
• the vacuum chuck, 16, is configured with a rotational axis, ⁇ , as shown.
• the vacuum chuck is typically incorporated in an electro-mechanical system (not shown) having suitable means for moving the vacuum chuck 16 with these 4 degrees of freedom (X, Y, Z, ⁇ ).
• three plasma sources, 17t, 17e and 17b are respectively located in proximity to the top side, the edge and the bottom side of the wafer 10 in order to supply the reactive gas flow toward the three surfaces of the wafer 10.
• Each plasma source is constructed, such as the atmospheric pressure plasma jet described in US Patent 5,961 ,772. This arrangement of three plasma sources allows for maximum flexibility in processing options as follows:
• a pair of flow channels 19 and 20 associated with each plasma source 17 provide a means to control the unwanted diffusion of reactive gas flow onto portions of the wafer 10 where processing is unwanted.
• Channel 19 supplies a diluent or quenching gas flow inward toward the wafer, 10, and directed radially outwards towards the edge of wafer 10.
• Fine exhaust channel 20 provides an exhaust flow directed outward from the plane of the wafer 10.
• Conductance adjustment valve, 21 is tuned to match the diluent or quenching gas flow rate of the channel, 19.
• Reactive gases from plasma source 17 that diffuse towards the center of the wafer are neutralized, entrained in the exhaust flow and removed via fine exhaust channel 20. This technique provides for the sharp boundary between the processed and unprocessed regions.
• the plasma sources, 17, are mounted to a semi-circular housing, 18.
• the housing includes a slot 22 for receiving the wafer 10 as indicated in Fig. 3, the housing 18 is equal to or approximately equal to one-half the size of the wafer 10.
• the housing also includes an exhaust plenum, 23, which is connected to the exhaust source (not shown) via an adjustable conductance control valve 24.
• each set can operate independently with respect to process chemistry. For example, one set can perform etching of polymers, as indicated by 17', 19', 21' and 24', while another set performs etching of Si0 2 , as indicated by items, 17, 19, 21 and 24, while a third set, as indicated by items 17", 19", 21" and 24", deposits an encapsulating Si0 2 layer.
• the first column contains the input gases.
• the second column contains the active output species.
• the third column contains the type of process performed and the fourth column contains the thin film addressed by the process.
• a typical sequence of events to shape an Si0 2 thin film on the top surface of a wafer followed by an Si02 CVD encapsulation process as depicted in Figs. 2a, 2b and 2c is described below: 1.
• a well-centered wafer, 10, is placed on the vacuum wafer platen, 16.
• the vacuum wafer platen is moved in X, Y and Z such that the wafer is centered within the slot, 22, and the edge portion of the wafer is located immediately adjacent to diluent / quenching gas supply channels 19t and 19b.
• Diluent / quenching gas flow rate setpoints are sent to the mass flow controllers (MFC) 25t and 25b and the diluent / quenching gas shutoff valves 26t and 26b are commanded to open. Gas begins to flow down diluent / quenching gas supply channels 19t and 19b and impinges on the edge of the wafer 10.
• MFC mass flow controllers
• Fine exhaust channel conductance control valve, 21t is commanded open to a predefined position. (Conductance control valve 21b is not opened. This allows the diluent / quenching gas flow from channel 19b to protect the backside of the wafer 10 from unwanted diffusion of reactive gases).
• Process gas flow rate setpoints are sent to the process input gas MFCs (not shown) and process input gas shutoff valve 27t is commanded to open. Process input gases He, 0 2 and CF 4 begin to flow through channel 30t.
• the conductance control valve 24 of housing exhaust plenum 23 is commanded to a pre-defined position.
• a forward power setpoint is sent to the RF power supply 29t and the RF power is commanded on.
• a plasma is formed inside the plasma source 17t and reactive gases begin to flow through channel 30t into the housing exhaust plenum 23 and out through the conductance control valve 24 to the exhaust system (not shown).
• the impedance matching network, 28t tunes the load impedance to match the output impedance of the RF power supply 29t.
• the control system (not shown) compares the magnitude of the power reflected back to power supply 29t to a pre-defined threshold value.
• the control system (not shown) decides to halt the process or continue based upon the reflected power comparison.
• a successful comparison signifies formation of a stable plasma inside plasma source 17t.
• the vacuum wafer platen 16 is commanded to begin rotating at a predefined angular velocity.
• the vacuum wafer platen 16 is commanded to move in the X, Y and Z axes, positioning the edge surfaces into the reactive gas stream flowing from reactive gas channel 30t. 11.
• the shaping of the thin films is controlled by the dynamics of the vacuum wafer platen's, 16, motion as follows:
• the exhaust plenum 23 directs the effluent flow towards the exhaust system (not shown) under control of the conductance control valve 24.
• the vacuum wafer platen 16 is commanded to reverse direction and move in a smoothly decelerating motion until it arrives back at its starting position. The described motion will yield an Si0 2 removal profile that, when applied to the thin film shape 11 and 12 depicted in Fig 2a, will result in the thin film shape 11 depicted in Fig 2b.
• the housing exhaust plenum's conductance control valve 24 is closed.
• certain metal films may have become exposed during the oxide removal step.
• an encapsulating Si0 2 thin film 15 can be deposited as follows:
• diluent / quenching gas flow rate setpoints are sent to the mass flow controllers (MFC) 25t" and 25b" and the diluent / quenching gas shutoff valves 26t" and 26b" are commanded to open.
• Gas begins to flow down diluent / quenching gas supply channels 19t" and 19b" and impinges on the edge of the wafer 10.
• Fine exhaust channel conductance control valve 211" is commanded open to a predefined position. (Conductance control valve 21b" is not opened. This allows the diluent / quenching gas flow from channel 19b" to protect the backside of the wafer 10 from unwanted diffusion of reactive gases).
• Process gas flow rate setpoints are sent to the process input gas MFCs (not shown) and process input gas shutoff valve 27t" is commanded to open. Process input gases He, TEOS and 0 3 begin to flow through channel 30t".
• the conductance control valve 24" of the housing exhaust plenum 23 is commanded to a pre-defined position.
• a forward power setpoint is sent to the RF power supply 29t" and the RF power is commanded on.
• a plasma is formed inside the plasma source 17t" and reactive gases begin to flow through channel 30t" into the housing exhaust plenum 23 and out through the conductance control valve 24" to the exhaust system (not shown).
• the impedance matching network 28t tunes the load impedance to match the output impedance of the RF power supply 29t".
• the control system (not shown) compares the magnitude of the power reflected back to power supply 29t" to a pre-defined threshold value.
• the control system (not shown) decides to halt the process or continue based upon the reflected power comparison.
• a successful comparison signifies formation of a stable plasma inside plasma source 17t".
• the vacuum wafer platen 16 is commanded to begin rotating at a predefined angular velocity.
• the vacuum wafer platen 16 is commanded to move in the X, Y and Z axes, positioning the edge surfaces into the reactive gas stream flowing from reactive gas channel 30t".
• the shaping of the thin film deposition is controlled by the dynamics of the motion of the vacuum wafer platen 16 as follows:
• the exhaust plenum 23 directs the flow towards the exhaust system (not shown) under control of the conductance control valve 24".
• the vacuum wafer platen 16 is commanded to reverse direction and move in a smoothly decelerating motion until it arrives back at its starting position. The described motion will yield an Si0 2 thin film deposition profile that, when applied to the thin film shape 11 depicted in Fig 2b, will result in the deposited thin film shape 15 depicted in Fig 2c.
• the housing exhaust plenum's conductance control valve 24" is closed.
• the wafer 10 can be removed from the vacuum wafer platen 16.
• the shape of the etched surface can be nearly anything. The limiting factors are the spatial frequency capabilities of the reactive gas footprint shape and the servo system dynamic response. Other shapes of interest might include convex or concave shapes or shapes that intersect the wafer top surface plane further in from the edge.
• the protective thin film 15 may be of any suitable thickness. Typically, the film 15 is thin enough such that none of the layer of film 15 extends above the plane of the remaining film 11 and thick enough to be mechanically strong enough to weather the stresses exerted by the film 11 the protective film 15 is covering. For example, a thickness of 0.1 to 0.3um should be sufficient. The thickness of the layer of film 15 may also be varied in the same way the etching process profile is varied, via a spatial variation of the reactive gas footprint dwell time. The invention thus provides an apparatus and method of shaping thin films in the regions of in-processs semiconductor substrates that are economical and relatively simple and efficient.
• the invention also provides a method that allows flakes to be readily removed from a semiconductor substrate and the edge region of the processed substate to be contoured to a desired shape.

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• 2003
  • 2003-03-27 US US10/401,074 patent/US6936546B2/en not_active Expired - Fee Related
  • 2003-04-24 AU AU2003225127A patent/AU2003225127A1/en not_active Abandoned
  • 2003-04-24 KR KR10-2004-7017253A patent/KR20050010770A/ko not_active Abandoned
  • 2003-04-24 EP EP03721837A patent/EP1500129A4/en not_active Withdrawn
  • 2003-04-24 WO PCT/US2003/012615 patent/WO2003092337A2/en not_active Ceased
  • 2003-04-24 JP JP2004500540A patent/JP2005524235A/ja active Pending
• 2005
  • 2005-05-18 US US11/131,611 patent/US20050205518A1/en not_active Abandoned

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