Classifications

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  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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  • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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  • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
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  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
  • H01L25/0657—Stacked arrangements of devices
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  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
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  • H01L2924/151—Die mounting substrate
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  • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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  • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
  • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
  • H05K1/0231—Capacitors or dielectric substances
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  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0266—Marks, test patterns or identification means
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  • H05K1/02—Details
  • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
  • H05K1/0298—Multilayer circuits
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  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
  • H05K1/144—Stacked arrangements of planar printed circuit boards
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  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
  • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/04—Assemblies of printed circuits
  • H05K2201/045—Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
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  • H05K2201/04—Assemblies of printed circuits
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  • H05K2201/09—Shape and layout
  • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
  • H05K2201/09954—More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
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  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10431—Details of mounted components
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  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
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  • H05K2203/15—Position of the PCB during processing
  • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/341—Surface mounted components
  • H05K3/3431—Leadless components
  • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

• the present invention relates to an integrated circuit chip carrier. More particularly a carrier that allows for an increase in the density of integrated circuit (IC) chips mounted on a printed circuit board and among other things, is adaptable to connecting a wide variety of standard IC chip package designs to a printed circuit board in a three dimensional array as well as a system and method for testing the carrier and chips while all are connected into the circuitry of a larger system.
• IC integrated circuit
• Semiconductor chips are typically connected to a printed circuit board or similar structure that in turn interconnects the chips into the rest of circuitry ofthe computer with which the chip will operate, including other chips on the printed circuit board.
• the chips were spread out across the printed circuit board on their large flat sides in a simple two-dimensional array.
• the trend in the computer industiy has been towards more densely packed configurations of chips on a printed circuit boards.
• the causes for this are the increasing demand for larger random access computer memories, demand for faster computers, demand for more compact computers and a push to decrease costs of printed circuit boards by increasing the circuit density on the printed circuit board.
• the move to surface mount technology resulted in the practice of positioning the chips on the printed circuit board in a variety of configurations to increase chip density on the circuit board and thereby decrease the distance between the chips to speed up operation ofthe overall system.
• Layering or positioning the chips on one another to form a three dimensional array is one of the means used to increase chip density on the printed circuit board.
• the practice of positioning or layering the chips on one another to form a three dimensional array is particularly adaptable to memory chips given the redundancies in their circuits.
• An example of a significant advance in the stacking of semiconductor chips on a printed circuit board is described in US patent 6,313,998, which is incorporated by reference herein, it being owned by the same entity as the instant application.
• US patent 6,313 ,998 discloses a carrier with leads and a unique way of positioning one chip over another.
• BGA ball grid array
• BGA types of connectors have their own problems among them being an inability to test the BGA connected device while it is connected into the circuitry of a board or other device.
• IC packages that are connected by leads on the other hand are very easy to test while the device is still connected into the circuit since the long leads can readily have test probes attached to them.
• BGA connected devices by the very nature of the connection are impossible to directly or even indirectly test while they are connected into the circuit.
• a BGA packaged chip by its very nature is connected by blind pads, i.e. non-exposed pads that can not be accessed.
• Another problem with BGA type of connectors is the need to develop new techniques that will allow for stacking chips since many if not most ofthe techniques used to stack chips are for integrated circuit packages that use leads and cannot be readily adapt to BGA type of connectors. Additionally, most ofthe existing chip stacking devices and methods used to form chips into a three dimensional array tend to be very complicated. They typically cannot work with standard IC packages, be they the lead type or BGA type and generally require the modification of the chip package itself for implementation. Additionally, many if not most of the existing stacking methodologies require special manufacturing steps and/or machines in order to integrate them into standard circuit board assembly and similar processes.
• CSP chip scale packages
• a carrier for stacking integrated circuit chips having: a.) a platform with a top surface and a bottom surface; b) a first strut at a first side of the platform and a second strut at a second side of the platform, the struts providing support for the platform and thereby creating a space below the bottom surface of the platform; c) the platform having a pattern of BGA pads on its top surface for receiving at least one integrated chip on the top surface on the pattern of BGA pads, a bottom side of each pad of the pattern of pads being connected to a via that pass down through the platform to a lower layer in the platform wherein the via connects to a conductive path that extend towards the first or second strut; d) the first and second struts having strut vias that extend up through each strut from the bottom of the strut to the top ofthe strut wherein each ofthe strut vias connect to a specific conductive path in the platform which specific conductive
• the upwardly extending vias in the first strut extend up to a top edge ofthe first side ofthe platform to thereby expose a top surface of the upwardly extending vias on the top surface ofthe platform and the upwardly extending vias in the second strut extend up to top edge ofthe second side ofthe platform to expose a top edge ofthe upwardly extending vias on the top surface ofthe platform.
• the invention provides a way to position the pads on which a chip rests directly over a descending via. It does this by filing in the hollow portions left in a via after its fabrication with a non-conductive or conductive filler material. This reduces the space necessary for the pads by avoiding the need to offset the pads from the vias.
• the invention provides a system that can be used with BGA type of connectors, CSP type of connectors or other similar connection arrangements. Additionally, it provides away for testing the components when they are still connected to the carrier ofthe present invention and connected to a circuit board by providing accessible contact pads points that in one preferred embodiment include adjacent electrical grounds for a testing probe.
• Fig. 1 is aperspective view of apreferred embodiment ofthe carrier of the present invention.
• Fig. 2 is a side view of a carrier ofthe present invention connected to a circuit board and stacked with two IC chips;
• Fig. 3 is an exploded view ofthe carrier ofthe present invention and components with which it would be connected to a circuit board;
• Fig. 4 is a cross sectional view along line I - 1 of the carrier depicted in Fig. 1;
• Fig. 5 A is a schematic view of a prior art method for connecting a BGA pad to a circuit board
• Fig. 5B is a cross sectional view ofthe BGA pad and connection in Fig. 5A;
• Fig. 5C is a cross sectional view of a connection technique use in a preferred embodiment of the present invention.
• Fig. 5D is a cross- sectional view of a connection technique used in a preferred embodiment ofthe present invention.
• Fig. 6 is a schematic view of typical circuitry on a lower routing layer ofthe carrier ofthe present invention.
• Fig. 7A - 7D provide one example of primary layers that make up the various layers of one example ofthe carrier ofthe present invention
• Fig. 8A is a cross sectional schematic view of the principal layers of one version of the carrier ofthe present invention
• Fig. 8B is a cross section of a portion ofthe carrier ofthe present invention that shows the layers that make up the carrier
• Fig. 8C is a cross sectional view of one embodiment of a pad and part of a via in the strut of.
• Fig. 9 is a cut away perspective view of a version of the carrier of the present invention attached to a circuit board with stacked BGA devices;
• Fig. 10 is an exploded view of double- stacked carriers ofthe present invention with BGA devices
• Fig. 11 is an end view of two carriers ofthe present invention stacked with BGA devices
• Fig. 12 is a side view of two carriers ofthe present invention stacked with BGA devices
• Fig. 13 is a view of another version ofthe carrier ofthe present invention in which IC chips are attached to both sides ofthe carrier;
• Fig. 14 provides a schematic type diagram of one way to connect the pads on the version of the carrier depicted in Fig. 13;
• Fig. 15 is a cross sectional view along line II - II of Fig. 14;
• Fig. 16 is a top view of a circuit board to which the carriers ofthe present invention have been attached and before IC chips are placed on top ofthe carriers;
• Fig. 17 is a view ofthe board of Fig. 16 in which IC chips have been attached to the top of each carrier;
• Fig. 18 is a schematic diagram of another type of BGA array with which the present invention can work.
• Fig. 19 provides a table of pin connections between the pads ofthe carrier as depicted in Fig. 18;
• Fig. 20 is a view of a corner of a carrier ofthe present invention showing a via descending from a decoupling capacitor pad;
• Fig. 21 is a perspective view of the carrier of the present invention with an alternate placement of decoupling capacitors
• Fig. 21A is a cross sectional view ofthe carrier in Fig. 21 along line XX-XX;
• Fig.2 IB is a view of a corner of a carrier ofthe present invention showing an alternative way for connecting the decoupling capacitors;
• Fig. 22 is a schematic of electrical connections on a substrate layer of the carrier of the present invention.
• Fig. 1 is a perspective view of a preferred embodiment of the chip carrier 21 of the present invention.
• Chip carrier 21 has top platform 23 and two side struts 25 and 27.
• An array of BGA pads 29A and 29B on the top of platform 23 are positioned to receive an IC chip that connects by means of a BGA pad array.
• pads 29A and 29B connect to vias that descend into platform 23 and then connect by conduction lines running laterally to vias in struts 25 and 27.
• Top exposed portions 33 of each ofthe vias in struts 25 and 27 can be seen at the top edge of platform 23 above each strut, 25 and 27.
• each ofthe vias in strut 25 and 27 descent down through strut 25 and 27 and end at a pad or exposed portion to which a solder ball 37 can be attached.
• Carrier 21 in one of its preferred embodiments has pads 41 for receiving decoupling capacitors 43 on the top of plate form 23. As will be illustrated below the decoupling capacitors connect into the circuitry through appropriately placed vias and conduction lines. Additionally, placement ofthe decoupling capacitor next to the IC chip enhances operation. The invention thus provides for proper decapacitive decoupling.
• Fig. 2 provides a side profile view of a canier 21 ofthe present invention connected to a circuit board 49 with integrated circuit (IC) chips 51 and 52.
• IC chip 51 connects to carrier 21 by means of pads sets 29A and 29B (shown in Fig. 1).
• IC chip 52 connects by means of a similar BGA pad array sets to board 49.
• Decoupling capacitors 43 are positioned on carrier 21 at the corners of its platform 23.
• the array of pads 29A and 29B on platform 23, to which balls 61 ofthe BGA array of IC chip 51 attach have vias descending below them into platform 23 which connect to conductive lines that connect to vias in struts 25 and 27.
• Solder balls 37 connect to the bottoms of the vias in struts 25 and 27 to board 49 and provide the final electrical connection to board 49.
• IC chip 52 connects to board 49 through solder balls 63 in the typical BGA pad array on board 49 not shown.
• the pads of the decoupling capacitors 43 have their own conductive vias descending down through each strut 25 and 27 that terminate in a solder ball 37.
• the decoupling capacitors allow for impedance control, help control return current and store charge.
• Fig. 3 provides an exploded view of board 49, IC chip 52, carrier 21 and IC chip 51.
• Carrier 21 connects to board 49 by means of BGA pad array 65A and 65B.
• Board 49 would have a series of sets of IC chips arranged in a three dimensional array by use of carriers which are the same as or similar to canier 21.
• Board 49 is the typical printed circuit board with layers of metalized and prepreged sheets that form a laminate structure with various conducting lines in it, not shown, that connect the devices, in this case IC chip 52 and carrier 21 and thus IC chip 51.
• Board 49 has connectors 69 along its bottom edge that connect the internal lines within board 49 to the rest of a system when board 49 is plugged into the appropriate socket in a computer.
• Board 49 is the typical board that might hold IC memory chips or similar chips.
• Fig.3 is only meant to provide an example of one setting in which the present invention and can be used.
• the present invention can be used in a wide variety of other configurations of printed circuit boards including positioning them on the main motherboard of a computer.
• Carrier 21 in its preferred embodiment is made in the same fashion as a printed circuit board in that it has laminate layers with vias and conducting lines laid out in the layers of platform 23 and struts 25 and 27 of carrier 21.
• Fig.4 provides a cross-sectional view of carrier 21 along line I - 1 of Fig. 1.
• Platform 21 has pads sets 29A and 29B on top and vias 73A, 73B, 73C and 73D.
• Nias 73 A, 73B, 73C and 73D descend to connecting paths 75A, 75B, 75C and 75D.
• the connecting path for pad 75B is behind path 75A and thus hidden by 75A.
• connecting path 75C is partially hidden by connecting path 75D.
• all ofthe connecting paths are electrically isolated from each other.
• the connecting paths 75A and 75B and 75C and 75D appear to run into together as will be explained below with another figure it is a matter ofthe perspective of the drawing.
• the conductive paths 75 A, 75B, 75C and 75D from each ofthe vias 73A, 73B, 73C and 73D run to vias in one ofthe struts 25 and 27. This is best illustrated by conductive path 75D that runs from via 73D to via 77D in strut 27and conductive path 75A that runs from via 73 A to via 77A in strut 25.
• the conductive paths and vias are electrically conductive paths.
• the vias are made of a copper core in the preferred embodiment and the conductive paths also are made of copper.
• via 77D and 77A are copper cores and vias 73A, 73B, 73C and 73D are copper cores.
• Conductive paths 75A, 75B and 75D are all made of copper in the preferred embodiment.
• all ofthe other vias and conductive paths of carrier 21 are made of copper in the same fashion as those shown in Fig.4.
• any suitable electrically conductive material can be used. As depicted in Fig.4 and can be seen in Figs. 1 and 3 the top ends ofthe vias in struts 25 and 27 have exposed ends that appear at two ofthe top edges of platform 23 at the top of struts 25 and 27.
• the vias in struts 25 and 27 do not have to have exposed top ends such as 79A of via 77A and 79D of via 77D to provide a functioning canier, and in fact the top ends could be covered by platform 23 as an alternative design.
• constructing these vias with the exposed top ends gives carrier 21 a number of unique features that will be mentioned here briefly and explained in more detail below.
• the exposed top ends on the vias in struts 25 and 27 provide exposed contacts points with which to test the internal circuitry of carrier 21 and IC chips 51 and 52 when they are all connected to a printed circuit board. Exposed top ends of the vias also provide an avenue for dissipation of heat.
• the exposed top ends provide pads for placing one or more carriers similar to canier 21 on top of each other to form a multi-stacked, three-dimensional array of carriers and IC chips. Also, extending vias 73A, 73B, 73C and 73D from the BGA pads on platform 23 down to the bottom of platform 23 adds additional heat dissipation capability to carrier 21. Another option is to leave the tops ofthe vias in the struts exposed during installation and testing and to cover them after this is completed. Additionally, the given the fact that in a preferred embodiment the carrier is fabricated in layered fashion similar to a circuit board the vias can also be blind or buried as well as through vias.
• the vias 73 of BGA pads 29A and 29B are placed directly under the pads ofthe BGA array on the top of platform 23. This is a unique way of placing vias since it has been customaiy to offset the vias from the pads as depicted in Fig. 5A a top view showing one BGA pad 81 and top end of a via 83 and the connecting conductive link 84.
• pad 81 is offset from pad 83 is the fact that it has a hollow center core 86.
• Hollow center core 86 is a result ofthe fact that copper 82, or some other conductive material, is applied by a plating process that typically leaves a hollow core.
• FIG. 5B is a cross sectional view of via 83 along v-v of Fig. 5A.
• Fig. 5B shows hollow core 86 in via 85 with copper lining 83.
• vias which descend through one or more layers of a circuit board are cut by a small mechanical drill bit, a laser drilling appliance, or some other device, that can achieve a similar result.
• the via is bored, it is plated with a conductive material, typically copper.
• the pads could be offset from the vias as depicted in Figs.5 A and 5B without departing from the spirit of the present invention.
• these techniques as noted have their drawbacks.
• the present invention in a preferred embodiment, provides a solid core via without a hollow shaft or core 86.
• One version is depicted in fig. 5C.
• Fig. 5C shows via 87 and BGA pad 89 configuration according to one alternative embodiment ofthe present invention.
• the via 88 in fig. 5C could be fabricated by a layering of copper 88 or other conductive material 87 as the layers ofthe carrier are formed in to form via 88 channel.
• placing ofthe downwardly descending vias directly under the pads on top ofthe carrier reduces the space needed for the carrier and related circuitry.
• the present invention provides, is the filling ofthe hollow core left in the via after the application of the conductive material with a non-conductive, or conductive material.
• 5D shows the hollow core 86, after it is filled with a conducting, or non-conducting material 91 ,thus via 90 is filled solidly with the conductive material 92 and material 91 applied to fill hollow core 86.
• pad 93 can be applied to the top of via 90.
• the vias in carrier 21 and those in the struts 25 and 27 can be fabricated in the same fashion.
• Fig. 6 a diagram of a lower routing layer ofthe carrier, provides a schematic diagram of an example of how the circuitry can be configured for a carrier made according to a preferred embodiment of the present invention.
• the vias 73 of the BGA array of carrier 21 connect by conduction paths 75 to specific vias 77 in the struts.
• the cross sectional view of Fig.4 would be along line I - 1 as noted in Fig. 6.
• vias 77 ofthe struts in the preferred embodiment are arranged in a staggered a ⁇ ay to optimize space along the edges of canier 21.
• Connections 93 for the decoupling capacitor pads can also be seen in Fig.6.
• the pattern of the array of pads on the top platform can be easily configured to accommodate a wide variety of currently manufacture IC chip packages with little or no changes in the structure ofthe carrier.
• the internal circuitry of carrier 21 can be configured to accommodate a wide variety IC chip and provide an appropriate connection ofthe IC chip to the circuit board.
• the carrier ofthe present invention is fabricated in the same fashion as the standard printed circuit board. In its preferred embodiment the carrier would have from two to four or more layers.
• Figs. 7 A, 7B, 7C and 7D provide a schematic view of the various layers that could make up the top platform ofthe carrier.
• Fig. 7 A depicts the bottom layer that contains electrically conductive paths 75.
• Fig. 7B depicts the internal ground layer
• Fig. 7C depicts the internal power layer
• Fig. 7D depicts the top layer with the arrangement of pads to which an IC chip would be connected.
• Figs. 7B and 7C are negative views ofthe layer depicted while Figs.7A and 7D are the positive views.
• the exposed ends 79 ofthe vias and the pads 73 ofthe BGA array are electrically isolated from the surrounding to surface 67 ofthe carrier.
• the surface area 73 is an electrically conductive material such as copper.
• a small Area 67, surrounding each pad 73, but electrically isolated from pad 73 provide a ground areas adjacent to each pad 73 and tops ofthe vias 79 for testing purposes, etc.
• the layers depicted in Figs. 7A, 7B, 7C and 7D are separated by prepreg layers that bond the layers together and also electrically isolate them.
• Fig. 8 A is a schematic side view ofthe sequence of layers that could make up the carrier with the layers depicted in Figs.7A to 7D.
• routing layer 101 is the bottom most layer.
• Next is prepreg layer 102 with ground layer 103 above it.
• Core layer 104 located at the center ofthe carrier, would next follow ground layer 103.
• power layer 105 would be next followed by perpreg layer 106, and finally, top routing layer 107.
• chip carrier 21 out ofthe same material as the printed circuit board to which it will be attached provides a number of significant advantages. Among them are that carrier 21 will be compatible with the other items in the circuitry ofthe printed circuit board to which it will connect. Incorporation of chip carrier 21 of the present invention into the circuitry of a board during the design process will not pose a significant problem since the electrical characteristics ofthe carrier will be well known and compatible with the other elements ofthe circuitiy.
• struts 110 and 111 are made of prepreg laminate type of materials also.
• the struts are built up in layers of laminated material. Other methods are possible such as an injection molding process.
• Fig. 8B provides another cross sectional view of a strut 112 and a portion ofthe platform 113 ofthe carrier ofthe present invention.
• the layers discussed above can be seen starting with the top layer 114, which has the pattern of BGA pads, below that is first prepreg layer 115.
• the prepreg layers as is well known in the industry is a laminate material that provides insulation between the conductive layers as well as the rigidity and support necessary to form the circuit board or in this case the carrier.
• Below first prepreg layer 115 is power plane layer 116, which has on its lower side a second prepreg layer 117.
• Below the second prepreg layer 117 is ground plane 118 followed by third prepreg layer 119 below it.
• Finally at the bottom of platform 113 is lower routing layer 120.
• Layers 114, 115, 116, 117, 118, 119 and 120 thus formplatforai 113 in a preferred embodiment.
• the layers continue with the formation of strut 112 by a fourth prepreg layer 121 another intermediate layer 122, a fifth prepreg layer 123 and ending in bottom layer 124 at bottom of which are pads 125 of vias 77.
• Nias 77 as discussed above descend down through the top edge of platform 113 through strut 112 to terminate in apad 125 to which a solder ball 126 is attached for connecting the carrier to a circuit board or another carrier as will be discussed below.
• tops 79 of vias 77 in strut 112 terminate in pads 127.
• vias 77 A of strut 112 are staggered to economize on space. Strut vias that descend through the edge ofthe platform into the strut could be aligned side by side without departing from the principals ofthe present invention.
• Via 73 shown in cross section and as discussed above and depicted in other Figs, in this specification connects pad 128 ofthe array of BGA pads ofthe IC chip package to conductive line 75 that in turn connects to via 77A.
• Conductive path 75 as noted above is made of a copper trace. However, any other suitable conductive material can be used.
• vias 77 and 73 are solid copper cores that are laid down during the fabrication process of the carrier.
• the conductive cores that make up the vias terminate at the top and bottom of each strut ofthe carrier and thus provide heat dissipation channels.
• the channels in which the vias are formed could also be made by drilling a hole into the layers ofthe carrier and plating that hole with copper or other suitable conductive material.
• the carrier in a multiplayer fashion as noted provides a number of advantages it allows for impedance and matching ofthe carrier with circuit board, the carrier can be tailored to work with any standard IC chip without having to modify the chip, etc. Additionally, a stepped laminate process, depth routing or other construction method, can be used to fabricate the vias and conductive paths in the canier. Although the preferred embodiment disclosed is a fabricated in the same fashion as a circuit board with multiple layers there are may applications that do not require a canier with multiple layers.
• the carrier for a variety of applications could be fabricated by an inj ection molding process or similar process. Even with a carrier fabricated by an inj ection molding process its structure can be tailored
• Fig. 9 provides a perspective view of a corner of a carrier 130 of the present invention connected to a circuit board 131. Connected to the top of carrier is an IC chip 132 connected to carrier 130 by a BGA array. Connected to circuit board 131, underneath carrier 130, is another IC chip 133. Exposed along the top edge of carrier 130, are part of an array of exposed top ends 134 of the vias in strut 135.
• probe points 136 and 137 from one or more test devices can be placed against the exposed top ends and a variety of test conducted to determine the cause of any problems with the circuitry and devices.
• This ability to test the carrier of the present invention and the IC chips or other BGA devices connected to it and positioned underneath it while all are still connected to the printed circuit board not only makes the test results very accurate it makes it very efficient and easy to do.
• Tests using the exposed top ends 79 ofthe vias ofthe struts could be made part ofthe standard quality control tests conducted during an automated fabrication process. This could be done in a number of ways including using a clamshell type of testing device with multiple probe points that would be momentarily connected to the exposed array 134 ofthe tops ofthe vias in the struts.
• top exposed ends 79 of the upwardly extending vias are electrically isolated from the surrounding area 67 on the top of platform.
• the vias and pads ofthe BGA array 69 are also electrically isolated by material 80 from the sunounding area 67 ofthe top of platform 23.
• much of top area 67 is covered with a copper layer.
• This copper layer 67 acts as a heat sink.
• a top insulating layer 68 covers a portion of layer 67. It also provides a convenient ground contact point for testing the unit 71. For example one ofthe probes 136 or 137 in Fig. 9 and Fig.
• the structure of the canier ofthe present invention provides an additional alternative for providing an adjacent ground for testing ofthe circuits.
• One or more ofthe tops ofthe exposed vias in the strut will most likely be a ground connection. Thus, is conducting a test this exposed via can be used as the ground test and it would be not be necessary to provide a special adjacent ground location for a test point.
• FIG. 10 is an exploded view of how the chips and carriers would be stacked.
• the first BGA device 139 attaches to circuit board 140 by a standard BGA array.
• carrier 141 connects to circuit board by an array of BGA pads 142 located on either side of BGA device 139.
• BGA device 145 connects to the top of carrier 141 with BGA pad array 147.
• carrier 149 attaches to carrier 141 on by means ofthe array 150 of exposed top ends of the vias in the struts of carrier 141.
• BGA device 153 attaches to carrier 149 by means of an array of BGA pads 154 on top of carrier 149. While only two stackable carriers are illustrated in Fig. 10 a multiplicity of carriers could be stacked on each other with attached BGA devices.
• Fig. 11 provides an end of view of two tiered carriers 161 and attached BGA devices 163 on circuit board 167 that form an enlarged three-dimensional array.
• Fig. 12 provides a side view of a stacked array of carriers and BGA devices. In Fig. 12 the BGA devices underneath each ofthe carriers 161 cannot be seen due to position of struts 169 of each carrier 161.
• Carrier 201 is attached to printed circuit board 205.
• An IC chip 210 is attached to carrier 201 in the manner described above.
• IC chip 211 instead of being attached to board 205 underneath carrier is attached to the bottom surface 213 of platform 215 of carrier 201. Attaching of IC chip 211 to the bottom of carrier 201 is done with an array of BGA pads that are positioned along the bottom surface 213 of carrier 201. This arcay would be the same as that depicted above. Any number of different circuitry connections could be made to in turn connect IC chip 210 and 211 into the circuitry through carrier 201. In fact they are too numerous to mention.
• Fig. 14 provides a view of one potential circuitry arrangement of pads that might be used with memoiy IC chips given the redundancies of their circuits with carrier 201 (Fig. 13).
• top pads 220 in solid outline are located on the top ofthe platform ofthe carrier. Each pad 220 on top connects by a solid line 223 to one ofthe vias 225. As noted previously the vias descend through the platform to the bottom layer of the platform where they each connect to a line 227 shown in outline form.
• each line 227 connects to a pad 229, shown in outline form on the bottom of the carrier.
• a pad 220 on top and a pad 229 on the bottom each connect to the same via.
• the one on the bottom is offset from the one on top.
• Fig. 15 provides a cross sectional view along line II - II ofthe platform shown in Fig. 14.
• a pad on top 220A connects by line 223A to via 225A. Via 225A descends down through platform 230. Via 225A connects to line 227A. Line 227A in turn connects to pad 229A.
• One advantage ofthe version ofthe carrier depicted in Fig. 13 is that the printed circuit board can be made to a standard configuration to work with the carrier 201 depicted in Fig. 13. Thus, the only item that has to be wired to handle the IC chips are carrier 201.
• Fig. 16 provides one example of a printed circuit board 251 populated with the carriers 253 ofthe present invention.
• the IC chips that would go on top of carriers 253 have not been added yet.
• the BGA pads 255 with which IC chips will be attached to the top of each carrier 253.
• the IC chips 259 have been attached to the tops ofthe carriers 253.
• BGA pads 255 are no longer visible, since the chips 259 now cover them.
• the pads 257 at the top of each via that descends down through the platform and struts ofthe carrier are clearly visible and accessible for testing and other purposes described above and below.
• the BGA pad arrays 255 on each carrier can be configured in any number of a variety of different ways to thereby accept any type of BGA pad array an IC chip might have, be it in the arrays depicted in Fig. 16 or any other configuration such as the matrix type of array depicted in Fig. 18. Since the carrier can be easily wired in a wide variety of different ways the carrier can be designed to work with any standard IC chip package without the need to modify the IC chip package.
• the carrier ofthe present invention is truly a modular device. In fact the carriers provide a standard but flexible pin assignments for attaching IC chips to a circuit board.
• the present invention provides a unique three-dimensional assembly for BGA, CSP, flip chips or and many other types of IC chip packages.
• the invention also provides for proper capacitive decoupling. Additionally, it provides probe or test points, arrays 257 (79 in some ofthe Figs.) for signal sampling, test points for subassembly, etc. Also, it provides close proximity ground points adjacent to the probe points on the top ofthe carrier, which are available whether or not an IC chip is placed on top ofthe carrier.
• An additional advantage ofthe present invention is that it can be used in a three-dimensional single sided reflow manufacturing process.
• the first layer of IC chips can be placed on the circuit board, then the carriers placed over them as appears in Fig. 16 and finally the second set of IC chips can be placed on top of the carriers as depicted in Fig. 17.
• Standard manufacturing machinery such as standard pick and place machines can be used to place all ofthe IC chips as well as the carriers.
• the carrier can be tailored to accept any standard IC chip, this could also include those with leads as well as BGA pads, flip chips, CSP etc. Additionally, the carriers could be placed on a strip for the manufacturing process or delivered in standard JEDEC style trays.
• Fig. 18 provides a schematic diagram of the pads that would appear on top ofthe carrier 301 in one preferred embodiment.
• a matrix of pads, 303 for connecting an IC chip to.
• pads for capacitors or other type of appropriate devices are connected to the IC pad matrix 303, in an appropriate pattern.
• each pin has an appropriate designation, such as Vdd, or DQ2, or NC, etc.
• Pad DQ0 in the configuration shown in Figure 18, is connected to strut via pad 310.
• the strut pads are designated as various pins in a traditional fashion, by referring to the table in figure 19, the connections between the matrix of pads 303, and the pads on each strut, are indicated by the pin conversion table. This is just one example of the possible pad connections that can be made to allow a large variety of different types of chips, with different pad configurations that can be connected with carrier 301.
• Fig. 20 provides a schematic diagram of how decoupling capacitors 43 is electrically connected as described above.
• Capacitor 43 sits on two separate pads (Fig. 1) and each ofthe pads connect to separate vias one which connects to ground and the other which connects to power.
• decoupling capacitor 43 is placed on pad 41.
• Pad 41 is connected to via 300 that descends through strut 27 of carrier 21 a corner of which is visible in Fig. 20. Via 300 would than connect to an appropriate pad on a circuit board not shown.
• decoupling capacitor connects two pads is depicted in Fig. 1 and each pad connects by a separate via either to a power or ground connection to thereby become part ofthe electronic structure ofthe circuit.
• the present invention in another variation allows for the positioning of the decoupling capacitors 303 at a variety oflocations on carrier 301 as depicted in Fig.21.
• Electrical connection of decoupling capacitors 303 to the system can be accomplished in a variety of way.
• Fig.21A a cross-sectional view of carrier301 along line XX in Fig.20 depicts how pads 305 and 306 on which decoupling capacitors 303 sit connect by vias to internal ground 309 and power plane 310 which make up the structure of carrier 301 as described above.
• Internal power plane 310 connects to at least one via 311 in a strut and internal power plane 309 connects to one via 312 in a strut.
• connections to internal power plane 310 are electrically isolated from all of the connections to internal power plane 309.
• vias 314 and 315 descending from pads 305 and 306 on which decoupling capacitors 303 sits connect to conduction lines 317 and 318 that in turn connect directly to vias 320 and 321 in strut 325 which provide power and ground connections.
• Fig.22 provides a schematic of one version of a wiring layout on a wiring substrate layer 401 ofthe canier ofthe present invention.
• aportion ofthe Vias 403 that descend from the Pads at the top of the platform to which the IC Chip connection can be seen.
• portions ofthe Vias 405 in the Struts appear along the edge ofthe carrier.
• conducive paths 407 run between Via portions 403, and the Via portions 405.
• One ofthe important operational aspects of any computer system is providing appropriate timing of signal movement. Signals that may be off by a millisecond, or even a picosecond can often create operational problems given the speeds at which computers currently operate.
• One ofthe advantages ofthe current invention is that it allows for the arranging of memory or other types of chips in a three-dimensional fashion that allows the reduction of connecting line lengths. This is often crucial in computer architecture and significantly aids in increasing the speed of operation.
• signals have to move in a coordinated fashion and arrive at a specific end point during the clock cycle. If the lines over which signals must move in a coordinated fashion can be the same length for each signal, a significant reduction in problems which arise from coordinating signals can be achieved.
• Another advantage ofthe carriers ofthe present invention is that if several signals must move over adjacent lines at the same time, by matching line lengths on the substrate by staggering the Via locations, the lines can be made exactly the same length.
• some ofthe conductive lines 407 that run between Viaset 403 to Viaset 405 are of equal length in a number of connections.
• all conducive lines labeled 407 in fig. 22 are of the same length.
• the conducive lines running between the Via portions 403 and Via portions 405 are the same length 410.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Testing Of Individual Semiconductor Devices (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Tests Of Electronic Circuits (AREA)
• Wire Bonding (AREA)
• Measuring Leads Or Probes (AREA)
• Combinations Of Printed Boards (AREA)

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• 2003
  • 2003-02-21 KR KR1020047013372A patent/KR100980356B1/ko not_active Expired - Fee Related
  • 2003-02-21 AU AU2003216362A patent/AU2003216362A1/en not_active Abandoned
  • 2003-02-21 WO PCT/US2003/005359 patent/WO2003073506A2/en not_active Ceased
  • 2003-02-21 ES ES03742896.8T patent/ES2440770T3/es not_active Expired - Lifetime
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