Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T5/00—Image enhancement or restoration
  • G06T5/70—Denoising; Smoothing
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
  • G06V10/00—Arrangements for image or video recognition or understanding
  • G06V10/20—Image preprocessing
  • G06V10/30—Noise filtering
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
  • G06V10/00—Arrangements for image or video recognition or understanding
  • G06V10/20—Image preprocessing
  • G06V10/34—Smoothing or thinning of the pattern; Morphological operations; Skeletonisation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T2207/00—Indexing scheme for image analysis or image enhancement
  • G06T2207/10—Image acquisition modality
  • G06T2207/10016—Video; Image sequence

Definitions

• the present invention relates to the field of image display systems, and more particularly, to methods and systems for reducing contouring artifacts in image display systems.
• the present invention is directed towards detecting contouring artifacts in a received video signal and removing the detected artifacts by dithering, by adding least significant bits to selected pixels in the video signal, or by utilizing unused states.
• FIG. 1 is a block diagram of an exemplary home entertainment system configured to support the present invention
• FIG. 2 is a flowchart of a preferred contouring detection test of the present invention
• FIG. 3 is a flowchart of an alternative contouring detection test of the present invention
• FIG. 4 is a flowchart of a contouring reduction technique of the present invention
• FIG . 5 is a flowchart of an alternative contouring reduction technique of the present invention.
• FIG. 6 is a flowchart of another alternative contouring reduction technique of the present invention.
• FIG. 7 is a graph illustrating an exemplary sequence of input pixel component values
• FIG. 8 is a graphical comparison of the input pixel component values of FIG. 7 and output pixel component values generated by the contouring reduction process of FIG. 5;
• FIG. 9 is a graphical comparison of the input pixel component values of FIG. 7 and output pixel component values generated by the contouring reduction process of FIG. 4;
• FIG. 1 0 is a graph illustrating another exemplary sequence of input pixel component values
• FIG . 1 1 is a graphical comparison of the input pixel component values of FIG. 1 0 and output pixel component values generated by the contouring reduction process of FIG. 6.
• the video receiver system includes an antenna 10 and input processor 1 5 for receiving and digitizing a broadcast carrier modulated with signals carrying audio, video, and associated data, a demodulator 20 for receiving and demodulating the digital output signal from input processor 1 5, and a decoder 30 outputting a signal that is trellis decoded, mapped into byte length data segments, de- interleaved, and Reed-Solomon error corrected.
• the corrected output data from decoder unit 30 is in the form of an MPEG compatible transport data stream containing program representative multiplexed audio, video, and data components.
• the video receiver system further includes a modem 80 that may be connected, via telephone lines, to a server 83 or connection service 87 such that data in various formats (e.g., MPEG, HTML, and/or JAVA) can be received by the video receiver system over the telephone lines.
• a processor 25 processes the data output from decoder 30 and/or modem
• processor 25 includes a controller 1 1 5 that interprets requests received from remote control unit 1 25 via remote unit interface 1 20 and appropriately configures the elements of processor 25 to carry out user requests (e.g., channel, website, and/or on-screen display (OSD)) .
• controller 1 1 5 configures the elements of processor 25 to provide MPEG decoded data and an OSD for display on display unit 75.
• controller 1 1 5 configures the elements of processor 25 to provide an MPEG compatible data stream for storage on storage medium 105 via storage device 90 and store interface 95.
• controller 1 1 5 configures the elements of processor 25 for other communication modes, such as for receiving bi-directional (e.g. Internet) communications via server 83 or connection service 87.
• Processor 25 includes a decode PID selection unit 45 that identifies and routes selected packets in the transport stream from decoder 30 to transport decoder 55.
• the transport stream from decoder 30 is demultiplexed into audio, video, and data components by transport decoder 55 and is further processed by the other elements of processor 25, as described in further detail below.
• the transport stream provided to processor 25 comprises data packets containing program channel data, ancillary system timing information, and program specific information such as program content rating, program aspect ratio, and program guide information.
• Transport decoder 55 directs the ancillary information packets to controller 1 1 5 which parses, collates, and assembles the ancillary information into hierarchically arranged tables. Individual data packets comprising the user selected program channel are identified and assembled using the assembled program specific information.
• the system timing information contains a time reference indicator and associated correction data (e.g. a daylight savings time indicator and offset information adjusting for time drift, leap years, etc.) . This timing information is sufficient for a decoder to convert the time reference indicator to a time clock (e.g., United States east coast time and date) for establishing a time of day and date of the future transmission of a program by the broadcaster of the program.
• a time clock e.g., United States east coast time and date
• the time clock is useable for initiating scheduled program processing functions such as program play, program recording, and program playback.
• the program specific information contains conditional access, network information, and identification and linking data enabling the system of FIG. 1 to tune to a desired channel and assemble data packets to form complete programs.
• Transport decoder 55 provides MPEG compatible video, audio, and sub- picture streams to MPEG decoder 65.
• the video and audio streams contain compressed video and audio data representing the selected channel program content.
• the sub-picture data contains information associated with the channel program content such as rating information, program description information, and the like.
• MPEG decoder 65 cooperates with a random access memory (RAM) 67 to decode and decompress the MPEG compatible packetized audio and video data from unit 55 and provides decompressed program representative pixel data to display processor 70.
• Decoder 65 also assembles, collates and interprets the sub-picture data from unit 55 to produce formatted program guide data for output to an internal OSD module (not shown) .
• the OSD module cooperates with RAM 67 to process the sub-picture data and other information to generate pixel mapped data representing subtitling, control, and information menu displays including selectable menu options and other items for presentation on display device 75.
• the control and information menus that are displayed enable a user to select a program to view and to schedule future program processing functions including tuning to receive a selected program for viewing, recording of a program onto storage medium 1 05, and playback of a program from medium 105.
• the control and information displays including text and graphics produced by the OSD module (not shown), are generated in the form of overlay pixel map data under direction of controller 1 1 5.
• the overlay pixel map data from the OSD module is combined and synchronized with the decompressed pixel representative data from MPEG decoder 65 under direction of controller 1 1 5.
• Combined pixel map data representing a video program on the selected channel together with associated sub-picture data is encoded by display processor 70 and output to device 75 for display.
• FIGS. 2-6 illustrate the contouring detection and reduction processes of the present invention.
• the processes of the present invention are preferably applied to the component values (e.g., red (R), green (G), and blue (B) component values) of a predetermined span (e.g., a single dimension horizontal and/or vertical pixel span, a multidimensional pixel span such as a two dimensional square pixel span or a circular pixel span, or any other pixel span known by those skilled in the art) of pixels, on a pixel-by-pixel basis, and may be implemented in whole or in part within the programmed instructions of display processor 70 (shown in FIG. 1 ).
• the processes of the present invention may be implemented in hardware in contouring detection and reduction circuitry (not shown) .
• display processor 70 identifies a predetermined span of pixel component values (e.g., an 8 pixel span). After the predetermined pixel span is identified display processor 70, at step 210, determines the maximum and minimum pixel component values in the predetermined pixel span. Next, at step 215, display processor 70 determines if the maximum component value minus the minimum component value is less than a predetermined threshold value "N.” The value selected for "N" is dependent on the contouring that is being guarded against and/or is anticipated as being present in a received video signal.
• processor 70 determines whether the maximum component value minus the minimum component value is less than the predetermined threshold value "N" processor 70, at step 225, replaces the center (or near center) pixel value in accordance with the contouring reduction process of FIG. 4, FIG. 5 or FIG. 6, as discussed in further detail below.
• FIG. 3 an alternative contouring detection process 300 of the present invention is shown.
• display processor 70 identifies a predetermined span of pixel component values (e.g., an 8 pixel span). Afterwards, at step 310, processor 70 calculates a running pixel component value sum over the predetermined pixel span.
• processor 70 multiplies the pixel component value at or near the center (e.g., the 4 th pixel component value) of the predetermined pixel span (e.g., 8 pixels) by the total number of pixel component values (e.g., 8) in the pixel span.
• Processor 70 calculates the absolute value of the difference between the multiplied pixel component value and the pixel component value sum.
• processor 70 determines if the absolute value of the calculated difference is within a predetermined range. One exemplary range is if the absolute value of the calculated difference is greater than 3 and less than 9. If not, processor 70, at step 330, does not alter the center pixel value. If so, processor 70, at step 335, replaces the center (or near center) pixel value in accordance with the contouring reduction process of FIG. 4, FIG. 5 or FIG. 6, as discussed in further detail below.
• processor 70 After it has been determined that the magnitude difference test of FIG. 2 or the averaging test of FIG. 3 has been passed, processor 70, at step 405, initiates the execution of the contouring reduction process 400. Initially, at step 410, processor 70 calculates the average pixel component value of the predetermined pixel span. Next, at step 41 5, processor 70 reduces (e.g., rounds or truncates) the average pixel component value to a predetermined bit width (i.e., the original bit width of the pixel component values plus an additional number of least significant bits (LSBs)).
• LSBs least significant bits
• processor 70 at step 420, replaces the center or near-center pixel component value (e.g., the 4 th pixel value of an 8 pixel span) with the reduced average value.
• Processor 70 at step 425, then tests the next pixel component value in accordance with contouring detection process 200 (shown in FIG. 2) and/or contouring detection process 300 (shown in FIG. 3).
• contouring detection process 200 shown in FIG. 2
• contouring detection process 300 shown in FIG. 3
• FIG. 9 A graphical comparison of an exemplary sequence of input pixel component values (shown in FIG 7) and a sequence of output pixel component values generated by contouring reduction process 400 is shown in FIG. 9 wherein a single LSB has been added.
• FIG. 5 an alternative contouring reduction process 500 of the present invention is shown. After it has been determined that the magnitude difference test of FIG.
• processor 70 at step 505, initiates the execution of the contouring reduction process 500.
• processor 70 calculates the average pixel component value of the predetermined pixel span.
• processor 70 reduces (e.g., rounds or truncates) the average value to the nearest integer to generate a new pixel component value.
• processor 70 replaces the center or near-center pixel component value (e.g., the 4 th pixel value of an 8 pixel span) with the reduced average pixel component value.
• Processor 70 at step 525, then tests the next pixel component value in accordance with contouring detection process 200 (shown in FIG. 2) and/or contouring detection process 300 (shown in FIG. 3).
• a graphical comparison of an exemplary sequence of input pixel component values (shown in FIG 7) and of a sequence of output pixel component values generated by contouring reduction process 500 is shown in FIG. 8.
• processor 70 After it has been determined that the magnitude difference test of FIG. 2 or the averaging test of FIG. 3 has been passed, processor 70, at step 605, initiates the execution of the contouring reduction process 600. Initially, at step 610, processor 70 calculates the average pixel component value of the predetermined pixel span. For example, if the bit width of each pixel component value in an 8-pixel span is 8 bits, the bit width of the average pixel component value will be 1 1 bits. Afterwards, at step 61 5, processor 70 adds a dither signal to the average to generate a new pixel component value.
• the dither signal may be an alternating signal such as, but not limited to, a string of alternating ones and zeroes (e.g., 1 , 0, 1 , 0, 1 , 0...) or the dithering signal could be implemented with a recursive rounding circuit, as known by those skilled in the art.
• a two state dither signal of alternating ones and zeroes can be added to the 1 1 -bit average using a 9-bit adder. To do so the 1 1 -bit average is truncated to a 9-bit average by discarding the two LSBs of the 1 1 -bit average and then adding the two state dither signal (via the 9 bit adder) to the least significant bit of the 9-bit average.
• the two state dither signal can be added to the 1 1 -bit average using an 1 1 -bit adder. To do so the two state dither signal is added (via the 1 1 -bit adder) to the 3 rd LSB of the 1 1 -bit average.
• processor 70 truncates the dithered pixel component value to the desired bit width (e.g., the original bit width of the pixel component values). For example, the 9 bit dithered average is truncated to an 8 bit dithered average by removing the LSB or the 1 1 bit dithered signal is truncated to an 8 bit dithered average by removing the three LSBs.
• processor 70 replaces the center or near-center pixel component value (e.g., the 4 th pixel value of the 8 pixel span) with the truncated pixel component value.
• Processor 70 tests the next pixel component value in accordance with contouring detection process 200 (shown in FIG. 2) and/or contouring detection process 300 (shown in FIG. 3).
• contouring detection process 200 shown in FIG. 2
• contouring detection process 300 shown in FIG. 3
• FIG. 1 1 A graphical comparison of an exemplary sequence of input pixel component values (shown in FIG. 10) and of a sequence of output pixel component values generated by contouring reduction process 600 is shown in FIG. 1 1 .

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Multimedia (AREA)
• Image Processing (AREA)
• Controls And Circuits For Display Device (AREA)
• Facsimile Image Signal Circuits (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Image Analysis (AREA)
• Liquid Crystal Display Device Control (AREA)
• Picture Signal Circuits (AREA)

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• 2002
  • 2002-01-25 US US10/056,595 patent/US6647152B2/en not_active Expired - Lifetime
• 2003
  • 2003-01-17 BR BR0307078-6A patent/BR0307078A/pt not_active Application Discontinuation
  • 2003-01-17 JP JP2003564810A patent/JP4740539B2/ja not_active Expired - Fee Related
  • 2003-01-17 EP EP03703878.3A patent/EP1468397A4/en not_active Withdrawn
  • 2003-01-17 WO PCT/US2003/001525 patent/WO2003065293A1/en not_active Ceased
  • 2003-01-17 MX MXPA04007139A patent/MXPA04007139A/es active IP Right Grant
  • 2003-01-17 KR KR1020047011454A patent/KR101000718B1/ko not_active Expired - Fee Related
  • 2003-01-17 CN CNB038026538A patent/CN1307592C/zh not_active Expired - Fee Related
  • 2003-01-17 TW TW092101006A patent/TW591936B/zh not_active IP Right Cessation
  • 2003-01-17 KR KR1020107016890A patent/KR20100089906A/ko not_active Ceased
  • 2003-01-24 MY MYPI20030243A patent/MY134337A/en unknown

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