WO2003058704A1 - Verfahren zum herstellen eines schutzes für chipkanten und anordnung zum schutz von chipkanten - Google Patents
Verfahren zum herstellen eines schutzes für chipkanten und anordnung zum schutz von chipkanten Download PDFInfo
- Publication number
- WO2003058704A1 WO2003058704A1 PCT/DE2003/000012 DE0300012W WO03058704A1 WO 2003058704 A1 WO2003058704 A1 WO 2003058704A1 DE 0300012 W DE0300012 W DE 0300012W WO 03058704 A1 WO03058704 A1 WO 03058704A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- encapsulant material
- substrate
- chip
- semiconductor chip
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- the invention relates to a method for producing protection for chip edges in case-less electronic components in which semiconductor chips provided with a laterally open bond channel are mounted on a substrate with the interposition of a tape.
- the invention further relates to an arrangement for protecting chip edges.
- unprotected chip edges are extremely sensitive to mechanical loads, e.g. against bumps.
- the result of the resulting damage is high failure rates in handling.
- a thermo-mechanical mismatch of the materials used for the electronic components can often lead to mechanical stress at the chip edges or their corners and damage.
- Unprotected fuses, including electrical fuses for switching on redundancies are also very sensitive to environmental influences such as moisture and ions and can therefore corrode very easily.
- thermomechanical see tensions can not be effectively eliminated with the described methods.
- thermomechanical stress Another possibility for reducing thermomechanical stress is shown, for example, in US Pat. No. 5,293,067.
- a chip carrier for integrated circuits in which a semiconductor chip is electrically and mechanically connected to a substrate via bumps (solder balls) and contact islands (pads).
- an organic connecting agent such as an epoxy resin or silicone.
- This underfiller is also intended to reduce mechanical stress (stress) between the semiconductor chip and the substrate.
- the underfiller also has the function of protecting the active areas and the electrical connections against environmental influences.
- the underfiller can fill the entire space between the components or, if appropriate, only the area of the active surface of the semiconductor chip. Effective edge protection of the semiconductor chip is, however, not possible with this arrangement.
- the invention is therefore based on the object of creating an easy-to-implement method and an arrangement for reliably protecting the chip edges / corners.
- the object on which the invention is based was achieved in a method of the type mentioned at the outset in that a tape is used for mounting the semiconductor chip on the substrate, the outline of which is smaller than the outline of the semiconductor chip, so that it runs between the semiconductor chip and the substrate a circumferential shelter is formed as a capillary that after the electrical connections have been made between the semiconductor chip and the carrier element (wire bonding), a flowable encapsulant material is introduced into the bond channel in a first step until the encapsulant material reaches the edge of the semiconductor chip uniformly encloses and that the bond channel is then completely filled with encapsulant material in a second step.
- the filling of the bond channel with the encapsulant material is preferably continued until a uniform material throat has formed around the semiconductor chip.
- the encapsulant material is briefly annealed after the first step, as a result of which an excessive amount of material is prevented from escaping and the subsequent assembly step is prepared.
- a further embodiment of the invention provides that a material that shrinks during hardening is used as the encapsulant material. This ensures extremely effective edge protection.
- An epoxy / silicone mixture is preferably used as the encapsulant material, which can be introduced easily into the bond channel and which has good flow properties.
- the encapsulant material is introduced into the bond channel by printing or dispensing. This allows the receipt channel to be filled quickly and effectively, the amount of the encapsulant material introduced in the first step being specified depending on the component.
- the object of the invention is further achieved by an arrangement for protecting chip edges in electronic components, in which semiconductor chips provided with a laterally open bond channel are mounted on a substrate with the interposition of a tape and which is characterized in that in the region of the outer periphery of the semiconductor chip there is an intermediate space in the form of a capillary between the latter and the substrate, which is filled with an encapsulant material and that a material fillet made of the encapsulant material extends around the semiconductor chip and envelops at least its lower chip edge.
- the material throat consisting of the encapsulant material preferably has an angle of approximately 45 ° with respect to the substrate.
- the encapsulant material consists of an epoxy / silicone mixture with shrinkage properties, the encapsulant material being formed in one piece in the intermediate space and in the material throat.
- the process control and the associated design result in a material fillet of approximately 45 ° made of a soft encapsulant material that fulfills several tasks.
- it protects active chip edges from mechanical ones Damage from the outside and reduces the mechanical stress on the cip edges. Due to the material properties of the material used, a tensile load is converted into a compressive load on the active chip edge. This occurs through the chemical shrinking process of the material used during curing. Chip edges are known less sensitive to pressure loads than tensile loads Another effect is the covering of fuses and thus the prevention of environmental influences on the fuses.
- the method according to the invention can in principle be used in all electronic components in which there is or can be an intermediate space in the form of a capillary between the semiconductor chip and the substrate on which the semiconductor chip is mounted, which can be filled via a bond channel ,
- Chipsize packages can be easily implemented using BOC technology.
- FIG. 1 shows a top view of an arrangement for protecting chip edges produced using the method according to the invention
- Fig. 2 is a sectional view of Figure 1, section 1.
- Fig. 3 is a sectional view of Figure 1, section 2.
- FIG. 4 is a sectional view of FIG. 1, section 3.
- the semiconductor chip 2 provided with a laterally open central bonding channel 1 is mounted on a substrate 4 with the interposition of a tape 3.
- the substrate 4 is provided with interconnects, not shown, which are usually connected to the semiconductor chip 2 via wire bridges and are provided on the underside of the substrate 4 with solder balls 5, with which an electrical connection of the electronic component to printed circuit boards or the like , can be manufactured.
- an intermediate space 6 in the form of a capillary between the latter and the substrate 4, which is filled with an encapsulant material 7.
- a material fillet 8 made of the encapsulant material 7 extends around the semiconductor chip 2. This material fillet 8 envelops the lower chip edge 9 and forms an angle of approximately 45 ° with respect to the substrate 4.
- This material fillet 8 can also be designed so that it also includes the upper chip edge.
- the material fillet 8 is produced in that after the electrical connections between the semiconductor chip and the substrate 4 have been made by wire bonding, a flowable encapsulant material 7 is provided in the first step Bond channel 1 is introduced until it surrounds the lower edge 9 of the semiconductor chip 2 evenly.
- the filling of the bonding channel 1 with the encapsulant material 7 is preferably continued until a uniform material fillet 8 has formed around the semiconductor chip 2.
- the introduced encapsulant material 7 is then briefly annealed, which prevents an excessive amount of material from escaping and the subsequent assembly step is prepared.
- the encapsulant material 7 is completely hardened after the first step, which can be achieved by a longer tempering step.
- the bond channel 1 is completely filled with encapsulant material 7, so that all the wire bridges that extend through the bond channel are also encased.
- a material that shrinks during hardening e.g. an epoxy / silicone mixture is used, which has good flow properties.
- the encapsulant material 7 can be introduced into the bonding channel 1 by printing or dispensing, as a result of which the receipt channel 1 can be filled quickly and effectively, the amount of the encapsulant material 7 introduced in the first step also being able to be predetermined depending on the component.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03702311A EP1444728A1 (de) | 2002-01-14 | 2003-01-07 | Verfahren zum herstellen eines schutzes für chipkanten und anordnung zum schutz von chipkanten |
US10/890,827 US7229857B2 (en) | 2002-01-14 | 2004-07-14 | Method for producing a protection for chip edges and system for the protection of chip edges |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10201204A DE10201204A1 (de) | 2002-01-14 | 2002-01-14 | Verfahren zum Herstellen eines Schutzes für Chipkanten und Anordnung zum Schutz von Chipkanten |
DE10201204.0 | 2002-01-14 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/890,827 Continuation US7229857B2 (en) | 2002-01-14 | 2004-07-14 | Method for producing a protection for chip edges and system for the protection of chip edges |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003058704A1 true WO2003058704A1 (de) | 2003-07-17 |
Family
ID=7712134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2003/000012 WO2003058704A1 (de) | 2002-01-14 | 2003-01-07 | Verfahren zum herstellen eines schutzes für chipkanten und anordnung zum schutz von chipkanten |
Country Status (5)
Country | Link |
---|---|
US (1) | US7229857B2 (de) |
EP (1) | EP1444728A1 (de) |
DE (1) | DE10201204A1 (de) |
TW (1) | TW591727B (de) |
WO (1) | WO2003058704A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7229857B2 (en) * | 2002-01-14 | 2007-06-12 | Infineon Technologies Ag | Method for producing a protection for chip edges and system for the protection of chip edges |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005015036B4 (de) | 2004-07-19 | 2008-08-28 | Qimonda Ag | Verfahren zur Montage eines Chips auf einer Unterlage |
US7265441B2 (en) | 2005-08-15 | 2007-09-04 | Infineon Technologies Ag | Stackable single package and stacked multi-chip assembly |
US8237293B2 (en) * | 2009-11-25 | 2012-08-07 | Freescale Semiconductor, Inc. | Semiconductor package with protective tape |
WO2015049852A1 (ja) * | 2013-10-01 | 2015-04-09 | パナソニックIpマネジメント株式会社 | 半導体装置 |
CN108993835A (zh) * | 2018-07-16 | 2018-12-14 | 成都捷翼电子科技有限公司 | 一种新型段差填充方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US5920118A (en) * | 1996-12-18 | 1999-07-06 | Hyundai Electronics Industries Co., Ltd. | Chip-size package semiconductor |
US6225144B1 (en) * | 1999-03-01 | 2001-05-01 | Motorola, Inc. | Method and machine for underfilling an assembly to form a semiconductor package |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2570498B2 (ja) | 1991-05-23 | 1997-01-08 | モトローラ・インコーポレイテッド | 集積回路チップ・キャリア |
US6232152B1 (en) * | 1994-05-19 | 2001-05-15 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures |
JP2924830B2 (ja) * | 1996-11-15 | 1999-07-26 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5923067A (en) * | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
US6124546A (en) * | 1997-12-03 | 2000-09-26 | Advanced Micro Devices, Inc. | Integrated circuit chip package and method of making the same |
US6300166B1 (en) * | 1999-08-30 | 2001-10-09 | Advanced Semiconductor Engineering, Inc. | Method for packaging a BGA and the structure of a substrate for use with the method |
US6309908B1 (en) * | 1999-12-21 | 2001-10-30 | Motorola, Inc. | Package for an electronic component and a method of making it |
US6560108B2 (en) | 2000-02-16 | 2003-05-06 | Hughes Electronics Corporation | Chip scale packaging on CTE matched printed wiring boards |
MY131961A (en) * | 2000-03-06 | 2007-09-28 | Hitachi Chemical Co Ltd | Resin composition, heat-resistant resin paste and semiconductor device using them and method for manufacture thereof |
DE10201204A1 (de) * | 2002-01-14 | 2003-07-31 | Infineon Technologies Ag | Verfahren zum Herstellen eines Schutzes für Chipkanten und Anordnung zum Schutz von Chipkanten |
-
2002
- 2002-01-14 DE DE10201204A patent/DE10201204A1/de not_active Ceased
-
2003
- 2003-01-07 EP EP03702311A patent/EP1444728A1/de not_active Withdrawn
- 2003-01-07 WO PCT/DE2003/000012 patent/WO2003058704A1/de not_active Application Discontinuation
- 2003-01-14 TW TW092100708A patent/TW591727B/zh not_active IP Right Cessation
-
2004
- 2004-07-14 US US10/890,827 patent/US7229857B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
US5920118A (en) * | 1996-12-18 | 1999-07-06 | Hyundai Electronics Industries Co., Ltd. | Chip-size package semiconductor |
US6225144B1 (en) * | 1999-03-01 | 2001-05-01 | Motorola, Inc. | Method and machine for underfilling an assembly to form a semiconductor package |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7229857B2 (en) * | 2002-01-14 | 2007-06-12 | Infineon Technologies Ag | Method for producing a protection for chip edges and system for the protection of chip edges |
Also Published As
Publication number | Publication date |
---|---|
TW591727B (en) | 2004-06-11 |
US20050064630A1 (en) | 2005-03-24 |
US7229857B2 (en) | 2007-06-12 |
TW200304190A (en) | 2003-09-16 |
EP1444728A1 (de) | 2004-08-11 |
DE10201204A1 (de) | 2003-07-31 |
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