WO2003046920A3 - Verfahren zur herstellung einer speicherzelle eines speicherzellenfeldes in einem halbleiterspeicher - Google Patents

Verfahren zur herstellung einer speicherzelle eines speicherzellenfeldes in einem halbleiterspeicher Download PDF

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Publication number
WO2003046920A3
WO2003046920A3 PCT/DE2002/004287 DE0204287W WO03046920A3 WO 2003046920 A3 WO2003046920 A3 WO 2003046920A3 DE 0204287 W DE0204287 W DE 0204287W WO 03046920 A3 WO03046920 A3 WO 03046920A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
capacitor
web
memory
trenches
Prior art date
Application number
PCT/DE2002/004287
Other languages
English (en)
French (fr)
Other versions
WO2003046920A2 (de
Inventor
Dirk Manger
Original Assignee
Infineon Technologies Ag
Dirk Manger
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Dirk Manger filed Critical Infineon Technologies Ag
Priority to KR1020047007675A priority Critical patent/KR100551786B1/ko
Publication of WO2003046920A2 publication Critical patent/WO2003046920A2/de
Publication of WO2003046920A3 publication Critical patent/WO2003046920A3/de
Priority to US10/850,960 priority patent/US7005346B2/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Der Erfindung, bei der in einem Halbleitersubstrat ein Kondensator mit einer Elektrode (11) als Speicherzellenknoten und einer zweiten Elektrode (20) als gemeinsame Gegenelektrode des Speicherzellenfeldes gebildet und anschließend oberhalb des Kondensators ein Feldeffekttransistor (FET) erzeugt wird, liegt die Aufgabe zugrunde, eine Speicherzelle mit einem vertikalen Aufbau des Kondensators und einem darüber angeordneten vertikalen FET zu schaffen die mit geringerem Aufwand und technologisch sicherer zu fertigen ist. Dies wird dadurch gelöst, dass in dem Halbleitersubstrat zwei parallel verlaufende erste Gräben (10) mit einer ersten Tiefe (13) geätzt werden, zwischen denen ein Steg (11) gebildet wird, der an seinen Schmalseiten mit dem Halbleitersubstrat verbunden ist und der an seiner Unterseite durchtrennt und von dem Halbleitersubstrat getrennt wird. Der freihängende Steg (15) wird nun mit einem geschlossenen Dielektrikum (19) versehen. Nach einer Füllung wird der FET (23, 24, 25, 26) aufgebracht und mit dem Steg als Speicherknoten verbunden.
PCT/DE2002/004287 2001-11-22 2002-11-21 Verfahren zur herstellung einer speicherzelle eines speicherzellenfeldes in einem halbleiterspeicher WO2003046920A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020047007675A KR100551786B1 (ko) 2001-11-22 2002-11-21 반도체 메모리의 반도체 메모리 셀 어레이의 메모리 셀제조 방법
US10/850,960 US7005346B2 (en) 2001-11-22 2004-05-21 Method for producing a memory cell of a memory cell field in a semiconductor memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10157179A DE10157179C1 (de) 2001-11-22 2001-11-22 Verfahren zur Herstellung einer Speicherzelle eines Speicherzellenfeldes in einem Halbleiterspeicher
DE10157179.8 2001-11-22

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/850,960 Continuation US7005346B2 (en) 2001-11-22 2004-05-21 Method for producing a memory cell of a memory cell field in a semiconductor memory

Publications (2)

Publication Number Publication Date
WO2003046920A2 WO2003046920A2 (de) 2003-06-05
WO2003046920A3 true WO2003046920A3 (de) 2003-08-14

Family

ID=7706498

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/004287 WO2003046920A2 (de) 2001-11-22 2002-11-21 Verfahren zur herstellung einer speicherzelle eines speicherzellenfeldes in einem halbleiterspeicher

Country Status (5)

Country Link
US (1) US7005346B2 (de)
KR (1) KR100551786B1 (de)
DE (1) DE10157179C1 (de)
TW (1) TW569399B (de)
WO (1) WO2003046920A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627478B1 (en) 2015-12-10 2017-04-18 International Business Machines Corporation Integrated vertical nanowire memory
US9812443B1 (en) 2017-01-13 2017-11-07 International Business Machines Corporation Forming vertical transistors and metal-insulator-metal capacitors on the same chip
KR200494019Y1 (ko) 2019-05-02 2021-07-16 하이윈 테크놀로지스 코포레이션 볼 스플라인 장치
CN117042451B (zh) * 2023-10-08 2024-02-02 芯盟科技有限公司 半导体结构及其形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010000918A1 (en) * 1997-10-06 2001-05-10 Leonard Forbes Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US20010001722A1 (en) * 1997-10-06 2001-05-24 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420842B1 (en) 2000-01-11 2002-07-16 American Superconductor Corporation Exciter and electronic regulator for rotating machinery
US6503813B1 (en) * 2000-06-16 2003-01-07 International Business Machines Corporation Method and structure for forming a trench in a semiconductor substrate
DE10111760B4 (de) * 2001-03-12 2004-08-12 Infineon Technologies Ag Verfahren zur Herstellung von mindestens zwei Speicherzellen eines Halbleiterspeichers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010000918A1 (en) * 1997-10-06 2001-05-10 Leonard Forbes Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US20010001722A1 (en) * 1997-10-06 2001-05-24 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Also Published As

Publication number Publication date
US7005346B2 (en) 2006-02-28
TW569399B (en) 2004-01-01
KR100551786B1 (ko) 2006-02-13
KR20040063154A (ko) 2004-07-12
TW200303074A (en) 2003-08-16
DE10157179C1 (de) 2003-01-30
WO2003046920A2 (de) 2003-06-05
US20050032309A1 (en) 2005-02-10

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