WO2004064123A3 - Verfahren zur herstellung eines halbleiterbauelements - Google Patents

Verfahren zur herstellung eines halbleiterbauelements Download PDF

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Publication number
WO2004064123A3
WO2004064123A3 PCT/DE2003/004286 DE0304286W WO2004064123A3 WO 2004064123 A3 WO2004064123 A3 WO 2004064123A3 DE 0304286 W DE0304286 W DE 0304286W WO 2004064123 A3 WO2004064123 A3 WO 2004064123A3
Authority
WO
WIPO (PCT)
Prior art keywords
insulation
trench
component
production
semiconductor component
Prior art date
Application number
PCT/DE2003/004286
Other languages
English (en)
French (fr)
Other versions
WO2004064123A2 (de
Inventor
Platen Klaus Kohlmann-Von
Helmut Bernt
Detlef Friedrich
Original Assignee
Fraunhofer Ges Forschung
Platen Klaus Kohlmann-Von
Helmut Bernt
Detlef Friedrich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Ges Forschung, Platen Klaus Kohlmann-Von, Helmut Bernt, Detlef Friedrich filed Critical Fraunhofer Ges Forschung
Priority to US10/541,819 priority Critical patent/US7719077B2/en
Priority to JP2004565915A priority patent/JP4718187B2/ja
Priority to CA2511842A priority patent/CA2511842C/en
Priority to EP03799455A priority patent/EP1581966A2/de
Priority to AU2003299284A priority patent/AU2003299284A1/en
Publication of WO2004064123A2 publication Critical patent/WO2004064123A2/de
Publication of WO2004064123A3 publication Critical patent/WO2004064123A3/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Beschrieben wird ein Verfahren zur Herstellung eines Halbleiterbauelements, das wenigstens ein erstes vertikales Leistungsbauelement (5, 9) sowie wenigstens ein laterales, aktives Bauelement (6) und/oder zumindest ein zweites vertikales Leistungsbauelement (10) aufweist, zwischen denen wenigstens ein mit einer Isolierung (4) gefüllter Graben (2) angeordnet ist, sowie ein mit dem Verfahren hergestelltes Halbleiterbauelement. Das Halbleiterbauelement zeichnet sich im Wesent­lichen durch eine ex- oder konzentrische Anordnung der jeweiligen Funktionselemente (5, 6, 9, 10), die jeweils durch eine Trenchisolation voneinander getrennt sind, aus. Zur Herstellung eines solchen Halbleiterbauelementes wird in die Vorderseite eines Silizium Substrates (1) zumindest ein Graben (2) geätzt, der wenigstens eine Teilfläche der Vorderseite vollumfänglich umschließt und der anschließend mit einer Isolation (4) aufgefüllt wird. Im weiteren Verlauf des Verfahrens wird das Silizium-Substrat (1) von der Rückseite her bis an die Isolierung (4), also bis an die Unterseite der Isolation, ganzflächig gedünnt. Die Kontaktierung der Leistungsbauelemente (5, 9, 10) erfolgt von der Rückseite her.
PCT/DE2003/004286 2003-01-10 2003-12-23 Verfahren zur herstellung eines halbleiterbauelements WO2004064123A2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/541,819 US7719077B2 (en) 2003-01-10 2003-12-23 Method for the production of a semiconductor component
JP2004565915A JP4718187B2 (ja) 2003-01-10 2003-12-23 半導体部品及びその製造方法
CA2511842A CA2511842C (en) 2003-01-10 2003-12-23 Method for the production of a semiconductor component
EP03799455A EP1581966A2 (de) 2003-01-10 2003-12-23 Verfahren zur herstellung eines halbleiterbauelements
AU2003299284A AU2003299284A1 (en) 2003-01-10 2003-12-23 Method for the production of a semiconductor component

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10300577A DE10300577B4 (de) 2003-01-10 2003-01-10 Halbleiterbauelement mit vertikalem Leistungsbauelement aufweisend einen Trenngraben und Verfahren zu dessen Herstellung
DE10300577.3 2003-01-10

Publications (2)

Publication Number Publication Date
WO2004064123A2 WO2004064123A2 (de) 2004-07-29
WO2004064123A3 true WO2004064123A3 (de) 2004-09-10

Family

ID=32519783

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/004286 WO2004064123A2 (de) 2003-01-10 2003-12-23 Verfahren zur herstellung eines halbleiterbauelements

Country Status (7)

Country Link
US (1) US7719077B2 (de)
EP (1) EP1581966A2 (de)
JP (1) JP4718187B2 (de)
AU (1) AU2003299284A1 (de)
CA (1) CA2511842C (de)
DE (1) DE10300577B4 (de)
WO (1) WO2004064123A2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007317839A (ja) * 2006-05-25 2007-12-06 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP5217348B2 (ja) * 2006-12-06 2013-06-19 株式会社デンソー 半導体装置
CN101842736A (zh) * 2007-08-08 2010-09-22 新加坡科技研究局 电光设备及其制备方法
EP2031653B1 (de) * 2007-08-27 2014-03-05 Denso Corporation Herstellungsverfahren für ein Halbleiterbbauelement mit mehreren Elementbildungsbereichen
JP4678547B2 (ja) * 2007-11-06 2011-04-27 株式会社デンソー 半導体装置及びその製造方法
US7911023B2 (en) * 2007-11-06 2011-03-22 Denso Corporation Semiconductor apparatus including a double-sided electrode element and method for manufacturing the same
JP4577425B2 (ja) * 2007-11-07 2010-11-10 株式会社デンソー 半導体装置
US8125002B2 (en) * 2007-11-07 2012-02-28 Denso Corporation Semiconductor device and inverter circuit having the same
US8278731B2 (en) * 2007-11-20 2012-10-02 Denso Corporation Semiconductor device having SOI substrate and method for manufacturing the same
JP4737255B2 (ja) * 2007-11-20 2011-07-27 株式会社デンソー Ｓｏｉ基板を用いた半導体装置
JP5444648B2 (ja) * 2008-07-03 2014-03-19 富士電機株式会社 半導体装置の製造方法
US7989282B2 (en) * 2009-03-26 2011-08-02 International Business Machines Corporation Structure and method for latchup improvement using through wafer via latchup guard ring
US20110260245A1 (en) * 2010-04-23 2011-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device
US9142665B2 (en) 2010-12-10 2015-09-22 Infineon Technologies Austria Ag Semiconductor component with a semiconductor via
US9396997B2 (en) * 2010-12-10 2016-07-19 Infineon Technologies Ag Method for producing a semiconductor component with insulated semiconductor mesas
EP2887387A1 (de) * 2013-12-20 2015-06-24 Nxp B.V. Halbleitervorrichtung und zugehöriges Verfahren
US10546816B2 (en) * 2015-12-10 2020-01-28 Nexperia B.V. Semiconductor substrate with electrically isolating dielectric partition
JP6795032B2 (ja) * 2016-06-03 2020-12-02 富士電機株式会社 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0328331A2 (de) * 1988-02-08 1989-08-16 Kabushiki Kaisha Toshiba Halbleiteranordnung und Verfahren zu dessen Herstellung
US5356827A (en) * 1992-03-19 1994-10-18 Nec Corporation Method of manufacturing semiconductor device
US5909626A (en) * 1997-03-28 1999-06-01 Nec Corporation SOI substrate and fabrication process therefor
US6229179B1 (en) * 1998-10-29 2001-05-08 Fairchild Korea Semiconductor Ltd. Intelligent power integrated circuit
EP1267414A2 (de) * 1994-02-24 2002-12-18 Mitsubishi Denki Kabushiki Kaisha Thyristor und Verfahren zur Herstellung

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860081A (en) * 1984-06-28 1989-08-22 Gte Laboratories Incorporated Semiconductor integrated circuit structure with insulative partitions
US5294825A (en) * 1987-02-26 1994-03-15 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device
US5512774A (en) * 1988-02-08 1996-04-30 Kabushiki Kaisha Toshiba Dielectrically isolated substrate and semiconductor device using the same
DE4201910C2 (de) * 1991-11-29 1995-05-11 Fraunhofer Ges Forschung Verfahren zum Herstellen einer Halbleiterstruktur für eine integrierte Leistungsschaltung mit einem vertikalen Leistungsbauelement
US5981983A (en) * 1996-09-18 1999-11-09 Kabushiki Kaisha Toshiba High voltage semiconductor device
KR100218538B1 (ko) * 1996-10-17 1999-09-01 김덕중 반도체 기판 및 그 제조 방법
US6150697A (en) * 1998-04-30 2000-11-21 Denso Corporation Semiconductor apparatus having high withstand voltage
EP1071133B1 (de) * 1999-07-21 2010-04-21 STMicroelectronics Srl Verfahren zum Herstellen von CMOS Transistoren nichtflüchtiger Speicher und von vertikalen Bipolartransistoren mit hohem Verstärkungsfaktor
JP4631113B2 (ja) * 1999-10-26 2011-02-16 株式会社デンソー 半導体装置の製造方法
US6524890B2 (en) * 1999-11-17 2003-02-25 Denso Corporation Method for manufacturing semiconductor device having element isolation structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0328331A2 (de) * 1988-02-08 1989-08-16 Kabushiki Kaisha Toshiba Halbleiteranordnung und Verfahren zu dessen Herstellung
US5356827A (en) * 1992-03-19 1994-10-18 Nec Corporation Method of manufacturing semiconductor device
EP1267414A2 (de) * 1994-02-24 2002-12-18 Mitsubishi Denki Kabushiki Kaisha Thyristor und Verfahren zur Herstellung
US5909626A (en) * 1997-03-28 1999-06-01 Nec Corporation SOI substrate and fabrication process therefor
US6229179B1 (en) * 1998-10-29 2001-05-08 Fairchild Korea Semiconductor Ltd. Intelligent power integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YU OHATE ET AL: "DIELECTRICALLY ISOLATED INTELLIGENT POWER SWITCH", PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE. PORTLAND, MAY 4 - 7, 1987, NEW YORK, IEEE, US, vol. CONF. 9, 4 May 1987 (1987-05-04), pages 443 - 446, XP000011869 *

Also Published As

Publication number Publication date
WO2004064123A2 (de) 2004-07-29
CA2511842A1 (en) 2004-07-29
JP2006513563A (ja) 2006-04-20
AU2003299284A1 (en) 2004-08-10
US7719077B2 (en) 2010-05-18
CA2511842C (en) 2014-02-04
AU2003299284A8 (en) 2004-08-10
DE10300577A1 (de) 2004-07-22
EP1581966A2 (de) 2005-10-05
DE10300577B4 (de) 2012-01-26
US20060172494A1 (en) 2006-08-03
JP4718187B2 (ja) 2011-07-06

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