Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66234—Bipolar junction transistors [BJT]
  • H01L29/6625—Lateral transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8248—Combination of bipolar and field-effect technology
  • H01L21/8249—Bipolar and MOS technology
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
  • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
  • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/73—Bipolar junction transistors
  • H01L29/735—Lateral transistors

Definitions

• the present invention generally relates to the field of silicon IC-technology, and more specifically the invention relates to a lateral pnp transistor device, to an integrated circuit including the transistor device, and to fabrication of a lateral pnp transistor device in a semiconductor process flow, especially designed for bipolar F-IC:s.
• CMOS complementary metal-oxide-semiconductor
• BiCMOS Bipolar complementary metal-oxide-semiconductor
• BiCMOS complementary metal-oxide-semiconductor
• a common trend in microelectronics is to integrate more and more functions on a single chip, in order to increase the general performance and to reduce size, power consumption and price of the circuits.
• the versatility of a BiCMOS process is many time preferred, although it is not suited for all applications.
• High- performance bipolar integrated circuits have been used extensively for some critical building blocks in telecommunication circuits, mainly for analog functions such as switching currents and voltages, and for high-frequency radio circuit functions such as those in mixers, amplifiers, and detectors .
• a bipolar-only process is many times still to prefer, instead of a BiCMOS process.
• n-type devices i.e. npn- transistors
• p-type devices i.e. pnp- transistors
• a bipolar-only RF-IC process usually lacks good pnp-transistors, since the process is commonly designed for optimal vertical npn- transistor performance.
• High-performance vertical pnp- transistors can be added to the process flow, but to a cost of increased processing complexity and number of mask layers, see e.g. M.C. Wilson et al., "Process HJ: A 30 GHz NPN and 20 GHz PNP Complimentary Bipolar Process for High Linearity RF Circuits", Proc. IEEE BCTM Conf. 1998, p. 164.
• lateral pnp transistors are usually employed as p- devices, since the requirement can be very relaxed in terms of high-frequency properties, current drive ability, packing density etc.
• the lateral pnp transistor is commonly made by placing two p- type diffusions in close proximity to each other in the epi- layer, one of them, the collector, surrounding the other one, the emitter.
• the base will consist of the n-well, with the subcollector used as base contact.
• the collector and emitter regions are separated by field oxide.
• a typical example of a lateral pnp device in a BiCMOS process is described in US 5,953,600 by Gris.
• a lateral pnp transistor by using MOS transistors is usually layouted in a circular manner. In the center of the layout is the emitter ( source) , surrounded by the gate. The MOS gate is connected to the emitter (source), to assure that the channel of the MOS device is always in accumulation.
• a primary problem with the lateral pnp devices made by using MOS transistors is the low gain (beta), which typically is lower than 10. Another problem is the comparatively large area occupied by each device . An optimized structure is therefore needed.
• a lateral pnp transistor device which comprises a PMOS transistor structure including an n-type doped region or well formed in a p-type doped semiconductor substrate consisting of a bulk material optionally with one or several epitaxial layers; a gate region formed on the n-type doped region; p-type doped source and drain regions formed in the n- type doped region; and a buried n + -type doped region located underneath the n-type doped region.
• the buried n + -type doped region is connected to the upper surface of the substrate by means of a diffused n + -type doped contact.
• the source and gate regions are interconnected; the source constitutes an emitter of the pnp transistor device; the drain region constitutes a collector of the pnp transistor device; and the n-type doped region constitutes a base of the pnp transistor device.
• the pnp transistor device includes a buried p-type doped channel formed in the n-type doped region and having a maximum dopant concentration at a distance from the upper surface of the semiconductor substrate, wherein the buried p-type doped channel interconnects the source and drain regions.
• the transistor device further comprises field isolation areas formed as shallow trenches around, in a horizontal plane, the n-type doped region, whereby the n-type doped region is separated from the diffused n + -type doped contact.
• the shallow trenches may extend vertically from the upper surface of the substrate and down into the buried n + -type doped region such that the buried n + -type doped region extends into areas located underneath the shallow trenches .
• Deep trenches may surround the transistor device for component isolation purposes .
• Another advantageous feature that may be included in the transistor device is a single self-aligned source-gate contact.
• the contact covers, as seen from above, at least a portion of the gate region and the source region substantially completely. If the gate region surrounds, in a horizontal plane, the source region, the contact may be made to fill out a contact hole to the source region and to contact with the surrounding gate region.
• the present invention includes an integrated circuit comprising at least one pnp transistor as described above.
• an object of the present invention to provide a method in the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, including a lateral pnp transistor based on a PMOS transistor structure, which overcomes the problems mentioned above .
• the present invention comprises a method, which includes the steps of: forming in a p-type doped substrate a buried n + -type doped region; forming in the substrate an n-type doped region above the buried region; forming field isolation areas around, in a horizontal plane, the n-type doped region; forming a ' buried p-type doped channel in the n-type doped region such that the buried p-type doped channel has a maximum dopant concentration at a distance from an upper surface of the semiconductor substrate by means of ion implantation; forming a PMOS gate region on the n-type doped region; forming a diffused n + -type doped contact from the upper surface of the substrate to the buried n + -type doped region; forming separated PMOS source and drain regions in the n-type doped region in such a way that the source and drain regions become interconnected by the buried p-type doped channel; and connecting the PMOS structure thus obtained
• Figs. 1 and 2 are highly enlarged cross-sectional views of pnp transistors according to two preferred embodiments of the present invention.
• Figs. 3-10 are highly enlarged cross-sectional views of a portion of a semiconductor structure during processing according to yet a preferred embodiment of the present invention.
• Fig. 11 illustrates a preferred layout of important masks and electrical connections to component areas of a pnp transistor fabricated according to the present invention.
• a lateral pnp transistor device in an enlarged cross-sectional view, a lateral pnp transistor device according to a first preferred embodiment of the present invention.
• the pnp transistor device comprises a PMOS-based structure, which in turn includes an n- well 41, wherein a p-type doped source region 198 is centrally located.
• a ring-shaped likewise p-type doped drain region 199 is located in the n-well such that it is separated from and surrounds, in a horizontal plane, the source region 198.
• a ring-shaped gate region 111, 194 is located on top of the n- well 41 and between, in a horizontal plane, the source 198 and drain 199 regions.
• the gate region is comprised of an n + -type doped silicon layer 194 on top of an insulating oxide layer 111.
• the gate is surrounded by composite sidewall spacer structures 203, each preferably comprised of silicon nitride spacer 201 and a thin silicon oxide layer 200.
• n-type doped region 41 Underneath the n-type doped region 41 there is located a buried n + -type doped region 31, also referred to as a buried subcollector in a bipolar fabrication process, which region 31 is connected to the surface by means of a diffused n + -type doped contact 41, 195.
• the diffused n + -type doped contact has a rectangular horizontal cross section, but may alternatively surround, in a horizontal plane, the ring-shaped source region 199.
• the ring-shaped structures may be circular or elliptic, but are preferably rectangular or quadratic .
• the n-well is further surrounded, in a horizontal plane, by field isolation areas 81, preferably shallow trenches filled with oxide.
• the n-type doped region 41 is separated from the diffused n + -type doped contact 41, 195.
• the field isolation areas 81 are preferably extending vertically from the surface and down into the buried n + -type doped region 31.
• the buried n + -type doped region 31 extends into areas located underneath the field isolation areas 81.
• the PMOS-based structure is connected to resemble the principal operation of a pnp transistor.
• the drain region 199 is provided with a metal contact 501 and constitutes a collector of the pnp transistor device; and the diffused n + -type doped contact 41, 195 is provided with a metal contact 502 and the n-well 41, to which the diffused n + - type doped contact 41, 195 via the buried n-type doped region 31 is connected, constitutes a base of the pnp transistor device.
• the gate and source regions 194, 198 are each provided with a metal contact 503, 504, which are interconnected by means of metal connection or bridge 505.
• the source region 198 constitutes an emitter of the pnp transistor device.
• the source 198 and drain 199 regions may in a general instance be provided as two identically formed and doped regions and it is thus appreciated that the source 198 and drain 199 regions are exchangeable. Also, in the structure of Fig. 1 the centrally located source region 198 and the surrounding drain region 199 are exchangeable.
• the source region 198 constitutes an emitter of the pnp transistor device and the drain region 199 constitutes a collector of the pnp transistor device is equivalent to say that the drain region 199 constitutes an emitter of the pnp transistor device and the source region 198 constitutes a collector of the pnp transistor device, and accordingly both these expressions are intended to be included in the present invention.
• the pnp transistor device includes a buried p-type doped channel 506 formed in the n-type doped region 41 below the gate region 111, 194 such that the buried p-type doped channel 506 has a maximum dopant concentration at a distance from there.
• the buried p-type doped channel 506 interconnects the source 198 and drain 199 regions.
• the channel 506 is called a buried p-type doped channel and is indicated as a buried channel in Fig. 1.
• the transistor device of Fig. 1 is advantageously formed in a p- doped substrate, which includes a bulk material and optionally at least one epitaxial layer formed thereon (not illustrated in Fig. 1).
• the distance from the oxide 11 to the maximum p-dopant concentration of the buried channel may be at least 0.01 ⁇ m, more preferably at least 0.02 ⁇ m, and most preferably between about 0.02 and 0.06 ⁇ m.
• the buried channel 506 may have a thickness (i.e. dimension in vertical direction) of at least 0.01 ⁇ m, more preferably at least 0.03 ⁇ m, and most preferably between about 0.03 and 0.07 ⁇ m (measured as full width at half maximum, FWHM, with regards to the doping concentration) .
• the buried channel 506 may have a maximum p-type doping concentration of at least 5*10 16 cm “3 , more preferably at least 8*10 16 cm “3 , and most preferably at about 1- 2*10 17 cm “3 .
• a lateral pnp transistor device is shown in an enlarged cross-sectional view, a second preferred embodiment of the present invention will be described.
• the pnp transistor device of Fig. 2 differs from the Fig. 1 embodiment only with regards to the metallization of the active regions.
• the upper surface of the structure is covered by an insulating or passivation layer 601, in which contact holes are made, e.g. by means of photolithographic patterning followed by etching.
• the material of the sidewall spacer 203 has been selected to a material with substantially different etch rate compared to the insulating layer.
• a common choice would be silicon nitride for the sidewall spacer 201, and silicon dioxide for the insulating layers 601 and 200.
• etching at the edges of the gate 194 will occur possibly in underneath the gate 194 into the gate oxide 111, which will degrade or potentially damage the PMOS transistor.
• the actual dimensions of the source contact will in this way be set of the spacer-to-spacer distance in the center of the structure.
• the contact holes are then filled with metal to form metal contacts 501 and 502 for the drain/collector 199 and for the n- well/base 41, respectively.
• a single metal contact 603 is formed for the source/emitter 198 and the gate 194, which interconnects the source 198 and gate 194 regions in a self-aligned manner.
• the single metal contact 603 covers, as seen from above, at least a portion of the gate region 194 and the source region 198 in the center of the structure substantially completely.
• a contact which is larger than a conventional contact, can simultaneously and in a self-aligned manner be formed, for directly interconnecting and thus shortening the source/emitter 198 and the two gate stripes 194.
• a further aspect of the present invention relates to silicide formation.
• Silicide is generally formed on active silicon regions before metallization to reduce contact resistance between the silicon and the metal. However, for the centrally located source/emitter 198 the recombination rate is increased and the gain (beta) is reduced.
• the transistor device of Fig. 1 and or Fig. 2 may have the source region 198 of doped silicon directly connected to the metal contact 504/603) without having any silicide formed thereon, while the drain region 199, the diffused n + -type doped contact 41, 195 and the gate region 194, all made of doped silicon, have silicide formed thereon, and then the respective metal contacts 501, 502 and 503/603 are connected to the respective silicide layers, and the contact 603 also to the bare silicon surface of the source region 198 (not illustrated in Figs. 1-2).
• a process of manufacturing a lateral pnp transistor device in a bipolar process, to which only a few process steps are added, is described below with reference to Figs. 3-10. To illustrate the process the simultaneous formation of a vertical bipolar npn transistor is also described.
• a starting material 10 consisting of a highly p + -doped wafer 11 is provided, on which a low-doped silicon layer 12 of p-type is grown.
• the p-type wafer can be a homogeneously low-doped p-type wafer (not illustrated).
• regions are formed by means of (i) forming a thin protective layer of silicon dioxide on the layer 12; (ii) forming a mask thereon by photolithographic methods to define areas for a PMOS structure, and the bipolar transistor, respectively; (iii) n + - type doping the areas defined by the mask; (iv) removing the mask; (v) heat treating the structure obtained; (vi) optionally p-type doping in additional areas of the structure; and (vii) exposing the upper surfaces of regions 31 and 33.
• the regions 31 are also referred to as buried n + -type doped subcollectors .
• an epitaxial silicon layer 41 is grown on the surface, which layer is doped in selected regions to obtain regions of n- and p-type (n-wells and p-wells). In Fig. 3 all regions 41 are n-type doped.
• a single homogenous wafer may be provided, in which the buried regions 31 and 33 are formed by means of ion implantation at high energy and in which n- and optionally p-type doped surface regions 41 are formed by means of ion implantation.
• substrate as used herein is intended to mean a wafer, on which optionally a number of epitaxial layers have been grown.
• shallow and optionally deep trenches are formed to surround the respective regions 41.
• the shallow trenches are formed by the steps of (i) forming a hard mask by means of oxidizing the silicon surface; depositing a silicon nitride layer; patterning and etching away the silicon nitride and oxide layers at areas where the trenches are to be formed; and (ii) etching the structure.
• the shallow trenches reoxidized and filled with a deposited oxide 81 subsequently to deep trench filling, see below.
• the shallow trenches can be formed such that they extend vertically from the upper silicon surface, i.e. the upper surface of silicon layer 41, and down to the regions or subcollectors 31, and preferably further down into the subcollectors 31 (not illustrated in Figs. 3-10). Further, the subcollectors 31 and the shallow trenches can be formed relative each other such that the subcollectors 31 extend into areas located underneath the shallow trenches . Note that the n-wells 41 may be formed by ion implantation through the above-mentioned silicon nitride and oxide layers and p-wells may be performed at yet a later stage in the process.
• the deep trenches are formed by the steps of (i) forming a hard mask for the deep trenches by depositing a silicon dioxide layer; and patterning and etching this silicon dioxide layer to define openings for the deep trenches; (ii) etching the deep trenches; (iii) removing the remaining portions of the oxide hard mask layer; (iv) growing a thin oxide on top of the structure; (v) filling the deep trenches with deposited oxide (the thin grown oxide and the deposited oxide being together denoted by 71) and polysilicon 72; (vi) optionally planarizing the polysilicon; and (vii) etching back to remove all polysilicon from the shallow trench areas.
• the shallow trenches are filled with the oxide 81, whereupon the nitride and oxide layers, covering active areas 41, are removed.
• a photo mask 101 is formed on the structure, which is open on the areas, which shall serve as device areas for PMOS devices, see Fig. 3 this being a first step added to a pure bipolar process.
• the wafer is then implanted with a p-type dopant (boron) to form the buried channel or shallow layer 506 as described with reference to Fig. 1, see also pp. 392-397 in S. Wolf, "Silicon Processing for the VLSI Era, Volume 2 - Process Integration", Lattice Press, Sunset Beach, 1990, which is hereby incorporated by reference.
• the energy and dose are preferably selected to obtain a channel depth, channel thickness, and doping profile as described with reference to Fig. 1.
• the dose is further selected to adjust the threshold voltage (VTP) to be in the -0.5 to —1.5 V range.
• VTP threshold voltage
• the exact dose, or combination of doses, and elements are dependent on the oxide thickness and the background doping of the substrate under the PMOS gate. Subsequently, the photo mask 101 is removed.
• the oxide 91 is preferably replaced by a gate oxide 111 on top of the structure using oxide etching followed by thermal oxidation. This oxide renewal is due to high MOS requirements, as the quality of the first oxide is normally not sufficient after being subjected to ion implantation. Following directly, an undoped poly-crystalline or non-crystalline silicon layer 112 is deposited on the gate oxide 111. The resulting structure is shown in Fig. 4.
• a mask 121 which covers the PMOS device areas, is applied to the wafer. Using mask 121 silicon is removed by etching, using the field oxide/gate oxide 81/111 as etch stop. The resulting structure is shown in Fig. 5. The photo mask is then removed using conventional methods.
• low- resistance paths i.e. a collector diffused n + -type doped plugs, from the surface of the wafer to the buried n + -type doped layer 31 are needed.
• the paths are defined lithographically, by applying a mask 131 having open areas 132 and 133 for forming plugs for the bipolar transistor and the PMOS structure, respectively. Doping of n-type is performed through the open areas 132 and 133. Details of the selection of energy and doses are discussed in WO 9853489, which publication being hereby incorporated by reference .
• the thin protective silicon dioxide layer 111 is removed in the open areas .
• the resulting structure is shown in Fig. 6.
• the photo mask 131 is then removed by conventional methods, after which the wafer is optionally given a heat treatment .
• a thin silicon nitride layer is deposited (remaining portions thereof denoted by 141 in Fig. 7), the purpose of which is threefold: (i) to add to the insulator layer deposited in the active area of the bipolar transistor resulting in lower parasitic capacitance for the base-collector junction; (ii) to encapsulate the gate layer 112 of the PMOS structure during subsequent processing; and (iii) to serve as an oxidation-resistant mask for the collector plugs 41 (in openings 132 and 133 in Fig. 6) and the gate layer 112 of the PMOS transistor structure.
• step (viii) formation of an emitter/base opening; (ii) formation of an extrinsic base layer 151; (iii) formation of an oxide layer 152; (iv) formation of an emitter opening within the emitter/base opening; (v) optional formation of a secondary implanted collector 171; (vi) formation of p-type base contact paths 173; (vii) formation of an intrinsic base 174; (viii) formation of nitride sidewall spacers 181; and (ix) formation of a n-type doped polysilicon layer 182 for the emitter contact.
• step (viii) i.e.
• the thin silicon nitride layer 141 is removed on field areas, the diffused n + -type doped contact areas and on PMOS areas .
• a mask 183 is applied, the mask 183 having openings 132 and 133 for the n + -type doped plugs, through which additional n-type dopant is implanted.
• the resulting structure is illustrated in Fig. 7. Thereafter, the mask is removed.
• Other, non-illustrated areas, which will form resistors in the polysilicon layer, may be defined by the mask 183 during implantation.
• an emitter contact 191 and a collector contact 192 of the npn transistor, a gate 194 and a diffused n + -type doped contact 195 of the PMOS transistor structure are formed by means of patterning the structure by a mask 196 and etching the polysilicon layer 182 (and 112 at the PMOS transistor).
• the structure obtained is illustrated in Fig. 8. After the etching the mask 196 is removed.
• the oxide layer 152 on top of the p-type polysilicon layer 151 is removed by means of applying a photo mask 197 and etching until the polysilicon is exposed in the openings of the photo mask 197. After etching an additional p-type dopant implant is performed to dope the respective source 198 and drain 199 areas of the PMOS structure, and the extrinsic base 151 of the bipolar transistor. A resultant structure is shown in Fig. 9. After completed etching and implantation the photo mask 197 is removed.
• emitter activation and drive-in is performed to create n- type doped emitter region 202.
• an oxide-nitride bi-layer is formed on the structure, which layer is subsequently etched anisotropically, such that spacers 203 consisting of remaining portions 200, 201 of the oxide-nitride bi-layer are formed.
• exposed silicon surfaces may be provided with silicide 204 in a self-aligned manner (SALICIDE) to reduce the resistance.
• SALICIDE self-aligned manner
• silicide 204 is formed on top of the exposed silicon areas, before metallization.
• TiSi 2 or CoSi 2 is commonly used. The purpose is to reduce the resistivity of the doped silicon (collector, emitter) and polysilicon (gate), and to lower the contact resistance between the silicon and the metallization.
• the recombination rate is increased and the gain (beta) is reduced.
• Part of the remaining portions 200, 201 of the oxide-nitride bi- layer is, during formation of contact holes, etched away to expose the emitter/source region.
• the drain region 199, the gate region 194, the diffused n + -type doped contact 41, 195, and optionally the emitter contact 191 of the npn transistor can be protected by the same mask (not illustrated in Fig. 10) to further prevent silicide formation on these areas if desired.
• the layout of the lateral pnp transistor device may vary.
• circular gate 194 and drain 199 regions are formed, while the source region 198 and the diffused n + -type doped contact 195 are formed centrally and at one side of the drain region, respectively.
• Fig. 11 another preferred layout of the pnp transistor device is shown, where 210 is the mask layer for the formation of the n + -type doped buried layers, 211 is the mask for the shallow trenches, 212 is the mask for the deep trenches, and 213 is the mask for the PMOS transistor structure.
• Masks 121, 131, 196, and 197 are described above. Note that the design of this component differs from the cross sectional views as also the diffused n + - type doped contact is ring-shaped.
• contact holes 217, 218, 219 and 220 are illustrated for the gate, for the drain (collector) and source (emitter), and for the diffused n + -type doped contact (base), respectively.
• a PMOS transistor structure of the kind described may be used as an ordinary PMOS transistor.
• a buried-channel PMOS will have better current drive ability and gain (transconductance) than the corresponding surface channel device.
• the susceptibility towards punch-through at short gate lengths and high supply voltages will however be decreased, but making the gate longer can compensate for this.
• a gate length of approximately 0.6 um combined with a 120 A thick gate oxide give sufficient margin to allow operation at 5 V.

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