WO2003010883A1 - Amplificateur a etages multiples et circuit integre - Google Patents

Amplificateur a etages multiples et circuit integre Download PDF

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Publication number
WO2003010883A1
WO2003010883A1 PCT/JP2002/006972 JP0206972W WO03010883A1 WO 2003010883 A1 WO2003010883 A1 WO 2003010883A1 JP 0206972 W JP0206972 W JP 0206972W WO 03010883 A1 WO03010883 A1 WO 03010883A1
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WO
WIPO (PCT)
Prior art keywords
amplifiers
signal
circuit
control line
amplifier
Prior art date
Application number
PCT/JP2002/006972
Other languages
English (en)
Japanese (ja)
Inventor
Munehiro Karasudani
Original Assignee
Niigata Seimitsu Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Niigata Seimitsu Co., Ltd. filed Critical Niigata Seimitsu Co., Ltd.
Publication of WO2003010883A1 publication Critical patent/WO2003010883A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H03F3/347—DC amplifiers in which all stages are DC-coupled with semiconductor devices only in integrated circuits

Definitions

  • the present invention relates to a multi-stage amplifier and an integrated circuit, and is particularly suitable for use in a multi-stage amplifier in which a signal gain is sequentially amplified by a plurality of cascade-connected amplifier units.
  • a multi-stage cascade connection of multiple amplifiers is used in limiter amplifiers for FM radio receivers and IF (Integrated Frequency) amplifiers for AM radio receivers to amplify small input signals and obtain large gains.
  • Multistage amplifiers are used to obtain high gain.
  • FIG. 1 is a diagram showing a configuration example of a conventional multistage amplifier.
  • the multistage amplifier is composed of n (4 in this example) amplifiers 1, 2, 3, and 4 cascaded from the input side to the output side.
  • n 4 in this example
  • Each of the amplifiers 1 to 4 is commonly connected to the same power supply VDD, and performs an amplifying operation using the power supply VDD.
  • the amplifiers 1 to 4 of each stage supply power VDD based on digital control signals (power enable (PE) signal and power disable (PD) signal) supplied through the power control line 5. ON / OFF is controlled. Which amplifier sends the PE or PD signal is controlled by the decoder 6.
  • PE power enable
  • PD power disable
  • the small signal input to the first-stage amplifier 1 is amplified by a predetermined level by the amplifier 1 and output. Is done.
  • the signal amplified and output here is input to the second-stage amplifier 2 and further amplified by the amplifier 2 and output.
  • signals are sequentially amplified by the third and fourth stage amplifiers 3 and 4 in the same manner.
  • the amplitude of the small input signal to the first-stage amplifier 1 gradually increases in the later stages, and the signal amplified to a predetermined level is finally output from the fourth-stage amplifier 4. Is done.
  • a high gain of about 80 dB is required for a limiter amplifier of an FM radio receiver and an IF amplifier of an AM radio receiver, and by passing through this multi-stage amplifier, H ( A micro input signal on the order of (microport) is amplified to a signal on the order of mV (microport).
  • one power supply control line 5 is commonly connected to the amplifiers 1 to 4 of each stage. Therefore, a signal on the order of mV is fed back from the final stage amplifier 4 through the common power supply control line 5, and all the amplifiers 1 to 4 are physically coupled by the power supply control line 5.
  • a signal feedback loop is formed by the internal circuit of each of the amplifiers 1 to 4 and the power supply control line 5, and the signal is fed back from the subsequent amplifier to the previous amplifier.
  • the normal amplification signal and the feedback signal interfere with each other, the amplification operation becomes unstable, and the capability of the multistage amplifier is reduced.
  • the signal in the mV order in the final-stage amplifier 4 is fed back to the first-stage amplifier 1 that handles a small signal in the V-order, there is a problem that oscillation occurs.
  • the present invention has been made to solve such a problem, and an object of the present invention is to prevent coupling between circuits of each amplifier and to allow a multistage amplifier to operate stably. Disclosure of the invention
  • the multistage amplifier according to the present invention includes a plurality of amplifiers for amplifying an input signal from a preceding stage and outputting the amplified signal to a next stage; a signal line commonly connected to the plurality of amplifiers; A buffer circuit is provided on at least one input side of the amplifier.
  • the signal line is a power supply control line for supplying a control signal for controlling on / off of a power supply to the plurality of amplifiers to the plurality of amplifiers.
  • the buffer circuit is provided on all input sides of the plurality of amplifiers on the signal line.
  • the buffer circuit includes an inverter circuit for blocking propagation of a signal from the amplifier via the signal line. .
  • a plurality of amplifiers for amplifying an input signal from a previous stage and outputting the amplified signal to a next stage;
  • a power control line for supplying a control signal for controlling turning-off to the plurality of amplifiers; and a power control line provided on each input side of the plurality of amplifiers on the power supply control line.
  • an inverter circuit for blocking propagation of a signal through the circuit.
  • the integrated circuit of the present invention further includes a plurality of processing circuits that process an input signal from a previous stage and output the processed signal to a next stage; a control line commonly connected to the plurality of processing circuits; And a buffer circuit provided on at least one input side of the plurality of processing circuits.
  • a common connection is made to the analog circuit and the digital circuit.
  • a buffer circuit provided on at least one input side of the analog circuit and the digital circuit on the control line.
  • the analog circuit includes a multi-stage amplifier including a plurality of amplifiers for amplifying an input signal from a previous stage and outputting the amplified signal to a next stage.
  • control line is commonly connected to the digital circuit and the plurality of amplifiers
  • the buffer circuit is connected to an input side of the digital circuit on the control line. It is provided on each input side of the plurality of amplifiers.
  • the present invention comprises the above technical means, reflections and the like can be obtained by a buffer circuit provided on the input side of each amplifier on a signal line commonly connected to a plurality of amplifiers constituting a multistage amplifier. As a result, the signal that is fed back from the amplifier toward the signal line cannot pass through the buffer circuit, and the coupling between the circuits can be separated.
  • an analog circuit or a digital circuit is connected on a control line commonly connected to the analog circuit and the digital circuit.
  • a buffer circuit provided on at least one of the input sides prevents digital noise from the digital circuit from entering the analog circuit via the control line, and provides a coupling between the analog and digital circuits. Can be separated.
  • FIG. 1 is a diagram showing a configuration example of a conventional multistage amplifier.
  • FIG. 2 is a diagram illustrating a configuration example of the multistage amplifier according to the present embodiment.
  • FIG. 3 is a diagram illustrating a configuration example of the integrated circuit according to the present embodiment.
  • FIG. 4 is a diagram illustrating a configuration example of the buffer circuit according to the present embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 2 is a diagram illustrating a configuration example of the multistage amplifier according to the present embodiment.
  • n in this example, four
  • amplifiers 1, 2, 3, and 4 are cascaded from the input side to the output side.
  • Each of the amplifiers 1 to 4 is commonly connected to the same power supply VDD, and performs an amplification operation using this power supply VDD.
  • the on / off of the power supply V DD is controlled in each of the amplifiers 1 to 4 based on a digital control signal (PE signal and PD signal) provided through the power supply control line 5.
  • the decoder 6 controls which amplifier sends the PE or PD signal. That is, the decoder 6 decodes an externally supplied address signal, and supplies a PE signal or a PD signal to an amplifier specified based on the address signal.
  • the small signal input to the first-stage amplifier 1 is amplified by a predetermined level by the amplifier 1 and output.
  • the signal amplified and output here is input to the second-stage amplifier 2, and further amplified and output by the amplifier 2.
  • the signals are sequentially amplified by the third and fourth stage amplifiers 3 and 4 in the same manner.
  • the amplitude of the small input signal to the first-stage amplifier 1 gradually increases in the later stages, and the signal amplified to a predetermined level is finally output from the fourth-stage amplifier 4. Is done.
  • the plurality of amplifiers 1, 2, 3, and 4 are connected on the power control line 5 that is commonly connected to the plurality of amplifiers 1, 2, 3, and 4.
  • a plurality of buffer circuits 11, 12, 13, and 14 are provided on all input sides of units 1, 2, 3, and 4.
  • the plurality of buffer circuits 11 to 14 are circuits for cutting off the coupling of the plurality of amplifiers 1 to 4 via the power supply control line 5.
  • These buffer circuits 11 to 14 are provided with two inverters as shown in FIG. 4 in order to prevent signals from propagating from each of the amplifiers 1 to 4 via the power supply control line 5. It is composed of a circuit in which data 51 and 52 are connected in cascade (hereinafter referred to as a double inverter).
  • the decoder 6 supplies the 1 signal or the PD signal to the amplifiers 1 to 4.
  • the PD signal can be passed through the buffer circuits 11 to 14 as it is to control the power supply VDD on / off.
  • the buffer circuits 11 to 14 are configured by double inversion, but the present invention is not limited to this. That is, from the power control line 5 to the amplifiers 1 to 4 Any configuration can be used as long as it allows only the E signal and PD signal to pass, and conversely, the signal from the amplifiers 1 to 4 to the power supply control line 5 can be cut off.
  • the buffer circuits 11 to 14 are provided on the input sides of all the amplifiers 1 to 4, but they need not necessarily be provided in all stages. For example, in order to specifically prevent the large signal of mV order amplified in the final stage from returning to the first stage that handles signals of ⁇ V order, a buffer circuit is provided only for the input stage of one of the amplifiers. It may be inserted. Further, in the above-described embodiment, the power supply control line 5 is described as an example of the signal line commonly connected to each of the amplifiers 1 to 4, but is not limited thereto. If there are other control lines that are commonly connected to each of the amplifiers 1 to 4, a feedback loop may be formed via the control lines. Therefore, it is effective to provide a buffer circuit also on the input side of each of the amplifiers 1 to 4 on the control line.
  • the multi-stage amplifier has been described.
  • the present invention can be arbitrarily applied to a circuit for amplifying a small signal gain.
  • the present invention is not limited to a circuit for amplifying a signal gain, but may be an integrated circuit having a plurality of processing circuits for processing an input signal from a previous stage and outputting the processed signal to a next stage.
  • the present invention can be similarly applied to such an integrated circuit as long as there are commonly connected control lines.
  • the above-described buffer circuit is provided on the input side of each processing circuit.
  • FIG. 3 is a diagram illustrating a configuration example of the integrated circuit according to the present embodiment. Note that, in FIG. 3, components denoted by the same reference numerals as those shown in FIG. 2 have the same functions, and thus redundant description is omitted here.
  • a digital circuit 30 is also integrated on the same semiconductor chip.
  • the output from the decoder 6 is The power supply control line 5 is commonly connected to the amplifiers 1 to 4 of the analog circuit 20 and the internal circuit of the digital circuit 30.
  • a buffer circuit 31 is also provided on the input side of the digital circuit 30 on the power supply control line 5.
  • the analog circuit 20 and the digital circuit 30 are mixed, when the analog circuit 20 and the digital circuit 30 are controlled by using the common power supply control line 5, the digital circuit 30 generates Large digital noise may enter the analog circuit 20 and significantly degrade analog characteristics.
  • the analog circuit 20 and the digital circuit 30 are coupled via the power supply control line 5. This can be prevented, and the problem that the digital noise of the digital circuit 30 goes to the analog circuit 20 and adversely affects the digital circuit 30 can be avoided.
  • buffer circuits 11 to 14 and 31 are inserted into all the input sides of the amplifiers 1 to 4 and the input side of the digital circuit 30 in the analog circuit 20. However, it is not necessary to insert them all. For example, if the only purpose is to prevent digital noise from the digital circuit 30 from entering the analog circuit 20, the digital circuit 3 It is sufficient to provide the buffer circuit 31 only for the 0 input stage.
  • a multi-stage amplifier including a plurality of amplifiers 1 to 4 is shown as an example of the analog circuit 20, but the internal configuration of the analog circuit 20 is not limited to this.
  • the signal line commonly connected to the analog circuit 20 and the digital circuit 30 is not limited to the power supply control line 5, but may be other than the analog circuit 20. If there is a control line or the like commonly connected to the control circuit and the digital circuit 30, it is effective to provide a buffer circuit on the control line.
  • the multi-stage amplifier and integrated circuit of the present embodiment described above are used for AM or FM radio receivers, television receivers, mobile phones, cordless phones, and short-range wireless data communication technology bluetooth. It can be applied to various electronic devices that have the function of receiving and processing high-frequency signals (RF signals), such as wireless LANs, power navigation systems, and game machines with communication functions. is there.
  • RF signals high-frequency signals
  • the buffer circuit is provided on the input side of the amplifier on the signal line commonly connected to the plurality of amplifiers constituting the multi-stage amplifier, so that the plurality of amplifiers share the common signal line.
  • Can be prevented from being bonded via the This makes it possible to prevent a signal from being fed back from a subsequent-stage amplifier to a preceding-stage amplifier, thereby avoiding the disadvantage that the amplified signal and the feedback signal interfere with each other and limit the gain of amplification. Can be.
  • a large signal at the subsequent stage returns to the first stage that handles a small signal and oscillates. Inconvenience can be avoided, and the multistage amplifier can be operated stably.
  • At least one of the analog circuit and the digital circuit is provided on a control line commonly connected to the analog circuit and the digital circuit. Since a buffer circuit is provided on either input side, the analog circuit and the digital circuit can be prevented from being coupled via a common control line, and digital noise from the digital circuit Through the analog circuit.
  • the present invention is useful for preventing coupling between circuits of each amplifier and enabling a multistage amplifier to operate stably.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

La présente invention concerne une ligne (5) de commande de source électrique connectée en commun à des amplificateurs (1-4) qui constituent un amplificateur à étages multiples, pourvue de circuits tampon (11-14) positionnés sur le côté entrée de ces amplificateurs (1-4) de façon qu'on ne puisse pas raccorder ces amplificateurs (1-4) via cette ligne (5) de commande de source électrique. On peut ainsi éviter le cas défavorable dans lequel un signal d'amplification se brouille avec un signal de retour par le retour d'un signal en provenance de l'amplificateur d'étage postérieur et à destination de l'étage antérieur ainsi que le cas défavorable dans lequel un gros signal d'amplificateur d'étage postérieur oscille par retour vers l'étage initial en vue de traiter un microsignal.
PCT/JP2002/006972 2001-07-23 2002-07-10 Amplificateur a etages multiples et circuit integre WO2003010883A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-220876 2001-07-23
JP2001220876A JP2003037445A (ja) 2001-07-23 2001-07-23 多段増幅器および集積回路

Publications (1)

Publication Number Publication Date
WO2003010883A1 true WO2003010883A1 (fr) 2003-02-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/006972 WO2003010883A1 (fr) 2001-07-23 2002-07-10 Amplificateur a etages multiples et circuit integre

Country Status (3)

Country Link
JP (1) JP2003037445A (fr)
TW (1) TW552772B (fr)
WO (1) WO2003010883A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376408A (ja) * 1989-08-18 1991-04-02 Nec Corp 電圧制御減衰回路
JPH09135131A (ja) * 1995-11-07 1997-05-20 Nec Corp 可変利得増幅器
JP2001177361A (ja) * 1999-12-20 2001-06-29 Sony Corp 利得制御回路およびこれを用いた無線通信装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232744A (ja) * 1993-01-29 1994-08-19 Canon Inc 信号処理装置
JPH0818348A (ja) * 1994-06-30 1996-01-19 Matsushita Electric Ind Co Ltd 可変利得増幅器
JPH1155051A (ja) * 1997-07-29 1999-02-26 Matsushita Electric Ind Co Ltd 電力増幅回路
JP2001094050A (ja) * 1999-09-21 2001-04-06 Mitsubishi Electric Corp 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376408A (ja) * 1989-08-18 1991-04-02 Nec Corp 電圧制御減衰回路
JPH09135131A (ja) * 1995-11-07 1997-05-20 Nec Corp 可変利得増幅器
JP2001177361A (ja) * 1999-12-20 2001-06-29 Sony Corp 利得制御回路およびこれを用いた無線通信装置

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Publication number Publication date
TW552772B (en) 2003-09-11
JP2003037445A (ja) 2003-02-07

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