WO2002099870A1 - Procede de production d'un dispositif semi-conducteur - Google Patents

Procede de production d'un dispositif semi-conducteur Download PDF

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Publication number
WO2002099870A1
WO2002099870A1 PCT/JP2002/005515 JP0205515W WO02099870A1 WO 2002099870 A1 WO2002099870 A1 WO 2002099870A1 JP 0205515 W JP0205515 W JP 0205515W WO 02099870 A1 WO02099870 A1 WO 02099870A1
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trench
layer
etching
manufacturing
semiconductor device
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PCT/JP2002/005515
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English (en)
Japanese (ja)
Inventor
Osamu Kusumoto
Toshiya Yokogawa
Masao Uchida
Kenya Yamashita
Ryoko Miyanaga
Makoto Kitabatake
Kunimasa Takahashi
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Matsushita Electric Industrial Co., Ltd.
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Publication of WO2002099870A1 publication Critical patent/WO2002099870A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the present invention relates to a semiconductor power device used for high withstand voltage and large current, particularly to a semiconductor power device using a hard semiconductor such as silicon carbide.
  • semiconductor power devices are often used for power transmission, power control, and the like, and there are power semiconductor devices such as power MISFET and IGBT.
  • power semiconductor devices such as power MISFET and IGBT.
  • silicon carbide (SiC) has an order of magnitude higher dielectric breakdown field than silicon
  • semiconductor power devices using silicon carbide are expected to be devices with high withstand voltage and low on-resistance. Is being promoted.
  • FIG. 5 is a cross-sectional view of a conventional MISFET having a trench gate structure (hereinafter, referred to as a trench MISFET). As shown in the figure, this trench MISFET is epitaxially grown on a low-resistance n-type SiC substrate 101 and an n-type SiC substrate 101, A high-resistance layer 102 composed of a SiC layer containing an n-type impurity at a concentration lower than 01, and a SiC layer epitaxially grown on the high-resistance layer 102 and containing a p-type impurity.
  • a trench is formed through the base layer 103 to reach the high-resistance layer 102, and a gate insulating film 109 formed of an oxide film formed along the wall surface of the trench and a gate insulating film 109 are formed.
  • a gate electrode 110 made of polysilicon formed on the film 109 and filling the trench is provided.
  • a source electrode 111 that forms an ohmic junction with the source layer 104 and a drain electrode 111 that forms an ohmic junction with the back surface of the SiC substrate 101 are formed.
  • the source electrode 111 is fixed to the ground potential VSS, and the power supply voltage VDD is applied to the drain electrode 112.
  • VDD power supply voltage
  • a voltage equal to or higher than the threshold voltage Vth is applied to the gate electrode 110, a carrier inversion layer is formed in a region of the base layer 103 in contact with the gate insulating film 109, and the source Current flows between the drain electrodes.
  • the above-mentioned conventional trench MISFET is a type of vertical MISFET and can flow current over a wide area in the thickness direction of the substrate, thus exhibiting excellent performance as a power semiconductor device requiring a large current. be able to.
  • FIGS. 6 (a) to 6 () are cross-sectional views showing a manufacturing process of a conventional trench MISFET.
  • a low resistance n-type SiC substrate 101 is composed of a SiC layer containing an n-type impurity at a lower concentration than the SiC substrate 101.
  • the high resistance layer 102 and the base layer 103 made of the S′iC layer containing the p-type impurity are sequentially grown epitaxially.
  • a SiO 2 mask is formed by depositing a silicon oxide film, photolithography, and dry etching, and the SiO 2 mask is used as an injection mask, and the base layer 1 is formed.
  • a source layer 104 is formed by implanting high-concentration n-type impurity ions into a part of O3.
  • a high concentration p-type impurity is implanted into a region of the base layer 103 located on the side of the source layer 104 to form a P + type contact layer 105.
  • a trench 109 is formed by dry etching using high-density plasma using the Al mask 109 as an etching mask.
  • the source layer 104 and the p + type contact layer 105 are removed from the trench wall by thermal oxidation.
  • Upper surface A gate insulating film 109 made of a silicon oxide film is formed.
  • a p-type polysilicon film is deposited on the gate insulating film 109 and then patterned to form a gate electrode 110 filling the trench. . Further, the gate insulating film 109 is patterned to expose the upper surfaces of the source layer 104 and the p + -type contact layer 105. Thereafter, by depositing a nickel film and patterning the same, a source electrode 111 is formed, which is in homo-junction with the source layer 104 and the p + -type contact layer 105.
  • the conventional trench MISFET has the following disadvantages in the manufacturing process.
  • the process of forming the trench in which the gate electrode is buried is a very important process.
  • the depth of the trench in the trench MISFET varies depending on the required breakdown voltage and the like, but a trench with a breakdown voltage of several hundred V requires a depth of several micrometers.
  • SiC is hardly removed by wet etching because it is composed of a strong bond between silicon atoms and carbon atoms, and dry etching is used exclusively.
  • the etching rate is very low. For example, when parallel plate RIE (reactive ion etching) is used, the etching rate when etching is performed using a mixed gas of CF 4 and O 2 is about 50 nm / min.
  • FIGS. 7A and 7B are a cross-sectional view showing a vertical cross-sectional shape of a trench formed by dry etching using high-density plasma, and a cross-sectional view showing a supply state of fluorine ions to the trench.
  • the gas pressure 0. 6 P a
  • the antenna power 5 0 0 W the bias RF power 2 0
  • trench etching of the SiC layer is performed.
  • a small groove is formed at the bottom edge of the trench 107, which is called a micro-trench 108.
  • the micro-trench 108 Since the micro-trench 108 has a very small radius of curvature, when a voltage is applied between the gate electrode 110 and the SiC substrate 112, an electric field concentrates on the micro-trench 108, and the gate The insulating film 109 tends to cause dielectric breakdown at this portion. Therefore, if this phenomenon called trenching occurs, the breakdown voltage of the trench MISFET may decrease.
  • Etching species are ions or radicals that cause a chemical reaction with atoms of the object to be etched to promote etching.
  • Deposited species are radicals, ions, atoms, molecules, etc. that do not contribute to the chemical reaction of etching and form a deposited film deposited on the surface of the object to be etched.
  • a flon gas such as CF 4 or C 3 F a
  • Edzuchingu species is F
  • deposition species is Cx F y (x, y are arbitrary integers).
  • the etching species F ions or F radicals react with the Si, C atoms of the SiC layer, which is the object to be etched, as follows, whereby the etching proceeds.
  • deposition species polymerize to carbon Flora I de (C x F y: x, y are arbitrary integers) to form a polymer consisting of, the polymer is deposited on the substrate surface.
  • the polymer does not chemically react with the etching species. Therefore, the portion of the SiC layer covered by the polymer is not etched.
  • the table of the SiC layer The polymer deposited on the surface is physically removed by the ions incident on the substrate, so that the atoms in the exposed portion of the SiC layer react with the depot species and the etching proceeds.
  • the etching rate changes according to the relative existence ratio (relative amount) of the deposition species and the etching species on the surface of the SiC layer. That is, in the vicinity of the surface of the SiC layer, the etching progresses more in the portion where the proportion of the etching species relative to the deposition species is large, and conversely, the etching does not proceed much in the portion where the proportion of the etching species relative to the deposition species is small.
  • the etching species 120 is not consumed, so that some of the etching species 120 are It flows into the end of the bottom of the trench 107 through the side wall of 07. Therefore, on the bottom surface of the trench 107, in addition to the etching species directly reaching the bottom surface from above, there are etching species flowing from around the trench 107.
  • the distribution of the etching species on the bottom surface of the trench 107 is larger at the end than in other regions. As described above, where the relative amount of the etching species with respect to the deposition species is large, the progress of etching is promoted, so that the micro-trench 108 is formed at the bottom end of the trench 107.
  • An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving a shape abnormality generated at a bottom end portion of a trench while maintaining a time required for an etching process for forming a trench within a range suitable for practical use. Is to do.
  • a first method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device having a semiconductor layer and a trench provided in the semiconductor layer, wherein a trench forming region is formed on the semiconductor layer.
  • step (b) as in conventional dry etching, a shape abnormality called a micro-trench occurs at the end of the bottom of the trench, but in step (d), the radius of curvature of the bottom end is reduced. Rounded to be larger.
  • the reason for this effect is that, in the step (d), the etching seed is consumed even on the exposed surface of the semiconductor layer around the trench, so that the etching seed at the edge of the bottom of the trench is consumed. This is thought to be because the relative abundance ratio for the sedimentary species is lower than in step (b). Therefore, in a semiconductor device using the trench, it is possible to eliminate problems such as concentration of an electric field on the end of the bottom surface of the trench.
  • etching time can be reduced by performing dry etching using high-density plasma.
  • the etching is performed under a more isotropic condition than in the above step (b), whereby the radius of curvature of the microtrench can be effectively enlarged.
  • the step of reaching the semiconductor layer is higher than in the above step (b). It is preferable to perform the etching under the condition that the ion energy of the plasma is small. Since the semiconductor layer is a silicon carbide layer, it is possible to manufacture a power transistor using a silicon carbide wide band gap.
  • step (b) it is preferable to use a gas containing a fluorine atom as the etching gas.
  • the second method of manufacturing a semiconductor device includes a step of forming a high resistance layer containing a first conductivity type impurity at a lower concentration than the semiconductor substrate on an upper surface of the semiconductor substrate containing the first conductivity type impurity.
  • A a step of forming a base layer containing a second conductivity type impurity on the high resistance layer (b), and doping a first conductivity type impurity on the base layer to form a source
  • step (e) forming a trench that reaches the high-resistance layer through the pace layer.
  • the etching mask is removed to remove at least a part of the upper surface of the source layer.
  • the step of exposing (f) (G) etching a region of the source layer and the base layer exposed in at least a part of the trench and the upper surface of the source layer and the base layer with the etching mask removed;
  • step (g) the radius of curvature at the end of the bottom surface of the trench is enlarged, so that the electric field concentration at the lower end of the gate electrode is reduced, and the semiconductor functioning as a high pressure-resistant trench MISFET A device is obtained.
  • the step (g) is performed such that the radius of curvature at the bottom end of the trench is not less than 0.2 ⁇ m.
  • the step (g) is performed such that a radius of curvature at an upper end edge of a side wall of the trench is 0.2 or more.
  • the semiconductor layer is a silicon carbide layer, it functions as a power transistor. A practicable, high withstand voltage semiconductor device can be obtained.
  • the etching time can be shortened as much as possible, and mass productivity can be secured.
  • FIG. 1 is a cross-sectional view of a trench MISFET in the embodiment.
  • 2 (a) to 2 (g) are process diagrams showing a method for manufacturing the trench MISFET according to the embodiment.
  • FIG. 3 is a cross-sectional view for explaining the effect of the trench etching of the embodiment.
  • FIGS. 4 (a) and 4 (b) are views respectively simulating cross-sectional SEM images of a conventional trench MISFET and the trench MISFET of the present embodiment.
  • FIG. 5 is a cross-sectional view of a conventional trench MISFET.
  • 6 (a) to 6 (f) are cross-sectional views showing the steps of manufacturing a conventional trench MISFET.
  • FIGS. 7 (a) and 7 (b) are a cross-sectional view showing a vertical cross-sectional shape of a trench formed by dry etching using high-density plasma, respectively, and a cross-sectional view showing a supply state of fluorine ions to the trench. Best Embodiment
  • FIG. 1 is a cross-sectional view of a MISFET having a trench gate structure (hereinafter, referred to as a trench MISFET) according to the embodiment.
  • this trench MIS FET is epitaxially grown on a low-resistance n-type SiC substrate 1 and an n-type SiC substrate 1 and has a lower concentration than the SiC substrate 1.
  • a high-resistance layer 2 composed of a SiC layer containing n-type impurities, a base layer 3 composed of a SiC layer epitaxially grown on the high-resistance layer 2 and containing a p-type impurity,
  • the source layer 4 formed by implanting high-concentration n-type impurity ions into the surface region of the source layer 3 and the high-concentration P-type impurity ions And a p + -type contact layer 5 formed by injecting P + .
  • a trench is formed through the base layer 3 to reach the high-resistance layer 2, and a gate insulating film 9 made of an oxide film formed along the wall surface of the trench and a trench formed on the gate insulating film 9 are formed.
  • a gate electrode 10 made of polysilicon for filling the trench is provided.
  • a source electrode 11 that makes an ohmic junction with the source layer 4 and a drain electrode 12 that makes an ohmic junction with the back surface of the SoC substrate 1 are provided.
  • the source electrode 11 is fixed to the ground potential V SS, and the power supply voltage VDD is applied to the drain electrode 12.
  • VDD the power supply voltage
  • a voltage equal to or higher than the threshold voltage Vth is applied to the gate electrode 10
  • a carrier inversion layer is formed in a region of the base layer 3 that is in contact with the gate insulating film 9, and the source and drain electrodes are formed. Current flows between them.
  • the trench MISFET of the present embodiment is a type of vertical MISFET, and can flow current over a wide area in the thickness direction of the substrate, and thus exhibits excellent performance as a power semiconductor device requiring a large current. be able to.
  • the feature of the trench MISFET of the present embodiment is that the microtrench at the bottom end of the trench is rounded so as to increase the radius of curvature, and that the corner at the top end of the trench is rounded. It is.
  • a manufacturing process for obtaining such a structure will be described.
  • Figure 2 (a) ⁇ (g) are process diagrams showing a manufacturing how silicon carbide preparative wrench MISP 1 ET of the present embodiment.
  • a low-resistance SiC substrate 1 having an n-type impurity (for example, nitrogen) concentration of about lxl0 18 cm 3 is prepared.
  • an SiC layer having an n-type impurity (eg, nitrogen) concentration of about 3 ⁇ 10 15 cm 3 and a thickness of 10 ⁇ m is formed on the SiC substrate 11 by a thermal CVD method.
  • the high resistance layer 2 is epitaxially grown.
  • a SiC layer having a p-impurity (for example, aluminum, boron, etc.) concentration of about 2 ⁇ 10 16 cm 3 and a thickness of 2.5 ⁇ m is formed on the high-resistance layer 2 by a thermal CVD method.
  • the base layer 3 consisting of layers is epitaxially grown.
  • the thickness of the base layer 3 is set to be 0.5 ⁇ m thicker than that in the conventional process in consideration of the removal by 0.5 ⁇ m in the second etching step at the time of forming the trench. ing.
  • a SiO 2 mask is formed by depositing a silicon oxide film, photolithography, and dry etching, and using the SiO 2 mask as an injection mask, the substrate temperature is reduced. While keeping the temperature at 500 ° C. to 100 ° C., high concentration n-type impurity ions (for example, nitrogen ions) are implanted into a part of the base layer 3 to form the source layer 4. At this time, the doping concentration is about 1 ⁇ 10 19 cm 3 , and the implantation depth is about 800 nm.
  • a high concentration P-type impurity eg, aluminum, boron, etc.
  • the doping concentration is 1 ⁇ 10 18 cm— 3 or more, and the implantation depth is around 800 nm.
  • activation annealing is performed at a temperature of 150 ° C.
  • the implantation depth is set to 0.5 m thicker than the thickness in the conventional step in consideration of the removal of 0.5 ⁇ m in the second etching step when forming the trench. ing.
  • trench etching is performed in the step shown in FIG. First, after depositing a 200-nm-thick A1 film on the substrate, photolithography is used to remove the A1 film in the area where the trench is to be formed by ion milling etching. .
  • the first etching step is performed by using the A1 mask 6 that has been thus patterned.
  • etching was performed using a high-density plasma using an ICP-type dry etching apparatus.
  • the vacuum chamber one (not shown), and the flow rate of 3 2 of CF 4 (m 1 / mi n .), 0 2 of the flow rate and 8 (m 1 / min.) ,
  • the chamber one The pressure is maintained at 0.6 Pa.
  • RF power of 13.56 MHz and 500 W is applied to the antenna coil provided on the vacuum chamber, and RF power of 13.5 MHz and 20 W is applied to the bias electrode below the substrate. Power was turned on.
  • the etching rate of the SiC layer under this condition is 0.06 m / min. Therefore, it takes about 50 minutes to perform a trench etching to a depth of 3 m.
  • the steps so far are performed under substantially the same conditions as in the conventional technique. At this time, when the shape of the trench 7 was confirmed by the cross-sectional SEM, as shown in FIG. 3 ⁇ m. This is also substantially the same as the micro-trench in the prior art.
  • the second Edzuchingu step no state is A 1 mask, that is, in a state where the entire surface of the substrate is exposed, as in the first etching step, using Doraiedzuchingu device I CP method, the flow rate of CF 4 the 3 2 (ml / mi n. ) and were, 0 2 of the flow rate of 8 (ml / min.), the pressure were maintained 0. 6 P a, 1 to the antenna coil 3.
  • the taper angle of the side wall As close as possible to 90 °, so that the RF power below the substrate is increased and the ion energy is increased, but in the entire etching, the micro trench is not used.
  • a 2.5-im thick polysilicon film doped with a high concentration of P-type impurity (boron) is deposited on the gate insulating film 9 by CVD. After that, the polysilicon film is patterned by photolithography and dry etching to form a gate electrode 10 filling the trench.
  • P-type impurity boron
  • a portion of the gate insulating film 9 located in the source electrode formation region is removed by photolithography and wet etching. Then, the source electrode formation region of the source layer 4 and the p + type contact layer 5 is exposed. After that, a 200 nm-thick nickel film is formed on the substrate in the resist film and the source electrode formation region by vapor deposition, and then positioned in the source electrode formation region of the nickel film by a lift-off method. The source electrode 11 is formed leaving only the portion to be formed. Further, a drain electrode 12 made of a nickel film having a thickness of 200 nm is formed on the back surface of the SiC substrate 1 by vapor deposition.
  • FIG. 3 is a cross-sectional view for explaining the effect of the trench etching of the present embodiment.
  • two etchings are performed as the trench etching.
  • the first etching shown in FIG. 2 (c) is performed. Since the first etching is performed under almost the same condition as the conventional trench etching, as shown in the broken line in FIG.
  • Micro-trench 8 is generated at the bottom edge of the. At this time, the depth from the bottom of the microtrench 8 is about 0.5 ⁇ m, and the vertical cross-sectional shape of the microtrench 8 is a sharp wedge with an opening angle of about 5 °.
  • the micro-trench 8 has a shape as shown by the solid line in FIG. At this time, the depth from the bottom surface of the microtrench 8 is about 0.1 m, and the vertical cross-sectional shape of the microtrench 8 is a hemisphere having a radius of curvature of about 0.3 m. In other words, the micro-trench 8 has a shallower depth and a wider width. The edge of the upper end of the side wall of the trench 7 is also rounded, and the radius of curvature is about 0.3 zm.
  • FIGS. 4 (a) and 4 (b) are diagrams in which the cross-sectional SEM images of the conventional trench MIS FET and the trench MISFET of the present embodiment are copied in that order. 4 (a) and 4 (b) are further provided with explanatory diagrams.
  • the SEM image shown in FIG. 4 (b) shows that the second etching time is longer than in the above embodiment. Thus, the micro-trench is almost completely extinguished.
  • the A1 mask did not exist, but this was because it was removed to capture the SEM image. It is done in a state.
  • the etching species such as the area covered by the A1 mask flows into the bottom end, whereas in the first and second etchings, Since the A1 mask has been removed, the etching seeds are also consumed on the substrate surface around the trench.
  • the relative abundance (relative ratio) of the etching species to the deposited species near the bottom edge of the trench is not so high, so that the isotropic etching proceeds, and the top edge of the micro-trench or trench side wall is removed. It is considered to be rounded. It is also considered that the fact that the RF power applied to the via electrode below the substrate is as low as 10 W contributes to the progress of isotropic etching.
  • the micro-trench at the bottom of the trench generated by the first etching is rounded by the second etching, whereby the concentration of the electric field in the trench MISFET can be reduced, and the high withstand voltage can be reduced. Characteristics can be maintained.
  • the leak current sharply increases from the time when a voltage of about 10 V is applied between the gate and the source. In other words, the gate bias that can be applied is limited to about 10 V.
  • the trench MISFE having a high gate-source withstand voltage is provided. It can be seen that T is obtained.
  • the etching time is 50 minutes for the first etching and 10 minutes for the second etching, that is, 60 minutes in total, and the etching time is further increased as compared with the conventional trench etching. None.
  • reducing the RF power during trench etching to reduce the relative proportion of the etching species to the deposition species in the entire chamber. For example, reducing the RF power from 5 0 0 W to 40 0 W, can reduce the ratio of F to dissociate from CF 4. However, in that case, the etching time is considerably increased, so that this is not a very practical means.
  • a mixed gas of CF 4 and O 2 is used as an etching gas.
  • a mixed gas of SF 6 and O 2 higher-speed etching can be performed.
  • the flow rate of SF 6 and 2 0 (m 1 / mi n .), 0 as second flow of 0 ⁇ 2 0 (ml / mi n .), And the pressure in the chamber first and 0. 6 P a When the etching of the SiC layer is performed under the condition that the RF power of the antenna coil is set to 500 W and the RF power of the bias electrode below the substrate is set to 20 W, the etching rate is 0.16 m / min. .
  • CF 4 and SF 6 and 0 2 mixed Further gas may be used with, in the present embodiment, as the material of the etching mask in the trench E Uz quenching has been used A 1, N i (Nidzukeru) May be used.
  • a semiconductor device having a SiC layer as a semiconductor layer has been described as an example.
  • the present invention is not limited to such an embodiment, and GaN, A 1 N, and the like are also used as semiconductor layers. Can be used.
  • the effect of mitigating a microphone opening trench caused by trenching can be reduced. Obtainable.
  • the electric field concentration of the trench MISFET can be reduced and the breakdown voltage characteristics can be maintained high. it can.
  • the radius of curvature at the upper edge of the sidewall of the trench after completion of the second etching is 0.2 ⁇ m or more, the electric field concentration of the trench MISFET is relaxed, and the breakdown voltage characteristic is maintained high. be able to.
  • the trench MIS FET has been described as an example of a semiconductor device.
  • the present invention is not limited to such an embodiment, and particularly, in a semiconductor device requiring a deep trench in general, The shape abnormality at the bottom end of the trench can be improved.
  • the gate insulating film does not necessarily need to be a thermal oxide film, nor does it need to be a silicon oxide film.
  • a silicon nitride film, a tantalum oxide film, etc. can be used as the gate insulating film.
  • the present invention can also be applied to a p-channel trench MISFET.
  • a p-type high resistance layer, an n-type base layer, and a p + -type source layer are formed using the p + -type SiC substrate.
  • etching was performed with the A1 mask removed and the entire surface of the substrate exposed, but it is not always necessary to expose the entire surface, and the source layer 4 and the If at least a part of the p + -type contact layer 5 is exposed, the exposed portion consumes the etching species, so that the basic effects of the present invention can be obtained.
  • the present invention is used for a device such as a vertical MOS FET mounted on an electronic device, particularly for a device that handles a high-frequency signal and a power device.

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  • Drying Of Semiconductors (AREA)

Abstract

Une couche à haute résistance de type P (2) et une couche de base de type N (3) sont produites en séquence par croissance épitaxiale sur un substrat SiC de type P (1). Après la formation d'une couche de source (4) dans la couche de base (3) par implantation ionique, une tranchée (7) pénétrant dans la couche de source (4) et une couche de base (5) jusqu'à la couche à haute résistance (2) est formée par gravure sèche (première gravure) au moyen d'un plasma à haute densité avec un masque Al (6) maintenu fixé. Même si une anomalie de forme appelée micro-tranchée (8) se produit sur l'extrémité inférieure de la tranchée (7), le rayon de courbure de la micro-tranchée (8) peut être accru par gravure sèche de la surface entière sous condition d'isotropie élevée après le retrait du masque Al (6).
PCT/JP2002/005515 2001-06-04 2002-06-04 Procede de production d'un dispositif semi-conducteur WO2002099870A1 (fr)

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