WO2002093792A1 - Procede et circuit de reception synchrone de donnees grande vitesse a liaison montante dans un systeme de communication optique - Google Patents

Procede et circuit de reception synchrone de donnees grande vitesse a liaison montante dans un systeme de communication optique Download PDF

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Publication number
WO2002093792A1
WO2002093792A1 PCT/CN2002/000204 CN0200204W WO02093792A1 WO 2002093792 A1 WO2002093792 A1 WO 2002093792A1 CN 0200204 W CN0200204 W CN 0200204W WO 02093792 A1 WO02093792 A1 WO 02093792A1
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WIPO (PCT)
Prior art keywords
data
clock
circuit unit
channel
phase
Prior art date
Application number
PCT/CN2002/000204
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English (en)
Chinese (zh)
Inventor
Tao Liu
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Huawei Technologies Co., Ltd.
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Filing date
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Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2002093792A1 publication Critical patent/WO2002093792A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Definitions

  • the present invention relates to the field of optical communication technology, and more particularly, to a method and a circuit for synchronously receiving uplink high-speed burst data in an optical communication system.
  • ATM passive optical network ATM-Passive Optical Network
  • TDMA-Time Division Multiple Access
  • special technology and special methods are required to synchronize uplink data.
  • ATM Asynchronous Transfer Mode
  • ONT optical Network Unit
  • bit synchronization is required to align the data and complete byte synchronization and cell synchronization of the data at the same time. This is the problem of fast bit synchronization reception in the present invention; for example, due to the uplink ATM Cells may come from different far ends and are bursts of data, so the synchronization process needs to be performed on a cell-by-cell basis.
  • the special method and circuit adopted in order to obtain the maximum time margin, must locate the sampling clock at the receiving end of the OLT in the middle of the eye diagram of the input data.
  • a commonly used positioning method is to use phase-locked loop (PLL: Phase-Locked Loop) technology.
  • PLL Phase-Locked Loop
  • the phase detector first detects the phase of the upstream serial burst data and the rising and falling edges of the sampling clock to generate "up” (rising) and “(1 ( ⁇ 1" (falling) pulses. It is sent to a “charge pump” (charge pump), and the output voltage of the charge pump is used to control a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) to generate a clock with an appropriate phase.
  • VCO Voltage Controlled Oscillator
  • a more commonly used positioning method is to use a four-phase clock to oversample the high-speed uplink serial burst data.
  • the far end adds a special preamble to the cell header of the transmitted uplink serial data.
  • the central office receives, if a phase clock samples the correct preamble, it considers that the phase of the clock meets the requirements, and selects the The phase clock is used as the synchronization clock, and then the bit data sampling, byte data conversion, and cell recovery are completed.
  • the disadvantages of this method are: first, the selected clock is not necessarily located in the middle of the data, and the time margin provided may be small; second, it is difficult to meet the requirements for normal system operation in the case of high-speed applications; second, The phase noise of the system makes it difficult to achieve accurate tracking.
  • the purpose of the present invention is to design a method and a circuit for synchronously receiving uplink high-speed data in an optical communication system, to solve the existing problems of synchronous high-speed serial burst data of the A-PON system in the prior art solution, and It has the advantages of simple structure and easy implementation.
  • a method for synchronously receiving uplink high-speed data in an optical communication system which is characterized in that it is a multi-phase clock fast bit synchronous receiving method, including-.
  • A. Use the X-phase clock to oversample the received uplink high-speed serial burst data separately. Adapt the obtained data of channel X to the local clock, where X is a positive integer;
  • the X-phase clock is an 8-phase or 16-phase clock, and adjacent two-phase clocks have the same phase difference of 1 / X clock cycle.
  • the step A further includes: generating the X-phase data with the same phase data generated by the clock generation circuit and oversampling to obtain X-channel data; adapting the X-channel data to the local clock at a corresponding X-channel adaptation stage; The corresponding X-channel shift stages respectively shift the X-channel data adapted to the local clock to synchronize the X-channel data.
  • the X-channel data is adapted to the local clock by the corresponding X-channel adaptation stage.
  • the output data of the previous phase clock is sent to the data terminal of the register driven by the subsequent phase clock, and finally sent to the The data side of the local clock driven register is done.
  • Row shifting is performed by shifting the data by a local clock with 8 + 1 stages of serial registers.
  • the step B further includes: comparing the data of the X channel adapted to the local clock with the preamble, and judging the data of the detected preamble as correct data; performing polarity detection to test the rise and fall of the correct data. Along to replace the data.
  • the X-channel data adapted to the local clock is compared with the preamble, and if all bits are the same or only one bit is different, it is determined that the preamble is detected, and the number of preambles is detected. It is judged as correct data.
  • the polarity detection further includes: setting initial vectors hitl to hit8, so that "0" when the comparison result is different and " ⁇ " when the comparison result is the same respectively indicate the comparison result between the data and the preamble; from low to high, An exclusive-OR operation is performed on the comparison result of two adjacent initial vectors, and the operation result is put into a flag; the low 1 and high 1 of the flag are the rising and falling edges of the correct data, respectively.
  • the step C further includes: decoding a position a of the low order 1 in the flag by a selection logic circuit unit, decoding a position b of the high order 1 in the flag, and selecting ( a + b) Serial-to-parallel conversion and cell synchronization of the correct data sampled by the / 2-phase clock.
  • the method further includes directly dividing the local clock to generate the serial-to-parallel clock of the parallel data, and transmitting the data to the synchronization receiving circuit along with the data.
  • a synchronous receiving circuit for uplink high-speed data in an optical communication system which is characterized by including an X-phase clock generating circuit unit and an X-channel uplink high-speed serial burst data sampling circuit.
  • the generating circuit unit is respectively connected to the X-channel uplink high-speed serial burst data sampling circuit unit; the X-channel uplink high-speed serial burst data sampling circuit unit is correspondingly connected to the X-channel preamble detection circuit unit and connected to the X-channel data selection circuit unit in the byte and cell synchronization unit; the X-channel preamble detection circuit unit is connected to the selection logic circuit unit and the synchronization signal selection circuit in the byte and cell synchronization unit, respectively The selection logic circuit unit is respectively connected to the synchronization in the byte and cell synchronization unit No.
  • the X-channel data selection circuit unit and synchronization signal selection circuit unit in the byte and cell synchronization unit are respectively connected to the serial-parallel conversion circuit unit; a local clock connection Number of uplink high-speed serial bursts to X According to the sampling circuit unit and the X-channel preamble detection circuit unit.
  • It also includes a local clock frequency division circuit, which uses the local clock frequency division to directly generate a recovered clock of the received data, and sends the data synchronized by the bytes and cells to the outside of the synchronous reception circuit.
  • Each of the uplink high-speed serial burst data sampling circuit units is formed by sequentially removing a metastable sampling stage, an adaptation stage that implements data adaptation to a local clock, and a shift stage that implements data synchronization.
  • the selection logic circuit unit includes a timing generator, a first flag register, a second flag register, a first decoding logic circuit, a second decoding logic circuit, a first register, a second register, an adder, and a selection.
  • the timing generator is connected to the first flag register, the second flag register, the first register, the second register and the selector, respectively; the first flag register, the first translation A code logic circuit and a first register are sequentially connected and connected to one end of the adder; the second flag register, a second decoding logic circuit, and a second register are sequentially connected and connected to the other end of the adder; the addition
  • the selector output is connected to the selector; a local clock is connected to the first flag register, the second flag register, the first register, and the second register.
  • the X-phase clock generating circuit unit is implemented by a phase locked loop (PLL) or a digital phase locked loop (DLL).
  • PLL phase locked loop
  • DLL digital phase locked loop
  • the synchronous receiving method and circuit for uplink high-speed data in the optical communication system of the present invention are proposed to solve the shortcomings of the prior art solutions, and are a fast bit synchronous receiving method and circuit for a multi-phase clock.
  • Use a multi-phase (such as 8 to 16-phase) clock to oversample the high-speed uplink burst data first, and after adapting the multi-phase high-speed uplink burst data to the local clock, perform preamble (such as baker code) detection.
  • preamble such as baker code
  • the synchronous receiving method and circuit for uplink high-speed data in the optical communication system of the present invention are: Multi-phase clock fast bit synchronous receiving method and circuit, using multi-phase clock to over-samp arrival data, and then adapt to local clock; using polarity detection circuit to simplify its subsequent circuit; using selection logic circuit to select the location data The data sampled by the center clock; and adding the baker code as the preamble to the high-speed uplink serial burst data; selecting data instead of selecting the clock; and directly dividing the high-speed clock as the byte clock.
  • the method and circuit for fast bit synchronous reception of a multi-phase clock in a communication system of the present invention have the following beneficial effects: the number of clock phases participating in the oversample is large, and the sampling granularity is small , Can effectively track the phase noise of the system (phase error); can reliably and accurately select the clock located in the center of the eye of the received data, to provide the circuit with the maximum time margin; the circuit structure uses a pipeline (line) operation, because there is no The feedback logic greatly improves the operation speed and can meet the high-speed data bit synchronization requirements.
  • the received data is synchronized to the local clock before processing.
  • the circuit is simple and there is no problem of phase jitter. It is not necessary to use a buffer when applied to the system (FIFO) for synchronization, which is convenient for subsequent synchronization control; the circuit can also directly send out the clock divided by the high-speed clock without the glitch problem of clock switching.
  • FIG. 1 is a schematic diagram of 8-phase clock sampling of uplink data.
  • FIG. 3 is a schematic block diagram of a phase clock sampling circuit of the uplink sampling unit in FIG. 2.
  • FIG. 4 is a principle block diagram of a polarity detection circuit in a preamble (baker code) detection circuit unit in FIG. 2.
  • FIG. 5 is a principle block diagram of the selection logic circuit in FIG. 2.
  • W 02
  • the 8-phase clocks ClkO-Clk7 are used to oversample the high-speed serial burst data. It is assumed that the 8-phase clocks Clk0-Clk7 are all sampled correctly. Data, the data sampled by the clock Clk3 or Clk4 located in the middle of the upstream data is selected as the normal received data.
  • Fig. 2 shows the basic principle of the method and the basic structure of the circuit. It mainly includes multi-phase (8-phase) clock generation circuit unit 21, uplink high-speed serial burst data sampling circuit unit 22, baker code (a code in the preamble) detection circuit unit 23, selection logic circuit unit 24, and multi-phase A byte (8-channel) data selection circuit unit 251, a synchronization signal selection circuit unit 252, and a serial-parallel conversion circuit unit 253 are connected to form a byte and cell synchronization unit 25.
  • the circuit is also provided with a clock frequency division circuit 26, the frequency division number of which is related to the number of bits of the serial-parallel conversion circuit unit 253.
  • the multi-phase clock generating circuit unit 21 is used to generate an equal phase difference clock with the same number of phases and the same as the uplink data rate. For example, when the rate of the uplink high-speed serial burst data is 155Mbps, an external clock (155MHz) is input to generate eight The 155MHz clock with the same phase difference has a clock period of 6.4ns, and the phase difference between each adjacent two-phase clock is 1/8 external clock cycles, that is, the phase difference is 0.8ns.
  • the polyphase clock generating circuit unit 21 may be composed of a classic PLL or DLL (Digital Phase Locked Loop). Eight equal phase difference clocks Clk0-Clk7 are output to the upstream high-speed serial burst data sampling circuit unit 22.
  • the upstream high-speed serial burst data sampling circuit unit 22 is composed of eight clock sampling circuits, and uses eight equal phase difference clocks Clk0-Clk7. Data) to perform oversampling to obtain 8-channel serial data, and then adapt the conversion circuit to a 155MHz local clock to facilitate subsequent processing.
  • FIG. 3 shows an uplink high-speed serial burst data sampling circuit unit 22.
  • the principle structure of the 1-channel (phase) clock sampling circuit consists of three stages, which are represented by three dashed boxes, respectively.
  • the first stage 221 is a sampling stage.
  • the upstream high-speed serial burst data (Data) that arrives is oversampled with a one-phase clock from the 8-phase clocks Clk0-Clk7 in a shifting manner to obtain the corresponding clock phase.
  • the implementation circuit of the data can be composed of 3-stage serial registers, which is used to remove the metastable state and eliminate the unstable state of the received signal.
  • the second stage 222 is an adaptation stage (Adopt stage), which is used to adapt the data of eight different clock phases obtained by the eight sampling stages to the main clock or called by CLK3, CLK4, CLK5, CLK6, CLK7 (or directly)
  • the local clock (Mclk, 155MHz) goes up.
  • the third stage is a shift stage 223 (Shift stage), which is used to synchronize the data of the different clock phases that have been adapted to the main clock output from the adaptation stage 222.
  • the shifter is composed of 9 serially connected registers, 8 The lower 8-bit serial data sent by the circuit (phase) shift stage 223 to the corresponding circuit (phase) detection circuit of the preamble (baker code) detection circuit unit 23 respectively, the 8 (phase) shift stage The highest 1-bit data sent by 223 to the data selection circuit unit 251 for data selection, as shown in FIG. 2.
  • the preamble (baker code) detection circuit unit 23 also includes eight (phase) baker code detection circuits for the eight (phase) low 8-bit strings output by the shift stage 223 of the upstream high-speed burst data sampling circuit unit 22, respectively.
  • the preamble detection is performed on the row data to determine whether there is correct data in the 8-channel data.
  • Each (phase) baker code detection circuit consists of a baker code comparison circuit and a data polarity detection circuit.
  • the Bake code comparison circuit compares the incoming phase data with the Baker Code "11100101". As shown in the area except the shade (other data) in the figure, the arrow below the area indicates the comparison process.
  • the initial vector hit is set to "1", if it is not Baker Code, the initial vector hit is set to "0", as shown in the figure, hit 1, hit 8 is “0", and the remaining hit 2-hit 7 is "1" (total 6 "1"), when comparing, if all the bits are the same or there are different bits, it is judged that the baker code is detected.
  • the comparison is performed continuously, as shown in the figure hit 8, hit 1, hit 2 hit 7, hit 8 ....
  • the polarity detection circuit is mainly used to test the rising and falling edges of the uplink data, and use it to replace the entire sampled data and send it to the subsequent circuit for processing, which can greatly reduce the amount of data calculation, simplify the subsequent processing logic, and make the entire
  • the circuit can complete the processing of all 8 channels of data under the high-speed clock of 155MHz.
  • Eight exclusive OR gates (XOR) are used to XOR the comparison results of two adjacent Bake codes respectively, and the operation result "01000001" is sequentially placed in an 8-bit flag and constituted respectively Each bit in this flag has a low bit (LSB) of 0 and a high bit (MSB) of 1.
  • the selection logic circuit unit 24 is configured to perform operation on an 8 ⁇ 8-bit data eye pattern (pattern) sent by the baker code detection circuit unit 23 to calculate which phase clock is located in the middle.
  • the selection logic circuit unit 24 includes a timing generator 241, a flag 242 (a first flag, Flag A) composed of a register logic component, and a flag 243 (a second flag, Flag B), decoding logic 244 (first decoding logic, A), decoding logic 245 (second decoding logic, B), register 246 (first register, A), register 247 (second register, B ), An adder 248 (+), and a selector 249 (SEL) composed of register logic.
  • the selection logic circuit unit 24 decodes the position "a of the first" ⁇ in the flag and the position b of the second " ⁇ in the flag, as shown in the figure.
  • the main consideration of using selection logic is to solve the case where the Baker code crosses the boundary of the main clock cycle when the phase difference is large.
  • the main point in its design is to consider the impact of decoding speed on subsequent byte synchronization.
  • the byte and cell synchronization unit 25 is formed by connecting the data selection circuit unit 251, the synchronization signal selection circuit unit 252, and the serial-parallel conversion circuit unit 253, and is used to complete the selection, synchronization, and serial-parallel conversion of 8 channels of data, and realize the byte and signal Meta sync.
  • the data selection circuit unit 251 selects one of the highest-order data sent from the eight shift stages 223 of the upstream high-speed serial burst data sampling circuit unit 22 under the control of the selection logic circuit unit 24; a synchronization signal selection circuit Unit 252 selects and outputs the eight data from the Baker code detection circuit unit 23 and outputs them synchronously under the control of the selection logic circuit unit 24.
  • the serial-parallel conversion circuit unit 253 controls the clock frequency division circuit 26 and the data selection circuit unit 251. Down, right The 8-channel 8-bit parallel data output by the synchronization signal selection circuit unit 252 performs parallel-to-serial conversion to achieve cell synchronization, and a corresponding byte clock is sent by the clock frequency dividing circuit 26 at the same time.
  • the clock frequency dividing circuit 26 uses the local clock frequency division to directly generate a recovered clock of the received data, and sends it out of the circuit along with the data synchronized by the bytes and cells. Since this implementation circuit is a fairly mature technology in this technical field, it will not be described in detail.
  • the method and circuit of the present invention are verified by the system and prove that the technical solution is feasible and the system works stably at a rate of 155 Mbps.
  • the dynamic range reaches about 30db, which meets the requirements of the G.983.1 standard, and the bit error rate is ⁇ 1 X 10 " 12 survive

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)

Abstract

L'invention concerne un procédé de réception synchrone de données grande vitesse à liaison montante dans un système de communication optique, ainsi que le circuit correspondant. L'invention a pour objet un procédé de réception synchrone de bits rapides d'horloge multiphase, caractérisé en ce qu'il consiste à effectuer un échantillonnage superposé des données à liaison montante reçues par l'horloge à X phases, au moyen d'un circuit d'échantillonnage à liaison montante à X parcours, et à l'adapter à une horloge locale ; à effectuer un examen du code principal aux données à X parcours adaptées à l'horloge locale, au moyen d'une unité de circuit d'examen de code principal, et à sélectionner les données correctes ; à sélectionner les données correctes adoptées par l'horloge située au centre du modèle oculaire, au moyen d'une unité de circuit logique de sélection ; et à réaliser les sélections, la synchronisation et la conversion série-parallèle des données au moyen d'une unité synchrone d'éléments multiplets et d'information.
PCT/CN2002/000204 2001-05-14 2002-03-27 Procede et circuit de reception synchrone de donnees grande vitesse a liaison montante dans un systeme de communication optique WO2002093792A1 (fr)

Applications Claiming Priority (2)

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CN01116057.8 2001-05-14
CNB011160578A CN1161901C (zh) 2001-05-14 2001-05-14 光通信系统中上行高速数据的同步接收方法与电路

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DE102004025109B4 (de) * 2004-05-21 2007-05-03 Infineon Technologies Ag Vorrichtung und Verfahren zur Präambeldetektion und Rahmensynchronisation bei der Datenpaketübertragung
US7606490B2 (en) * 2005-12-01 2009-10-20 Alcatel Lucent Adaptive preamble adjustment for burst-mode optical systems
KR101132321B1 (ko) * 2007-10-05 2012-04-05 바이올린 메모리 인코포레이티드 중간동기식 데이터 버스 장치 및 데이터 전송 방법
CN101801048B (zh) * 2008-11-26 2012-06-06 联发科技股份有限公司 上行链路的传输时序及初始传输超前时序的设定方法
CN102522981B (zh) * 2011-12-28 2014-12-31 成都三零嘉微电子有限公司 一种高速并行接口电路
CN102510328B (zh) * 2011-12-29 2014-10-22 成都三零嘉微电子有限公司 一种高速并行接口电路
CN104735556B (zh) * 2015-03-27 2019-07-05 上海欣诺通信技术有限公司 一种g/epon双模链路放大器及其控制方法
US10142024B2 (en) * 2016-12-14 2018-11-27 Futurewei Technologies, Inc. Higher-level clock and data recovery (CDR) in passive optical networks (PONs)
GB2565006B (en) 2018-11-09 2021-09-08 O2Micro International Ltd Battery protection systems
RU2733923C1 (ru) * 2020-02-20 2020-10-08 Федеральное государственное бюджетное образовательное учреждение высшего образования "Сибирский государственный университет телекоммуникаций и информатики" (СибГУТИ) Метод приема синхронных данных старт-стопным интерфейсом

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CN1207220A (zh) * 1996-01-03 1999-02-03 国际商业机器公司 实现多模式无线光通信的健壮方法和装置
WO1999026364A1 (fr) * 1997-11-18 1999-05-27 International Business Machines Corporation Procede de communication optique sans fil amelioree et trames utilisees dans un systeme de communication optique sans fil

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CN1207220A (zh) * 1996-01-03 1999-02-03 国际商业机器公司 实现多模式无线光通信的健壮方法和装置
WO1999026364A1 (fr) * 1997-11-18 1999-05-27 International Business Machines Corporation Procede de communication optique sans fil amelioree et trames utilisees dans un systeme de communication optique sans fil

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CN1385972A (zh) 2002-12-18
RU2271069C2 (ru) 2006-02-27
RU2003136099A (ru) 2005-05-27

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