WO2002093792A1

WO2002093792A1 - A synchronous receiving method and the circuit of uplink high speed data in optical communication system

Info

Publication number: WO2002093792A1
Application number: PCT/CN2002/000204
Authority: WO
Inventors: Tao Liu
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2001-05-14
Filing date: 2002-03-27
Publication date: 2002-11-21
Also published as: RU2003136099A; CN1161901C; CN1385972A; RU2271069C2

Abstract

The invention relates to a synchronous receiving method of uplink high speed data in optical communication system, and the circuit, the invention is a synchronous receiving method of multiphase clock fast bit. It comprises:oversampling the received uplink data with the X-phase clock by means of the X-path uplink sampling cuicuit, and adapting to local clock; making leading code examination to X-path data adapted on local clock by means of leading code examining circuit unit choosing out the right data; choosing out the right data adopted by the clock locating on the centre of the eye pattern by means of choice logical circuit unit; make choices, synchronization and serial-paralle conversion of data by means of byte and information element synchronous unit.

Description

Method and circuit for synchronously receiving uplink high-speed data in optical communication system

Technical field

The present invention relates to the field of optical communication technology, and more particularly, to a method and a circuit for synchronously receiving uplink high-speed burst data in an optical communication system. Background of the invention

When an ATM passive optical network (A-PON: ATM-Passive Optical Network) communication system uses a high-speed time division multiple access (TDMA-Time: Division Multiple Access) technology, special technology and special methods are required to synchronize uplink data. . For example, each asynchronous transfer mode (ATM: Asynchronous Transfer Mode) cell that arrives at an optical network unit (OLT: Optical Line Terminal) needs to be roughly synchronized by ranging, but at this time, there is still a non-standard between the ATM cell and the cell. For integer bit gaps, bit synchronization is required to align the data and complete byte synchronization and cell synchronization of the data at the same time. This is the problem of fast bit synchronization reception in the present invention; for example, due to the uplink ATM Cells may come from different far ends and are bursts of data, so the synchronization process needs to be performed on a cell-by-cell basis.

In the above-mentioned synchronous receiving process, in order to obtain the maximum time margin, the special method and circuit adopted must locate the sampling clock at the receiving end of the OLT in the middle of the eye diagram of the input data. A commonly used positioning method is to use phase-locked loop (PLL: Phase-Locked Loop) technology. The phase detector first detects the phase of the upstream serial burst data and the rising and falling edges of the sampling clock to generate "up" (rising) and "(1 (^ 1" (falling) pulses. It is sent to a "charge pump" (charge pump), and the output voltage of the charge pump is used to control a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) to generate a clock with an appropriate phase.

The disadvantages of using PLL technology for synchronization are obvious: First, using PLL technology A long hang-up time is required to achieve stable phase lock, and it cannot adapt to the high-speed burst characteristics of the uplink data of the A-PON system. Second, under high-speed conditions, a high-speed uplink serial burst data and sampling is designed. The phase discrimination circuit for phase detection of the clock is more difficult; secondly, it is very difficult to obtain small static phase errors and dynamic phase errors between the sampling clock and the upstream serial burst data, such as processing delay , Synchronization delay, and the non-linear characteristics of the phase detector, it is required to ensure a low loopback bandwidth to maintain stability, but in this case, the circuit cannot track the high-frequency noise.

A more commonly used positioning method is to use a four-phase clock to oversample the high-speed uplink serial burst data. The far end adds a special preamble to the cell header of the transmitted uplink serial data. When the central office receives, if a phase clock samples the correct preamble, it considers that the phase of the clock meets the requirements, and selects the The phase clock is used as the synchronization clock, and then the bit data sampling, byte data conversion, and cell recovery are completed.

The disadvantages of this method are: first, the selected clock is not necessarily located in the middle of the data, and the time margin provided may be small; second, it is difficult to meet the requirements for normal system operation in the case of high-speed applications; second, The phase noise of the system makes it difficult to achieve accurate tracking. Summary of the Invention

The purpose of the present invention is to design a method and a circuit for synchronously receiving uplink high-speed data in an optical communication system, to solve the existing problems of synchronous high-speed serial burst data of the A-PON system in the prior art solution, and It has the advantages of simple structure and easy implementation.

The technical solution to achieve the purpose of the present invention is this: A method for synchronously receiving uplink high-speed data in an optical communication system, which is characterized in that it is a multi-phase clock fast bit synchronous receiving method, including-.

A. Use the X-phase clock to oversample the received uplink high-speed serial burst data separately. Adapt the obtained data of channel X to the local clock, where X is a positive integer;

B. Perform preamble detection on the X-channel data adapted to the local clock to determine the correct data received;

C. Select the correct data sampled by the clock located in the center of the data eye for serial-to-parallel conversion and byte-to-cell synchronization.

The X-phase clock is an 8-phase or 16-phase clock, and adjacent two-phase clocks have the same phase difference of 1 / X clock cycle.

The step A further includes: generating the X-phase data with the same phase data generated by the clock generation circuit and oversampling to obtain X-channel data; adapting the X-channel data to the local clock at a corresponding X-channel adaptation stage; The corresponding X-channel shift stages respectively shift the X-channel data adapted to the local clock to synchronize the X-channel data.

To eliminate unstable receiving signals.

The X-channel data is adapted to the local clock by the corresponding X-channel adaptation stage. The output data of the previous phase clock is sent to the data terminal of the register driven by the subsequent phase clock, and finally sent to the The data side of the local clock driven register is done. Row shifting is performed by shifting the data by a local clock with 8 + 1 stages of serial registers.

The step B further includes: comparing the data of the X channel adapted to the local clock with the preamble, and judging the data of the detected preamble as correct data; performing polarity detection to test the rise and fall of the correct data. Along to replace the data.

The X-channel data adapted to the local clock is compared with the preamble, and if all bits are the same or only one bit is different, it is determined that the preamble is detected, and the number of preambles is detected. It is judged as correct data.

The polarity detection further includes: setting initial vectors hitl to hit8, so that "0" when the comparison result is different and "Γ" when the comparison result is the same respectively indicate the comparison result between the data and the preamble; from low to high, An exclusive-OR operation is performed on the comparison result of two adjacent initial vectors, and the operation result is put into a flag; the low 1 and high 1 of the flag are the rising and falling edges of the correct data, respectively.

The step C further includes: decoding a position a of the low order 1 in the flag by a selection logic circuit unit, decoding a position b of the high order 1 in the flag, and selecting ( a + b) Serial-to-parallel conversion and cell synchronization of the correct data sampled by the / 2-phase clock.

The method further includes directly dividing the local clock to generate the serial-to-parallel clock of the parallel data, and transmitting the data to the synchronization receiving circuit along with the data.

The technical solution for achieving the purpose of the present invention may also be as follows: A synchronous receiving circuit for uplink high-speed data in an optical communication system, which is characterized by including an X-phase clock generating circuit unit and an X-channel uplink high-speed serial burst data sampling circuit. Unit, X-channel preamble detection circuit unit, selection logic circuit unit, and byte and cell synchronization unit composed of X-channel data selection circuit unit, synchronization signal selection circuit unit, and serial-parallel conversion circuit unit connection; said X-phase clock The generating circuit unit is respectively connected to the X-channel uplink high-speed serial burst data sampling circuit unit; the X-channel uplink high-speed serial burst data sampling circuit unit is correspondingly connected to the X-channel preamble detection circuit unit and connected to the X-channel data selection circuit unit in the byte and cell synchronization unit; the X-channel preamble detection circuit unit is connected to the selection logic circuit unit and the synchronization signal selection circuit in the byte and cell synchronization unit, respectively The selection logic circuit unit is respectively connected to the synchronization in the byte and cell synchronization unit No. selection circuit unit and X-channel data selection circuit unit; the X-channel data selection circuit unit and synchronization signal selection circuit unit in the byte and cell synchronization unit are respectively connected to the serial-parallel conversion circuit unit; a local clock connection Number of uplink high-speed serial bursts to X According to the sampling circuit unit and the X-channel preamble detection circuit unit.

It also includes a local clock frequency division circuit, which uses the local clock frequency division to directly generate a recovered clock of the received data, and sends the data synchronized by the bytes and cells to the outside of the synchronous reception circuit.

Each of the uplink high-speed serial burst data sampling circuit units is formed by sequentially removing a metastable sampling stage, an adaptation stage that implements data adaptation to a local clock, and a shift stage that implements data synchronization.

The selection logic circuit unit includes a timing generator, a first flag register, a second flag register, a first decoding logic circuit, a second decoding logic circuit, a first register, a second register, an adder, and a selection. And the timing generator is connected to the first flag register, the second flag register, the first register, the second register and the selector, respectively; the first flag register, the first translation A code logic circuit and a first register are sequentially connected and connected to one end of the adder; the second flag register, a second decoding logic circuit, and a second register are sequentially connected and connected to the other end of the adder; the addition The selector output is connected to the selector; a local clock is connected to the first flag register, the second flag register, the first register, and the second register.

The X-phase clock generating circuit unit is implemented by a phase locked loop (PLL) or a digital phase locked loop (DLL).

The synchronous receiving method and circuit for uplink high-speed data in the optical communication system of the present invention are proposed to solve the shortcomings of the prior art solutions, and are a fast bit synchronous receiving method and circuit for a multi-phase clock. Use a multi-phase (such as 8 to 16-phase) clock to oversample the high-speed uplink burst data first, and after adapting the multi-phase high-speed uplink burst data to the local clock, perform preamble (such as baker code) detection. According to the detection result, the data sampled by the clock located in the middle of the data eye diagram is selected and serial-to-parallel conversion is performed to complete the byte and cell synchronization.

The synchronous receiving method and circuit for uplink high-speed data in the optical communication system of the present invention are: Multi-phase clock fast bit synchronous receiving method and circuit, using multi-phase clock to over-samp arrival data, and then adapt to local clock; using polarity detection circuit to simplify its subsequent circuit; using selection logic circuit to select the location data The data sampled by the center clock; and adding the baker code as the preamble to the high-speed uplink serial burst data; selecting data instead of selecting the clock; and directly dividing the high-speed clock as the byte clock.

Compared with the method for supersampling uplink burst data using a four-phase clock, the method and circuit for fast bit synchronous reception of a multi-phase clock in a communication system of the present invention have the following beneficial effects: the number of clock phases participating in the oversample is large, and the sampling granularity is small , Can effectively track the phase noise of the system (phase error); can reliably and accurately select the clock located in the center of the eye of the received data, to provide the circuit with the maximum time margin; the circuit structure uses a pipeline (line) operation, because there is no The feedback logic greatly improves the operation speed and can meet the high-speed data bit synchronization requirements. The received data is synchronized to the local clock before processing. The circuit is simple and there is no problem of phase jitter. It is not necessary to use a buffer when applied to the system ( FIFO) for synchronization, which is convenient for subsequent synchronization control; the circuit can also directly send out the clock divided by the high-speed clock without the glitch problem of clock switching. Brief description of the drawings

Figure 1 is a schematic diagram of 8-phase clock sampling of uplink data. FIG. 3 is a schematic block diagram of a phase clock sampling circuit of the uplink sampling unit in FIG. 2. FIG. 4 is a principle block diagram of a polarity detection circuit in a preamble (baker code) detection circuit unit in FIG. 2.

FIG. 5 is a principle block diagram of the selection logic circuit in FIG. 2. W 02

Mode of Carrying Out the Invention

The present invention is described in detail below with reference to the drawings.

Referring to Figure 1, the principle of 8-phase clock sampling for uplink data is illustrated. The 8-phase clocks ClkO-Clk7 are used to oversample the high-speed serial burst data. It is assumed that the 8-phase clocks Clk0-Clk7 are all sampled correctly. Data, the data sampled by the clock Clk3 or Clk4 located in the middle of the upstream data is selected as the normal received data.

Referring to Fig. 2, Fig. 2 shows the basic principle of the method and the basic structure of the circuit. It mainly includes multi-phase (8-phase) clock generation circuit unit 21, uplink high-speed serial burst data sampling circuit unit 22, baker code (a code in the preamble) detection circuit unit 23, selection logic circuit unit 24, and multi-phase A byte (8-channel) data selection circuit unit 251, a synchronization signal selection circuit unit 252, and a serial-parallel conversion circuit unit 253 are connected to form a byte and cell synchronization unit 25. The circuit is also provided with a clock frequency division circuit 26, the frequency division number of which is related to the number of bits of the serial-parallel conversion circuit unit 253.

The multi-phase clock generating circuit unit 21 is used to generate an equal phase difference clock with the same number of phases and the same as the uplink data rate. For example, when the rate of the uplink high-speed serial burst data is 155Mbps, an external clock (155MHz) is input to generate eight The 155MHz clock with the same phase difference has a clock period of 6.4ns, and the phase difference between each adjacent two-phase clock is 1/8 external clock cycles, that is, the phase difference is 0.8ns. The polyphase clock generating circuit unit 21 may be composed of a classic PLL or DLL (Digital Phase Locked Loop). Eight equal phase difference clocks Clk0-Clk7 are output to the upstream high-speed serial burst data sampling circuit unit 22.

The upstream high-speed serial burst data sampling circuit unit 22 is composed of eight clock sampling circuits, and uses eight equal phase difference clocks Clk0-Clk7. Data) to perform oversampling to obtain 8-channel serial data, and then adapt the conversion circuit to a 155MHz local clock to facilitate subsequent processing.

Referring to FIG. 3 in combination, the figure shows an uplink high-speed serial burst data sampling circuit unit 22. The principle structure of the 1-channel (phase) clock sampling circuit consists of three stages, which are represented by three dashed boxes, respectively.

The first stage 221 is a sampling stage. The upstream high-speed serial burst data (Data) that arrives is oversampled with a one-phase clock from the 8-phase clocks Clk0-Clk7 in a shifting manner to obtain the corresponding clock phase. The implementation circuit of the data can be composed of 3-stage serial registers, which is used to remove the metastable state and eliminate the unstable state of the received signal.

The second stage 222 is an adaptation stage (Adopt stage), which is used to adapt the data of eight different clock phases obtained by the eight sampling stages to the main clock or called by CLK3, CLK4, CLK5, CLK6, CLK7 (or directly) The local clock (Mclk, 155MHz) goes up.

The adaptation of the master clock is performed according to the following relationship, where-> indicates that the data output by the clock before the arrow is sent to the data terminal of the register driven by the clock after the arrow:

ClkO—> Clk4—> Mclkl55M—> Mclkl55M;

Clkl—> Clk5—> Mclkl55M—> Mclkl55M;

Clk2—> Clk6—> Clk3—> Mclkl55M;

Clk3—> Clk7—> Clk4—> Mclkl55M;

Clk4—> Mclkl55M—> Mclkl55M;

Clk5—> Mclkl55M—> Mclkl55M;

Clk6—> Clk3—> Mclkl55M;

Clk7—> Clk4 -—> Mclkl55M.

From the above relation, it can be known that the data synchronized with the 8-phase clock are all adapted to the main clock or local time 4 (Mclk, 155MHz).

The third stage is a shift stage 223 (Shift stage), which is used to synchronize the data of the different clock phases that have been adapted to the main clock output from the adaptation stage 222. The shifter is composed of 9 serially connected registers, 8 The lower 8-bit serial data sent by the circuit (phase) shift stage 223 to the corresponding circuit (phase) detection circuit of the preamble (baker code) detection circuit unit 23 respectively, the 8 (phase) shift stage The highest 1-bit data sent by 223 to the data selection circuit unit 251 for data selection, as shown in FIG. 2.

The preamble (baker code) detection circuit unit 23 also includes eight (phase) baker code detection circuits for the eight (phase) low 8-bit strings output by the shift stage 223 of the upstream high-speed burst data sampling circuit unit 22, respectively. The preamble detection is performed on the row data to determine whether there is correct data in the 8-channel data. Each (phase) baker code detection circuit consists of a baker code comparison circuit and a data polarity detection circuit.

Refer to FIG. 4 in combination, which shows the detection principle of the baker code detection circuit. The Bake code comparison circuit compares the incoming phase data with the Baker Code "11100101". As shown in the area except the shade (other data) in the figure, the arrow below the area indicates the comparison process. For Baker Code, the The initial vector hit is set to "1", if it is not Baker Code, the initial vector hit is set to "0", as shown in the figure, hit 1, hit 8 is "0", and the remaining hit 2-hit 7 is "1" (total 6 "1"), when comparing, if all the bits are the same or there are different bits, it is judged that the baker code is detected. The comparison is performed continuously, as shown in the figure hit 8, hit 1, hit 2 hit 7, hit 8 ....

The polarity detection circuit is mainly used to test the rising and falling edges of the uplink data, and use it to replace the entire sampled data and send it to the subsequent circuit for processing, which can greatly reduce the amount of data calculation, simplify the subsequent processing logic, and make the entire The circuit can complete the processing of all 8 channels of data under the high-speed clock of 155MHz. Eight exclusive OR gates (XOR) are used to XOR the comparison results of two adjacent Bake codes respectively, and the operation result "01000001" is sequentially placed in an 8-bit flag and constituted respectively Each bit in this flag has a low bit (LSB) of 0 and a high bit (MSB) of 1.

It can be seen from FIG. 4 that through the polarity detection circuit, only two bits of data stored in the flag are “1”, and can replace the 6-bit 'T' in the initial hit vector, so that the subsequent processing circuit Greatly simplified. The selection logic circuit unit 24 is configured to perform operation on an 8 × 8-bit data eye pattern (pattern) sent by the baker code detection circuit unit 23 to calculate which phase clock is located in the middle.

With reference to FIG. 5, the selection logic circuit unit 24 includes a timing generator 241, a flag 242 (a first flag, Flag A) composed of a register logic component, and a flag 243 (a second flag, Flag B), decoding logic 244 (first decoding logic, A), decoding logic 245 (second decoding logic, B), register 246 (first register, A), register 247 (second register, B ), An adder 248 (+), and a selector 249 (SEL) composed of register logic. According to the result of the polarity detection, the selection logic circuit unit 24 decodes the position "a of the first" Γ in the flag and the position b of the second "Γ in the flag, as shown in the figure. Then, after the operation of the adder 248 (+) and the selector 249 (SEL), the middle-phase clock sampled to the Baker code is the (a + b) / 2-phase clock. It can be illustrated with reference to FIG. 4: that the position “a” of the first “1” in the flag (flag) is 2, and the position “b” of the second “Γ in the flag (ag) is 8, then The middle phase clock sampled into the Baker code is the (2 + 8) / 2 = 5 phase clock.

The main consideration of using selection logic is to solve the case where the Baker code crosses the boundary of the main clock cycle when the phase difference is large. The main point in its design is to consider the impact of decoding speed on subsequent byte synchronization.

The byte and cell synchronization unit 25 is formed by connecting the data selection circuit unit 251, the synchronization signal selection circuit unit 252, and the serial-parallel conversion circuit unit 253, and is used to complete the selection, synchronization, and serial-parallel conversion of 8 channels of data, and realize the byte and signal Meta sync. The data selection circuit unit 251 selects one of the highest-order data sent from the eight shift stages 223 of the upstream high-speed serial burst data sampling circuit unit 22 under the control of the selection logic circuit unit 24; a synchronization signal selection circuit Unit 252 selects and outputs the eight data from the Baker code detection circuit unit 23 and outputs them synchronously under the control of the selection logic circuit unit 24. The serial-parallel conversion circuit unit 253 controls the clock frequency division circuit 26 and the data selection circuit unit 251. Down, right The 8-channel 8-bit parallel data output by the synchronization signal selection circuit unit 252 performs parallel-to-serial conversion to achieve cell synchronization, and a corresponding byte clock is sent by the clock frequency dividing circuit 26 at the same time. The clock frequency dividing circuit 26 uses the local clock frequency division to directly generate a recovered clock of the received data, and sends it out of the circuit along with the data synchronized by the bytes and cells. Since this implementation circuit is a fairly mature technology in this technical field, it will not be described in detail.

The method and circuit of the present invention are verified by the system and prove that the technical solution is feasible and the system works stably at a rate of 155 Mbps. The dynamic range reaches about 30db, which meets the requirements of the G.983.1 standard, and the bit error rate is <1 X 10 " ¹² „

Claims

Claim

1. A synchronous receiving method for uplink high-speed data in an optical communication system, which is characterized in that a fast bit synchronous receiving method for a polyphase clock includes:

A. Use the X-phase clock to oversample the received uplink high-speed serial burst data separately, and distribute the obtained X-channel data to the local clock, where X is a positive integer;

2. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 1, characterized in that: the X-phase clock is an 8-phase or 16-phase clock, and two adjacent-phase clocks have Phase difference of the same 1 / X clock cycle.

3. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 1 or 2, characterized in that: said step A, further comprising: generating phase X signals having the same phase difference by a clock generating circuit Clock; the X-phase clock corresponds to the X-channel sampling circuit unit to oversample the upstream high-speed serial burst data to obtain the X-channel data; adapt the X-channel data to the local clock at the corresponding X-channel adaptation stage; The corresponding X-channel shift stages shift the X-channel data adapted to the local clock, respectively, and synchronize the X-channel data.

4. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 3, characterized in that: the X-phase clock corresponds to the X-channel sampling circuit unit to perform uplink high-speed serial burst data, respectively. Oversampling consists of shifting the data with the X-phase clock by the 3-stage serial registers to stabilize the received signal.

5. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 3, characterized in that: the X-channel data is all adapted to the corresponding X-channel adaptation level. The assignment to the local clock is accomplished by sending the output data of the previous phase clock to the data end of the register driven by the latter phase clock, and finally to the data end of the register driven by the local clock.

6. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 3, characterized in that: said X-channel data adapted to a local clock are respectively adapted to corresponding X-channel shift stages. The shifting is performed by shifting the data by a local clock with 8 + 1 stages of serial registers.

7. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 1 or 2, characterized in that: said step B further comprises: separately connecting the X-channel data adapted to the local clock with The preamble comparison judges the data of the detected preamble as the correct data. The polarity detection is performed to test the rising and falling edges of the correct data to replace the data of the channel.

8. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 7, characterized in that: said X-channel data adapted to a local clock is compared with a preamble, all bits The same or only one bit is different, it is judged that the preamble is detected, and the data of the detected preamble is judged as correct data.

9. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 7, characterized in that: said polarity detection further comprises: setting initial vectors hitl to hit8 to compare results at different times. "0" and "1" when the comparison result is the same respectively indicate the comparison result between the data and the preamble; from low to high, XOR operation is performed on the comparison result of two adjacent initial vectors, and the operation result is put into one. In the flag; the low 1 and high 1 in the flag are the rising and falling edges of the correct data, respectively.

10. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 1 or 2 or 9, characterized in that: said step C further comprises: decoding said selection circuit unit by a selection logic circuit unit The position a of the low bit 1 in the flag, decodes the At the position b of the high bit 1 in the flag, select (a + b) the correct data sampled by the 12-phase clock for serial-to-parallel conversion and byte and cell synchronization.

11. The method for synchronously receiving uplink high-speed data in an optical communication system according to claim 1 or 2, further comprising: directly dividing a local clock to generate serial-parallel conversion of the parallel data. The clock and the data are sent out of the synchronous receiving circuit.

12. A synchronous receiving circuit for uplink high-speed data in an optical communication system, comprising: an X-phase clock generating circuit unit, an X-channel uplink high-speed serial burst data sampling circuit unit, an X-channel preamble detection circuit unit, and a selection Logic circuit unit and byte and cell synchronization unit composed of X-channel data selection circuit unit, synchronization signal selection circuit unit, and serial-parallel conversion circuit unit; the X-phase clock generation circuit unit is respectively connected to X-channel uplink high-speed serial Burst data sampling circuit unit; the X-channel uplink high-speed serial burst data sampling circuit unit is respectively connected to the X-channel preamble detection circuit unit and the X-channel data in the byte and cell synchronization unit. A selection circuit unit; the X-channel preamble detection circuit unit is respectively connected to the selection logic circuit unit and a synchronization signal selection circuit unit in the byte and cell synchronization unit; the selection logic circuit units are respectively connected Synchronization signal selection circuit unit and number of X channels in the byte and cell synchronization unit A selection circuit unit; the X-channel data selection circuit unit and the synchronization signal selection circuit unit in the byte and cell synchronization unit are respectively connected to the serial-parallel conversion circuit unit; a local clock is connected to the X-channel uplink high speed Serial burst data sampling circuit unit and X-channel preamble detection circuit unit.

13. The synchronous receiving circuit for uplink high-speed data in an optical communication system according to claim 12, further comprising a local clock frequency dividing circuit, which directly generates a recovered clock for receiving data by using the local clock frequency dividing, and The data synchronized with the byte and the cell is sent out of the synchronization receiving circuit.

14. The synchronous receiving circuit for uplink high-speed data in an optical communication system according to claim 12 or 13, characterized in that: each of the uplink high-speed serial burst data sampling circuit units is removed from a metastable state. The sampling stage, the adaptation stage that implements data and local clock adaptation, and the shift stage that implements data synchronization are sequentially connected.

15. A synchronous receiving circuit for uplink high-speed data in an optical communication system according to claim 12 or 13, characterized in that: said selection logic circuit unit comprises a timing generator, a first flag register, and a second flag A flag register, a first decoding logic circuit, a second decoding logic circuit, a first register, a second register, an adder, and a selector are connected; the timing generator is connected to the first flag register, A second flag register, a first register, a second register, and a selector; the first flag register, the first decoding logic circuit, and the first register are sequentially connected and connected to one end of the adder; the first Two flag registers, a second decoding logic circuit, and a second register are sequentially connected and connected to the other end of the adder; the output of the adder is connected to the selector; a local clock is connected to the first flag register , A second flag register, a first register, and a second register.

16. The synchronous receiving circuit for uplink high-speed data in an optical communication system according to claim 12, wherein: the X-phase clock generating circuit unit is a phase-locked loop

(PLL) or Digital Phase Locked Loop (DLL).