WO2002089202A3 - Herstellungsverfahren für eine integrierte schaltung - Google Patents

Herstellungsverfahren für eine integrierte schaltung Download PDF

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Publication number
WO2002089202A3
WO2002089202A3 PCT/EP2002/004067 EP0204067W WO02089202A3 WO 2002089202 A3 WO2002089202 A3 WO 2002089202A3 EP 0204067 W EP0204067 W EP 0204067W WO 02089202 A3 WO02089202 A3 WO 02089202A3
Authority
WO
WIPO (PCT)
Prior art keywords
gate stack
substrate
gate
upper side
contact hole
Prior art date
Application number
PCT/EP2002/004067
Other languages
English (en)
French (fr)
Other versions
WO2002089202A2 (de
Inventor
Wolfgang Gustin
Kae-Horng Wang
Matthias Kroenke
Original Assignee
Infineon Technologies Ag
Wolfgang Gustin
Kae-Horng Wang
Matthias Kroenke
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Wolfgang Gustin, Kae-Horng Wang, Matthias Kroenke filed Critical Infineon Technologies Ag
Priority to KR1020037014172A priority Critical patent/KR100563789B1/ko
Priority to EP02737948A priority patent/EP1384259A2/de
Priority to US10/476,355 priority patent/US6984578B2/en
Publication of WO2002089202A2 publication Critical patent/WO2002089202A2/de
Publication of WO2002089202A3 publication Critical patent/WO2002089202A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Die vorliegende Erfindung schafft ein Herstellungsverfahren für eine integrierte Schaltung mit den Schritten: Herstellungsverfahren für eine integrierte Schaltung mit den Schritten: Bereitstellen eines Substrats (1) mit mindestens einem ersten, zweiten und dritten auf der Substratoberfläche vorgesehenen, ungefähr gleich hohen Gatestapel (GS1, GS2, GS3), wobei ein gemeinsamer aktiver Bereich (60) an der Substratoberfläche im Substrat (1) zwischen dem ersten und zweiten Gatestapel (GS1, GS2) vorgesehen ist; Vorsehen einer ersten Isolationsschicht (70) zum überdeckenden Einbetten des ersten, zweiten und dritten Gatestapels (GS1, GS2, GS3); Freilegen der Oberseite eines Gateanschlusses (20) des dritten Gatestapels (GS3); Vorsehen einer zweiten Isolationsschicht (80) zum Überdecken der Oberseite eines Gateanschlusses (20); Vorsehen einer Maske (M2) auf der resultierenden Struktur, welche eine erste Öffnung (F2a) oberhalb der freigelegten Oberseite des Gateanschlusses (20) des dritten Gatestapels (GS3), eine zweite Öffnung (F2b) oberhalb des Substrats (1) zwischen dem dritten und dem zweiten Gatestapel (GS3, GS2) und eine dritte Öffnung (F2c) oberhalb des gemeinsamen aktiven Bereichs (60) aufweist, die den ersten und des zweiten Gatestapel (GS1, GS2) teilweise überlappt; und gleichzeitiges Bilden eines ersten, zweiten und dritten Kontaktlochs (KB, KS, KG) durch einen Ätzprozeß unter Verwendung der Maske (M2), wobei das erste Kontaktloch (KB) den gemeinsamen aktiven Bereich (60) an der Substratoberfläche zwischen dem ersten und zweiten Gatestapel (GS1, GS2), das zweite Kontaktloch (KS) die Substratoberfläche zwischen dem zweiten und dritten Gatestapel (GS2, GS2) und das dritte Kontaktloch (KG) die Oberseite des Gateanschlusses (20) des dritten Gatestapels (GS3) freilegt.
PCT/EP2002/004067 2001-04-30 2002-04-11 Herstellungsverfahren für eine integrierte schaltung WO2002089202A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020037014172A KR100563789B1 (ko) 2001-04-30 2002-04-11 집적 회로 제조 방법
EP02737948A EP1384259A2 (de) 2001-04-30 2002-04-11 Herstellungsverfahren für eine integrierte schaltung
US10/476,355 US6984578B2 (en) 2001-04-30 2002-04-11 Method for the production of an integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10120929A DE10120929A1 (de) 2001-04-30 2001-04-30 Herstellungsverfahren für eine integrierte Schaltung
DE10120929.0 2001-04-30

Publications (2)

Publication Number Publication Date
WO2002089202A2 WO2002089202A2 (de) 2002-11-07
WO2002089202A3 true WO2002089202A3 (de) 2003-02-20

Family

ID=7683100

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/004067 WO2002089202A2 (de) 2001-04-30 2002-04-11 Herstellungsverfahren für eine integrierte schaltung

Country Status (6)

Country Link
US (1) US6984578B2 (de)
EP (1) EP1384259A2 (de)
KR (1) KR100563789B1 (de)
DE (1) DE10120929A1 (de)
TW (1) TW571393B (de)
WO (1) WO2002089202A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6903022B2 (en) * 2002-10-03 2005-06-07 Promos Technologies Inc. Method of forming contact hole
DE10326319B3 (de) * 2003-06-11 2004-12-16 Infineon Technologies Ag Verfahren zum Herstellen einer Metellebene auf einer Siliziumscheibe
DE10354421B4 (de) * 2003-11-21 2008-09-25 Infineon Technologies Ag Verfahren zur Herstellung einer Gatekontaktstruktur eines Trench-Hochleistungstransistors und mit diesem Verfahren hergestellter Hochleistungstransistor
DE102004020935B3 (de) * 2004-04-28 2005-09-01 Infineon Technologies Ag Verfahren zum Herstellen einer ersten Kontaktlochebene in einem Speicherbaustein

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104052A (en) * 1998-03-30 2000-08-15 Kabushiki Kaisha Toshiba Semiconductor device adopting a self-aligned contact structure and method for manufacturing a semiconductor memory device
US6207571B1 (en) * 1997-08-20 2001-03-27 Micron Technology, Inc. Self-aligned contact formation for semiconductor devices
US6337278B1 (en) * 2000-08-23 2002-01-08 Mosel Vitelic, Inc. Technique for forming a borderless overlapping gate and diffusion contact structure in integrated circuit device processing

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206187A (en) * 1991-08-30 1993-04-27 Micron Technology, Inc. Method of processing semiconductor wafers using a contact etch stop
JP2765478B2 (ja) * 1994-03-30 1998-06-18 日本電気株式会社 半導体装置およびその製造方法
US5498570A (en) * 1994-09-15 1996-03-12 Micron Technology Inc. Method of reducing overetch during the formation of a semiconductor device
US5763910A (en) * 1995-01-31 1998-06-09 Fujitsu Limited Semiconductor device having a through-hole formed on diffused layer by self-alignment
JP2000058480A (ja) * 1998-08-07 2000-02-25 Mitsubishi Electric Corp 半導体装置の製造方法
JP2000077625A (ja) * 1998-08-31 2000-03-14 Hitachi Ltd 半導体集積回路装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6207571B1 (en) * 1997-08-20 2001-03-27 Micron Technology, Inc. Self-aligned contact formation for semiconductor devices
US6104052A (en) * 1998-03-30 2000-08-15 Kabushiki Kaisha Toshiba Semiconductor device adopting a self-aligned contact structure and method for manufacturing a semiconductor memory device
US6337278B1 (en) * 2000-08-23 2002-01-08 Mosel Vitelic, Inc. Technique for forming a borderless overlapping gate and diffusion contact structure in integrated circuit device processing

Also Published As

Publication number Publication date
KR20040015210A (ko) 2004-02-18
WO2002089202A2 (de) 2002-11-07
EP1384259A2 (de) 2004-01-28
TW571393B (en) 2004-01-11
US6984578B2 (en) 2006-01-10
US20040147107A1 (en) 2004-07-29
KR100563789B1 (ko) 2006-03-27
DE10120929A1 (de) 2002-10-31

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