WO2002073411A1 - Procede de test de memoire, support d'enregistrement d'information et circuit integre semi-conducteur - Google Patents

Procede de test de memoire, support d'enregistrement d'information et circuit integre semi-conducteur Download PDF

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Publication number
WO2002073411A1
WO2002073411A1 PCT/JP2002/001467 JP0201467W WO02073411A1 WO 2002073411 A1 WO2002073411 A1 WO 2002073411A1 JP 0201467 W JP0201467 W JP 0201467W WO 02073411 A1 WO02073411 A1 WO 02073411A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
instruction
test
cpu
bus
Prior art date
Application number
PCT/JP2002/001467
Other languages
English (en)
Japanese (ja)
Inventor
Tatsuya Kamei
Saneaki Tamaki
Hisayoshi Ide
Ken Tatezawa
Haruo Ii
Original Assignee
Hitachi, Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd filed Critical Hitachi, Ltd
Priority to JP2002572003A priority Critical patent/JP4015025B2/ja
Publication of WO2002073411A1 publication Critical patent/WO2002073411A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Definitions

  • the memory test program executes certain operations such as memory read / write by changing only the address and over the entire memory area, it is necessary to use a loop-type program.
  • This requires a branch instruction to execute, and this also reduces the ratio of read / write instructions.
  • the branch instruction itself requires multiple execution cycles, The number of cycles required for the test increases more than the number of instructions increases.
  • FIG. 16 is an explanatory diagram showing a method of a 13N test which is one of the test sequences of the on-chip memory.
  • the DSP 104 uses the XY memory 108 connected by the XY bus 109 for digital signal processing operations that perform a variety of product-sum operations.
  • the memory 106 is stored outside the chip: temporarily stores the programs that are used relatively frequently among the programs stored in the OM 131, RAM 132, etc. deep.
  • the general-purpose memory 107 is used as a work area of the CPU 102 or a temporary storage area for data storage.
  • the BIST module 110 is a test circuit used for testing on-chip memory.
  • the overnight write operation to the fuse circuit 1 The write data from the module 110 is performed according to an instruction from the fuse control terminal 117 of the chip (generally from a test at the time of a test before shipment).
  • the fuse circuit 115 is a nonvolatile memory, and in this embodiment, is configured by a small-capacity flash memory.
  • Address registers (BI STF AR 0, BISTF AR 1, BISTF AR 2) 302 are 32-bit registers each. General-purpose memory can rescue each page, and it is necessary to hold up to four error addresses. There are four available.
  • a fuse address register (BI STFDR) 303 is a 32-bit register for holding data to be written to the fuse circuit 115. Data is automatically generated by the rescue judging unit 254 based on an error address.
  • FIG. 5 illustrates the configuration of one page of the memory 108 as a representative of the general-purpose memory 107 and the memory 108 to be subjected to the memory test.
  • 0xA5600000 to 0xA57 FFF This is an address bit that determines whether the upper half or lower half of the FF area.
  • ENOR (exclusive (Negative OR gate) 480 works as a receiver, and enable signal of each page (UPAGE 0LEN) 470, (UP AGE 0 HEN) 471, (UP AGE 1 LEN) 472 (UP AGE 1 HEN) 473 Is exclusively asserted.
  • E NOR 480 acts as a buffer, and the enable signal of each page only when address bits A21 and A15 are both “0” and UMEMEN is “1”. 473 are asserted in parallel, and when the address is in any other condition, the operation is performed such that all enable signals 470-473 are negated regardless of UME MENU.
  • the instruction queue 103 has, for example, an instruction buffer 103 BF having a 12-stage buffer area, a read pointer 103 RP for operating the instruction buffer 103 BF at FIF 0 and a write pointer 103 WP. .
  • the read pointer 103 RP is a loop counter for designating a buffer area for performing a read operation, and has a count value CNTRJ of # 0 to # 11.
  • the write pointer 103WP is a loop counter for designating a buffer area for performing a write operation, and the count value CNTW is set to # 0 to # 11.
  • the read pointer 103 RP and the write pointer 103 WP start and end each time a write operation is performed based on the initial value.
  • CD-R Compact Disk-Recordable
  • CR-W Compact Disk-Rewritable
  • DVD-ROM Digital Video Disk-Read Only Memory
  • DVD-RAM Digital Video Disk-Random Access Memory
  • FD Freloppy Disk
  • the instruction queue is operated as a loop queue, it is not necessary to use a branch instruction to enable the same test program to be repeatedly executed. Then, the test program to be repeatedly executed may be repeatedly fetched from the instruction queue, and the memory read / write access for the memory test and the memory access for the instruction fetch do not conflict on the bus. Therefore, it is possible to eliminate the branch instruction from the test program, and it is not necessary to repeatedly fetch the same instruction from the bus connected to the CPU, thereby improving the test efficiency of the on-chip memory of the semiconductor integrated circuit. Becomes possible.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un procédé de test d'une mémoire d'un circuit intégré semi-conducteur contenant une UC (102) dotée d'une file d'attente d'instructions (103), de mémoires (107, 108) et d'un bus (105) permettant de connecter l'UC aux mémoires, dans lequel un programme de test est stocké dans la file d'attente d'instructions, l'UC exécutant le programme de test afin de réaliser un accès mémoire via le bus, le programme de test étant appelé de façon répétée à partir de la file d'attente d'instructions sans passer par le bus après stockage du programme dans la file d'attente d'instructions. Le traitement de la file d'attente en boucle de la liste d'attente d'instructions dispense de toute instruction de branchement permettant une exécution répétitive du même programme de test. Tout ce qui doit être fait consiste en l'appel répétitif d'un programme de test qui doit être exécuté de façon répétitive à partir de la file d'attente d'instructions et, par conséquent, un accès écriture/lecture en mémoire pour un test mémoire ne rentre pas en compétition sur le bus avec un accès mémoire pour appeler une instruction. Il en résulte une amélioration de l'efficacité de test d'une mémoire sur puce dans un circuit intégré semi-conducteur.
PCT/JP2002/001467 2001-02-22 2002-02-20 Procede de test de memoire, support d'enregistrement d'information et circuit integre semi-conducteur WO2002073411A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002572003A JP4015025B2 (ja) 2001-02-22 2002-02-20 メモリテスト方法、情報記録媒体及び半導体集積回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001046218 2001-02-22
JP2001-46218 2001-02-22

Publications (1)

Publication Number Publication Date
WO2002073411A1 true WO2002073411A1 (fr) 2002-09-19

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Country Status (3)

Country Link
JP (1) JP4015025B2 (fr)
TW (1) TW591378B (fr)
WO (1) WO2002073411A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005050329A (ja) * 2003-07-11 2005-02-24 Yogitech Spa 信頼性マイクロコントローラ、マイクロコントローラにおける欠陥検出方法、マイクロコントローラ用欠陥許容システム設計方法、およびコンピュータプログラム製品
US8117573B2 (en) 2007-10-10 2012-02-14 Fujitsu Limited Verification-scenario generating apparatus, verification-scenario generating method, and computer product
JP2016081276A (ja) * 2014-10-16 2016-05-16 富士通株式会社 情報処理装置および情報処理装置の制御方法
CN110275818A (zh) * 2018-03-13 2019-09-24 龙芯中科技术有限公司 测试程序生成方法、装置及存储介质
CN112242177A (zh) * 2019-07-16 2021-01-19 北京地平线机器人技术研发有限公司 存储器测试方法、装置、计算机可读存储介质及电子设备
CN112363875A (zh) * 2020-10-21 2021-02-12 海光信息技术股份有限公司 一种系统缺陷检测方法、设备、电子设备和存储介质
CN115656788A (zh) * 2022-12-23 2023-01-31 南京芯驰半导体科技有限公司 一种芯片测试系统、方法、设备及存储介质

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101212748B1 (ko) * 2010-10-29 2012-12-14 에스케이하이닉스 주식회사 반도체 메모리, 메모리 시스템 및 그 프로그래밍 방법
KR102002753B1 (ko) * 2019-03-15 2019-07-23 호서대학교 산학협력단 메모리를 테스트하기 위한 인터페이스 카드
US11961258B2 (en) 2022-01-26 2024-04-16 Industrial Technology Research Institute Calibration method for optical see-through display and calibration system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5644942A (en) * 1979-09-19 1981-04-24 Hitachi Ltd Information processing unit
JPH07160585A (ja) * 1993-12-13 1995-06-23 Hitachi Ltd 低電力データ処理装置
JPH10511790A (ja) * 1995-06-16 1998-11-10 エロネックス・ソフトウェア・ソリューションズ・インコーポレーテッド Ｃｐｕキャッシュと命令ユニットの並列試験

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5644942A (en) * 1979-09-19 1981-04-24 Hitachi Ltd Information processing unit
JPH07160585A (ja) * 1993-12-13 1995-06-23 Hitachi Ltd 低電力データ処理装置
JPH10511790A (ja) * 1995-06-16 1998-11-10 エロネックス・ソフトウェア・ソリューションズ・インコーポレーテッド Ｃｐｕキャッシュと命令ユニットの並列試験

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005050329A (ja) * 2003-07-11 2005-02-24 Yogitech Spa 信頼性マイクロコントローラ、マイクロコントローラにおける欠陥検出方法、マイクロコントローラ用欠陥許容システム設計方法、およびコンピュータプログラム製品
US8117573B2 (en) 2007-10-10 2012-02-14 Fujitsu Limited Verification-scenario generating apparatus, verification-scenario generating method, and computer product
JP2016081276A (ja) * 2014-10-16 2016-05-16 富士通株式会社 情報処理装置および情報処理装置の制御方法
US9645818B2 (en) 2014-10-16 2017-05-09 Fujitsu Limited Information processing apparatus and control method of information processing apparatus
CN110275818A (zh) * 2018-03-13 2019-09-24 龙芯中科技术有限公司 测试程序生成方法、装置及存储介质
CN110275818B (zh) * 2018-03-13 2024-04-30 龙芯中科技术股份有限公司 硅后验证方法、装置及存储介质
CN112242177A (zh) * 2019-07-16 2021-01-19 北京地平线机器人技术研发有限公司 存储器测试方法、装置、计算机可读存储介质及电子设备
CN112363875A (zh) * 2020-10-21 2021-02-12 海光信息技术股份有限公司 一种系统缺陷检测方法、设备、电子设备和存储介质
CN112363875B (zh) * 2020-10-21 2023-04-07 海光信息技术股份有限公司 一种系统缺陷检测方法、设备、电子设备和存储介质
CN115656788A (zh) * 2022-12-23 2023-01-31 南京芯驰半导体科技有限公司 一种芯片测试系统、方法、设备及存储介质

Also Published As

Publication number Publication date
JP4015025B2 (ja) 2007-11-28
JPWO2002073411A1 (ja) 2004-07-02
TW591378B (en) 2004-06-11

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