WO2002063690A1 - Dispositif de circuit integre a semi-conducteur et son procede de fabrication - Google Patents
Dispositif de circuit integre a semi-conducteur et son procede de fabrication Download PDFInfo
- Publication number
- WO2002063690A1 WO2002063690A1 PCT/JP2001/010082 JP0110082W WO02063690A1 WO 2002063690 A1 WO2002063690 A1 WO 2002063690A1 JP 0110082 W JP0110082 W JP 0110082W WO 02063690 A1 WO02063690 A1 WO 02063690A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- reduce
- oxide film
- isolation groove
- element isolation
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002563535A JPWO2002063690A1 (ja) | 2001-02-08 | 2001-11-19 | 半導体集積回路装置およびその製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001031776 | 2001-02-08 | ||
JP2001-31776 | 2001-02-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002063690A1 true WO2002063690A1 (fr) | 2002-08-15 |
Family
ID=18895808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/010082 WO2002063690A1 (fr) | 2001-02-08 | 2001-11-19 | Dispositif de circuit integre a semi-conducteur et son procede de fabrication |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPWO2002063690A1 (ja) |
TW (1) | TW518710B (ja) |
WO (1) | WO2002063690A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005294791A (ja) * | 2004-03-09 | 2005-10-20 | Nec Corp | 不揮発性メモリ及び不揮発性メモリの製造方法 |
US7084477B2 (en) | 2002-06-24 | 2006-08-01 | Hitachi, Ltd. | Semiconductor device and manufacturing method of the same |
JP2010283199A (ja) * | 2009-06-05 | 2010-12-16 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8778717B2 (en) * | 2010-03-17 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Local oxidation of silicon processes with reduced lateral oxidation |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5925908A (en) * | 1997-07-30 | 1999-07-20 | Motorola, Inc. | Integrated circuit including a non-volatile memory device and a semiconductor device |
JPH11317508A (ja) * | 1998-05-06 | 1999-11-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH11340313A (ja) * | 1998-05-07 | 1999-12-10 | Samsung Electronics Co Ltd | トレンチ隔離形成方法 |
JP2000036535A (ja) * | 1998-04-27 | 2000-02-02 | Samsung Electronics Co Ltd | トレンチ隔離形成方法 |
JP2000150833A (ja) * | 1998-11-11 | 2000-05-30 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
-
2001
- 2001-11-19 JP JP2002563535A patent/JPWO2002063690A1/ja active Pending
- 2001-11-19 WO PCT/JP2001/010082 patent/WO2002063690A1/ja active Application Filing
- 2001-12-24 TW TW090132035A patent/TW518710B/zh not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5925908A (en) * | 1997-07-30 | 1999-07-20 | Motorola, Inc. | Integrated circuit including a non-volatile memory device and a semiconductor device |
JP2000036535A (ja) * | 1998-04-27 | 2000-02-02 | Samsung Electronics Co Ltd | トレンチ隔離形成方法 |
JPH11317508A (ja) * | 1998-05-06 | 1999-11-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JPH11340313A (ja) * | 1998-05-07 | 1999-12-10 | Samsung Electronics Co Ltd | トレンチ隔離形成方法 |
JP2000150833A (ja) * | 1998-11-11 | 2000-05-30 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7084477B2 (en) | 2002-06-24 | 2006-08-01 | Hitachi, Ltd. | Semiconductor device and manufacturing method of the same |
JP2005294791A (ja) * | 2004-03-09 | 2005-10-20 | Nec Corp | 不揮発性メモリ及び不揮発性メモリの製造方法 |
JP2010283199A (ja) * | 2009-06-05 | 2010-12-16 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW518710B (en) | 2003-01-21 |
JPWO2002063690A1 (ja) | 2004-06-10 |
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