WO2002059902A1 - Procede de production d'un dispositif a semi-conducteur et dispositif a semi-conducteur ainsi obtenu - Google Patents

Procede de production d'un dispositif a semi-conducteur et dispositif a semi-conducteur ainsi obtenu Download PDF

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Publication number
WO2002059902A1
WO2002059902A1 PCT/JP2001/009245 JP0109245W WO02059902A1 WO 2002059902 A1 WO2002059902 A1 WO 2002059902A1 JP 0109245 W JP0109245 W JP 0109245W WO 02059902 A1 WO02059902 A1 WO 02059902A1
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WIPO (PCT)
Prior art keywords
circuit
memory
semiconductor device
test
fuse
Prior art date
Application number
PCT/JP2001/009245
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English (en)
Japanese (ja)
Inventor
Hideki Hayashi
Keiichi Higeta
Shigeru Nakahara
Takashi Koba
Naomi Ohshima
Original Assignee
Hitachi, Ltd.
Hitachi Ulsi Systems Co., Ltd.
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Application filed by Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd. filed Critical Hitachi, Ltd.
Priority to JP2002560140A priority Critical patent/JPWO2002059902A1/ja
Publication of WO2002059902A1 publication Critical patent/WO2002059902A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a technology that is effective when applied to a technology for repairing and manufacturing a defective memory cell of a semiconductor device having a plurality of memories.
  • an object of the present invention to provide a semiconductor device having a simplified manufacturing process for a semiconductor device having a memory circuit and a logic circuit such as a RAM, and a method of manufacturing the same. It is another object of the present invention to provide a semiconductor device and a method of manufacturing the same, which efficiently and rationally remedy a defective bit of a memory circuit.
  • a test of the memory portion is performed in a first step, and a defect is found in the memory portion in a second step.
  • the defect information of the memory cell is held in a register.
  • the logic section is tested in the state where the defect information is held in the register, and after the first to third steps, Based on the defect information held in the register in the fourth step, a fuse circuit that holds the defect information is set.
  • Logic using data stored in a memory unit having a plurality of memory cells In a semiconductor device that performs signal processing in a memory section, a test pattern generation circuit that tests the memory section and the logic section, and a memory test that performs a relief analysis corresponding to the test result of the memory section by the test pattern generation circuit A circuit, and a fuse circuit for storing defect information formed by the memory test circuit, wherein the memory section has defect information set in the fuse circuit and a defect formed by the memory test circuit.
  • a rescue address register for selectively inputting information and a redundancy circuit for selecting a substitute memory cell instead of a defective memory cell corresponding to the rescue address of the rescue address register are provided.
  • FIG. 1 is a block diagram showing one embodiment of a semiconductor device according to the present invention
  • FIG. 2 is a flow chart showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.
  • FIG. 3 is a schematic overall block diagram showing one embodiment of a semiconductor device to which the present invention is applied.
  • FIG. 4 is a schematic configuration diagram of a semiconductor device to which the present invention is applied.
  • FIG. 5 is a configuration diagram of a shift register included in the setting circuit 10 of FIG.
  • FIG. 6 is a bit configuration diagram for explaining the shift register of FIG. 5,
  • FIG. 7 is a specific circuit diagram showing one embodiment of flip-flops FZF1 to FZF13 with a built-in fuse constituting the setting circuit 10 having the shift register function of FIG.
  • FIG. 8 is a timing chart for explaining the operation of the flip-flop shown in FIG. FIG.
  • FIG. 9 is a timing diagram for explaining the operation of the memory diagnostic controller of FIG.
  • FIG. 10 is a block diagram showing one embodiment of the RAM macro cell of FIG.
  • FIG. 11 is a block diagram showing one embodiment of a RAM core of the RAM macro cell of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a block diagram of an embodiment of the semiconductor device according to the present invention.
  • This embodiment is directed to a large-scale semiconductor device such as a computer processor equipped with a logic circuit and a memory circuit.
  • a large number of large-scale integrated circuits (LSI) with multiple memories on a single semiconductor chip have come to be seen.
  • LSI large-scale integrated circuits
  • a processor for a computer a large number of RAMs such as a large-capacity primary cache, a secondary cache, a translation look-aside buffer (TLB), a tag, a branch prediction memory, and a write buffer are provided.
  • TLB translation look-aside buffer
  • tag a branch prediction memory
  • write buffer Built-in RAM power is provided.
  • the built-in RAM 200 of this embodiment includes an address selection circuit 211, 215, a regular memory array 2 13 and a spare memory cell, as schematically shown in FIG.
  • the memory section is composed of a redundant circuit 214 provided with power and a data input / output circuit 216.
  • a switching circuit 270 is provided for the address AD, the data DI, and the read Z write control signal WE.
  • the built-in RAM 200 is selectively input with the input signal during normal operation formed by the logic circuit 301 and the test signal during test operation formed by the test pattern generation circuit 400. I can do it.
  • a comparison / determination circuit 220 comparing the RAM output signal DO and the input expected value to the memory unit 210, and a determination signal of the comparison / determination circuit 220 and an address signal AD are provided.
  • R comprising a rescue analysis circuit 230 received, a judgment register 240 receiving the output signal of the comparison judgment circuit 220, and a redress address register 250 receiving the output signal of the rescue analysis circuit 230 AM—BIST power provided and built-in R AM 200 power configuration.
  • a redundancy circuit for replacing a defective memory cell of the regular array 21 with a spare memory cell 214 is provided for each of the plurality of RAMs 210, and a fuse circuit 5 commonly provided for a plurality of internal RAMs is provided.
  • the fuse information receiving circuit 290 receives the defect information from 0 0, and takes in and holds a repair address for enabling the redundant circuit 2 14.
  • a program element e.g., a flash memory
  • a relief address setting circuit that includes the above-mentioned configuration causes an enormous number of program elements alone, which causes an increase in chip size.
  • a fuse circuit 500 for setting a relief address is provided. Because the number of program elements can be reduced, the total number of program elements can be reduced and the chip size can be reduced.
  • the built-in RAM 200 is provided between the logic circuits 301 and 302 in order to speed up the operation. That is, memory access is performed by an address signal and a control signal formed by the logic circuit 301, and the read data is logically processed as an input signal of the logic circuit 302 of the next stage.
  • the logic circuit 301 outputs a signal for memory access in synchronization with a system clock signal, and transmits it to the built-in RAM.
  • the built-in RAM 200 forms an output signal D0 in response to the input signal. This output signal D ⁇ is used as an input signal of the next-stage logic circuit 302 to perform logic processing.
  • the sequence operation of a logic circuit is performed in synchronization with a clock signal.
  • a logic stage is inserted between two flip-flop circuits that fetch a signal in synchronization with a clock signal, and an operation sequence in the logic stage is executed in synchronization with the clock signal.
  • the signal propagation delay time in the above logic stage be shorter than one clock cycle (one machine cycle). If a RAM is incorporated in such a logic stage, it becomes possible to determine, for example, a hit / miss hit of a cache in one machine cycle.
  • the register 26 for taking in the defective address through the switching circuit 280 which is switched by the relief address force switching control formed by the RAM-BIST in such a test operation without going to the fuse processing step after performing the fuse processing. Conveyed to 0.
  • the remedy can be performed and checked immediately after the test force of the memory unit 210 is performed. For this reason, it is possible to carry out a comprehensive circuit test combining the memory section 210 and the logic circuits 301 and 302 following the internal RAM test.
  • the register 260 captures defective address information from the fuse information receiving circuit 290 by the switching circuit 280 during normal operation.
  • FIG. 2 is a flowchart showing one embodiment of the method of manufacturing a semiconductor device according to the present invention. The figure shows the wafer probing process from completion of the circuit on the wafer to assembly.
  • step (1) the ram test force is implemented. That is, when the circuit is completed on the wafer, the RAM test force is performed.
  • the switching circuit 270 is switched to the test pattern generation circuit side by the system Z test switching signal shown in Fig. 1, and the RAM address AD, data input DI and read / write control are performed. Supply the signal WE to write and read data at the specified time.
  • the read data and the expected value are transmitted to the RAM-BIST comparison / determination circuit 220, and the match Z mismatch is determined.
  • step (2) the RAM read data DO Since the expected value is input from the test pattern generation circuit, the judgment of the comparison judgment circuit 220 is performed.
  • the determination result is transmitted to the address rescue analysis circuit 230, and based on the previous failure information stored in the determination register, whether to perform X address rescue, Y address rescue, or A determination is made as to whether the rescue is impossible. If the remedy is edible, it is stored in the rescue addressless address register 250.
  • the repair cannot be performed by the redundant circuit 214, such a chip is determined to be defective. If the semiconductor device has no defect in the built-in RAM, shift to the logic test in step (6).
  • step (3) a relief operation is performed. That is, the switching circuit 280 sets the rescue address stored in the rescue address register 250 in the register 260 by the switching control. As a result, the address selection circuits 2 11 and 2 15 select spare memory cells of the redundant circuit 2 14 instead of the defective memory cells of the normal circuit 2 13.
  • step (4) a RAM test including the above rescue operation is performed.
  • step (5) the judgment is made, and if a defect occurs, that is, if remedy is not possible, the chip is determined to be defective. If the defective bit in the RAM has been remedied, the logic test in step (6) is performed as a good product.
  • the logic test of the step (6) a test of a circuit function including the RAM incorporated in the logic circuit is performed. That is, the circuit verification power is implemented in accordance with the actual operation corresponding to the test pattern formed by the test pattern generation circuit 400.
  • the above manufacturing steps (1) to (7) are performed in one wafer probing step.
  • a chip which is determined to be a non-defective product by each of the steps (1) to (7) is subjected to the following fuse processing step.
  • this fuse processing step in step (8), if there is no defect in the RAM, it is determined that processing is unnecessary, and there is a method that relieves the defective bit of the RAM.
  • the fuse processing of step (9) is performed. That is, the selective cutting of the fuse circuit 500 is performed by the selective irradiation of one laser beam or the like. Then, the wafers are divided for each chip, and only those that do not require fuse processing or those that have undergone fuse processing are assembled in the assembly process.
  • the RAM 210 receives a memory cell array having a redundant circuit 214 as a repair area for repairing a defect, a memory cell array, and an address and a repair address, and inputs the memory cell arrays 2 13 and 2 14 Address selection circuits 211 and 215 having a function of selecting one memory cell from the above and a circuit 216 for writing / reading the selected memory cell.
  • a plurality of RAMs having the above-described defect relief function are provided in one LSI.
  • a test is performed on the RAM, and the RAM-BIST circuit has a function of seeking a repair address when there is a defect.
  • a register 250 for storing the rescue address calculated by RAM-BIST is set for each RAM.
  • a fuse circuit that can change the power signal value by a method such as laser processing in order to input the RAM defect relief address to the LSI.
  • a communication means is provided for distributing fuse information from the fuse circuit 500 to a plurality of RAMs.
  • the fuse circuit 500 and the built-in RAM 200 are connected by a communication bus wiring 600, and the fuse information receiving circuit 290 sends the fuse information to [Destination RAM number] + [Rescue].
  • [Relief address] is received as the packet information of [Address].
  • a register 260 for storing information distributed by the communication bus wiring 600 is provided for each RAM. The value of this register 260 is input to the address selection circuit 211.215 as a "rescue address". The value of the calculated rescue address register supplied to the register 260 may be arbitrarily set to the “replacement” of the information from the fuse circuit 500 0 instead of the rescue address of the RAM—BIST rescue address register 250.
  • a switching circuit 280 is provided. Switching control for selecting which information is stored is performed by a RAM-BIST control circuit. During normal (user) use, fuse information transferred from the fuse circuit 500 is stored in the register 280, and this is used as a RAM defect repair address for RAM operation.
  • the above switching control makes it possible to use the RAM defect rescue address obtained from the RAM-BIST circuit power in place of the fuse information.
  • the 1st P inspection development inspection
  • the RAM-BIST calculates the RAM defect relief address (this data is processed into fuses) Later, you can use the data as it is to see if the RAM is actually rescued.
  • the failure rate of the fuse process is so small as to be negligible in practice, it is estimated to be a good product in the probing process (the LSI that could be fully tested with the RAM defect repair address calculated by the RAM-BIST force). Can be expected to become a completely non-defective product by adding a fuse, and it is possible to proceed to the next process (assembly) without performing the second probing inspection after fuse processing.
  • two registers 250 and 260 are provided to confirm the RAM rescue effect before fuse processing.
  • the rescue address register 250 is necessary and necessary for calculating the RAM rescue method, that is, the rescue address for rescue RAM.
  • the contents of the register 260 fuse information are input as a RAM repair address.
  • two registers that can be shared at first glance are provided independently.
  • registers 250 and 260 are shared, the RAM relief information will be rewritten during RAM test by RAM-BIST. If the RAM rescue operation is slower than the RAM test operation speed, the RAM rescue operation during the test may cause the RAM to malfunction and correct results may not be obtained. If there are more than two types of RAM rescue methods, for example, if it is possible to rescue the X system and the Y system, it is better to rescue using the X or Y rescue method when the first defect is found. In some cases, it cannot be determined. If registers 250 and 260 are shared, the correct remedy method may not be selectable.
  • the RAM can be fully operated in the first P detection process.
  • the RAM is fully operating, and it is possible to evaluate items that cannot be tested unless the RAM operates, at the time of the first P inspection.
  • This is one of the objects of the present invention.
  • a logical operation test of the LSI as described above.
  • the logical operation test of the LSI is based on the model that the RAM assumes in the logical operation test of the LSI. If it does not work, the test will not pass. For this reason, the RAM before remedy may not operate as expected in the logic operation test of the LSI. Therefore, until the RAM is remedied, pass / fail cannot be determined by the logic operation test of the LSI.
  • the RAM has a defect in the power logic that can be rescued, and many chips cannot be shipped.
  • the cost of the fuse processing is wasteful. According to the present invention, it is possible to eliminate such waste in the process of applying the fuse. In other words, in the present embodiment, in the first P detection process, the RAM is completely operated by the rescue, so that all the test items including the logic operation test can be performed. Useless processing of non-equipment is eliminated.
  • FIG. 3 is a schematic overall block diagram of an embodiment of a semiconductor device to which the present invention is applied.
  • an identification code (ID code) is given in advance to each of a plurality of memory blocks MCL1, MCL2,. Comparator that compares the ID and the input identification code (RAM-ID) When the identification code matches the CMP, the latch circuit or latch circuit that latches the input information such as the address (Data) and the LTC is provided. It is possible.
  • This configuration corresponds to the fuse information receiving circuit I 90 for receiving a defective address from the fuse circuit 500 of FIG. 1 and the register 260.
  • MC Ln are provided in a location different from the memory block, and a relief address (Data 0 to Data M) and 3 ⁇ 4: identification for specifying a memory block to be completed
  • a setting circuit 10 for setting codes (RAM—IDO to RAM_IDM) in pairs and a memory diagnostic controller 20 as a control circuit for controlling the setting circuit 10 are provided.
  • the setting circuit 10 includes a fuse array F—ALY 11 in which fuses as externally programmable program elements are arranged and a shift register SFT for reading the state of each fuse and serially transferring the fuse state. It consists of. Then, the memory diagnostic controller 20 reads the setting information from the setting circuit 10 serially via the serial bus SBUS, converts it into parallel data, and converts it into parallel data via the memory controller port 30 as a parallel bus.
  • the memory blocks MCL1, MCL2 are supplied to MCLn, and the relief address is automatically latched.
  • the setting circuit 10 and the memory diagnostic controller 20 there is a selector SEL input for supplying either the data F DAT A from the setting circuit 10 or the data DAT A from an external terminal to the memory diagnostic controller. Have been killed. As a result, if a new defective bit occurs in any of the memory blocks while the system is operating, the external data DATA is replaced with the external data DATA instead of the data FDATA from the setting circuit 10. By sending it to the memory block where the force was generated and latching it, the fault can be eliminated without replacing the chip or performing additional programming on the fuse.
  • the data terminal of the first-stage flip-flop F / F1 is used to detect the failure of the shift register itself that constitutes the setting circuit 10. Is connected to the data output terminal of the test data input flip-flop F / Fin.
  • the data output terminal of the last flip-flop FZFz of the shift register is connected to the data input terminal of the test data output flip-flop F / Fut.
  • "1" or "0" is set to the flip-flop F / F in for the test data input and the shift register is shifted, and finally, the test data output flip-flop FZF out It is possible to detect whether or not there is an abnormality in the shift register by judging whether or not the data input is latched in the latch.
  • test data input / output flip-flops F / F in and F / F out are provided on a scan path used for, for example, a test of a mouthpiece or a boundary scan test to set test data and read a test result. It can be configured so that it can be performed without any special mechanism. Also, instead of providing test data input / output flip-flops F / Fin and FZFout, external terminals for test data input / output are provided so that test data can be directly input and test results can be observed. May be.
  • FIG. 4 shows a schematic configuration diagram of a semiconductor device to which the present invention is applied.
  • Each circuit block shown in the figure is formed on one semiconductor chip such as single crystal silicon.
  • ⁇ indicates a pad as an external terminal provided on the semiconductor chip, and the figure indicates an external terminal actually provided which is related to the present invention.
  • an external terminal and a power supply voltage terminal for performing the functions of the chip are provided.
  • the symbols MCL 1, MCL 2... MCL n are the RAM macro cells as internal memory, LGC 11, LGC 1 2 ?? LGC 2 n is a logic circuit that implements the original logic function (system logic) of the chip.
  • the above-mentioned RAM macro cells MCL 1, MCL 2... MCL n are each a memory array, a decoder circuit for selection, a read / write circuit, a spare memory column to be replaced with a defective bit, a replacement control circuit, and a memory. It is configured to include a test auxiliary circuit for facilitating the test.
  • a RAM macrocell is a memory circuit that is inconsistently designed and whose operation has been confirmed, and has a desired storage capacity from a plurality of RAMs registered in a database or the like. It is only necessary to select a device having performance and place it on the chip, which means that a detailed circuit design can be omitted.
  • Such macrocells include not only RAM but also circuits often used in logic LSI, such as ROM, logic operation circuits, PLL (Fuse Locked Loop) circuits, and clock amplifiers.
  • a setting circuit 10 including a fuse array for setting information for identifying the RAM macro cells MCL 1 and MCL 2-"— MCLn and defect address information; Based on the test mode setting signal TMODE (0: 2), the trigger signal TRIG, and the control pulse PULSE, the control signal FSET and the shift clock signal SCK for the setting circuit 10 are generated, and are set in the setting circuit 10.
  • Memory diagnostic controller 20 that has a timing control function to read the data F DAT A and transfer it to the RAM macro cells MCL 1 and MCL2—MC Ln, and a function to convert the setting information into one-parallel data, and a memory diagnostic controller A dedicated memory controller bus 30 for supplying setting information from 20 to the above-mentioned RAM macrocells MCL1, M.CL2... MC Ln is provided.
  • this memory control bus 30 The test mode setting signal TMODE (0: 2) is output as it is to three bits, and the RAM macro cell MC L 1 is read from the setting circuit 10 to 13 bits. , MC L 2... Information about the setting transferred to MC L n is output, and a signal giving a timing for latching the setting information is output in the remaining one bit.
  • a memory test circuit 40 including a pattern generator for generating a test pattern for testing the above RAM cells MCL1, MCL2,... MCLn built in the chip.
  • the pattern generator can use an FSM (finite state machine) type circuit or a microprogram type circuit. Since such a memory test circuit uses only the one already established as a BIST (vinole-in self-test) technology, a detailed description thereof will be omitted.
  • a memory test start signal MBI_STSTRAT is supplied from the outside, the memory test circuit 40 generates a test pattern ⁇ test control signal ⁇ , and outputs each of the RAM macro cells MCL 1, MCL 2... via a test signal line 50. It is configured to supply to MC L n.
  • a test input terminal TESTIN connected to the test signal line 50 is provided as shown by a broken line A, and the test pattern generated by an external memory test circuit is provided. It is also possible to input a signal similar to the test control signal or a fixed pattern from the test input terminal TESTIN to test the RAM macro cells MCL1, MCL2,... MCLn.
  • FIG. 5 shows a configuration example of a shift register constituting the setting circuit 10.
  • each flip-flop is shown as a flip-flop with a built-in fuse.
  • the shift register of this embodiment is composed of thirteen cascade-connected 30 flip-flops F / F1 to FZF13.
  • the fuse sets FS 1 to FS 30 are provided, and these sets are further connected in cascade, and the held data is shifted one bit at a time by the shift clock SCK commonly applied to each flip-flop.
  • FSET is a fuse-set signal that allows all flip-flops to capture and retain the state of the internal fuse.
  • the 13 flip-flops F / F1 to FZF13 in one fuse set each have a bit B1 indicating an application and a bit B indicating an identification code of a RAM macrocell. 2 to B7, B8 to B13 indicating a rescue address code or a timing adjustment code.
  • the bit B1 indicating the application is a bit indicating whether the code of B8 to B13 represents the rescue address code or the timing adjustment code, and specifically, the bit B1 When it is "0", the code of B8 to B13 is the relief address code. When bit B1 is "1", the code of B8 to B13 is timing adjusted. It is a code.
  • the codes B8 to B13 are timing adjustment codes, the preceding four bits are used as adjustment information of the activation timing of the sense amplifier, and the latter two bits are used as adjustment information of the pulse width of the word drive pulse.
  • Bits B2 to B7 indicating the RAM macrocell identification code further include bits B2 and B3 indicating the type of the macrocell and bits B4 to B7 indicating the macrocell number. For example, when bits B2 and B3 are set to "0 0", it indicates that the specified RAM macro cell is a cell having a storage capacity of 4 kbytes, and bits B2 and B3 are set to "01". "" Indicates that the specified RAM macro cell is a cell having 2 kwords of self-control capacity, and bits B2 and B3 are "10" when the specified RAM macro cell is "10". That the cell has a capacity of 1 k ⁇ It represents.
  • Bits B2 and B3 When "1 ⁇ '", it indicates that all RAM macrocells are specified.
  • the specification of RAM macrocells by bits B2 and B3 is mainly performed by bits B1 and B3. This bit is valid when the bit B8 to B13 is the timing adjustment code for bits 1 to 8. Since the same type of RAM in the same chip has similar characteristics to each other, the timing must be adjusted collectively.
  • " ⁇ " means data having a bit length of 36 bits.
  • the type of RAM macrocell is not limited to the above.
  • the word length is not required to be 36 bits, and may be different from one another depending on the cell.
  • FIG. 7 shows a specific circuit diagram of one embodiment of the flip-flops F / F1 to F / F13 with a built-in fuse which constitute the setting circuit 10 having the shift register function.
  • each flip-flop is composed of a fuse F i and a MOS FET Q i connected in series with the fuse, and supplies a potential (V cc or GND) according to the state (cut or uncut) of the fuse F i.
  • the fuse set signal FSET when the fuse set signal FSET is negated to a low level, the data input to the data input terminal IN is synchronized with the shift clock SCK supplied from the memory diagnostic controller 20.
  • the transmission gate is transmitted so as to be transmitted to the latch circuit 13.
  • a logic circuit 15 is provided to form a signal for controlling 14.
  • the fuse built-in flip-flop of FIG. 7 which constitutes the setting circuit 10 having the shift register function is provided with the fuse set signal FSET force as shown in FIG.
  • the shift clock SCK is input when the fuse set signal FSET is negated to low level and goes low, the fuse state FUSE is latched at the rising edge of the fuse and the data input terminal IN It operates to latch the input data into the latch circuit 13.
  • the data latched by the latch circuit 13 is supplied from the output terminal 0 UT to the data input terminal IN of the next-stage flip-flop.
  • the fuse set signal F SET is changed to a high level to latch the fuse state FUSE in the latch circuit 13, and then the shift clock SCK is continuously changed.
  • the transmission gate 14 is formed of a two-stage gate in order to prevent so-called racing in which data input to the data input terminal IN is output from the output terminal OUT as it is.
  • FIG. 9 shows the relationship between the input clock signal CK and trigger signal TRIG, the fuse set signal FSET, the shift clock SCK, and the bus output signals MC3 to MC15 and MC16.
  • the shift clock SCK is output for 13 cycles of the internal clock NCK
  • the serial data is taken in from the fuse setting circuit 10
  • the memory control bus 3 is sent from the memory diagnostic controller 20 in the next 16 cycles.
  • a signal is output on 0.
  • the RAM macrocell decodes signals B3 to B9 indicating the macrocell number on the bus to determine whether the data is addressed to itself. judge.
  • the information signals B10 to B15 on the memory control bus 30 to the RAM macro cell are latched.
  • the above operation which requires a total of 45 cycles, is performed only 30 times, which is the number of fuse sets, and all the fuse setting information is transferred to the corresponding RAM macro cell.
  • the memory diagnostic control circuit 20 is provided with a selector function.
  • the memory diagnostic control circuit 20 can be operated by an external control pulse PULSE instead of the clock signal CK.
  • PULSE an external control pulse
  • CK the clock signal
  • the switching of the operation of the memory diagnosis control circuit 20 is configured to be performed according to a test mode setting signal supplied from the outside.
  • the test mode setting signal is output as MC0 to MC2 on the memory control bus 30 and supplied to the RAM macro cells MCL1 to MCLn.
  • the configuration of the RAM macrocells MCL1 to MCLn will be described with reference to FIG.
  • the RAM macro cell MCL of this embodiment is a RAM core 110 including a memory array in which a plurality of memory cells are arranged in a matrix and a peripheral circuit such as a redundant circuit, and a defective bit in the RAM core 110 is replaced with a spare memory cell.
  • Address receiving latch circuit 121 which takes in a relief address from memory control bus 30 and holds it, acquires timing information for adjusting the timing of signals in RAM core 110 from memory control bus 30 and holds the timing information Reception Latch circuit 122, RAM supplied from memory control bus 30
  • a test bit decoder 150 that generates a signal TDB0 to TDB35 that specifies the test target bit.In test mode, the read data and the expected value data are compared to determine whether they match.
  • Test result comparison and judgment circuit 160, LSI The address signal A, read / write control signal WE, write data WD, or memory test circuit 40 supplied from the system logic circuit that constitutes the original function. It is composed of a selector group 170 for selecting one of the supplied address signal TA and the read / write control signal TWE.test write data TWD.
  • FIG. 11 shows a specific configuration example of the RAM core 110.
  • the RAM core 110 of this embodiment includes a memory array 111 in which a plurality of memory cells MC are arranged in a matrix, an address latch circuit 112 for latching input address signals, and a row address signal.
  • a row address decoder 113 which decodes and selects one of the row lines WL in the memory array corresponding thereto, decodes the input column address signal and sets bit lines BL and BL in the memory array.
  • the timing circuit 116 generates the timing adjustment signals TC 0 to TC 5 supplied from the latch circuit 122 and decodes the timing control signals TC 4 and TC 5 to the pulse generation circuit 115.
  • Adjustment decoder 1 17a for generating an adjustment signal also adjustment decoder 11 1 b for decoding the TC 0 to TC 3 of TC 0 to TC 5 and generating an adjustment signal for the above-mentioned timing circuit 1 16
  • the redundant address decoder 1118 decodes the relief address RYA 0 to RYA 5 supplied from the relief address reception latch circuit 121 to generate a selector switching signal, based on the signal generated by the pulse generation circuit 115.
  • the memory array 11 1 includes 36 memory blocks BLK 0 to BLK 35 and a redundant or spare memory block R—BLK corresponding to 36 bit data read / written at a time. It consists of.
  • Each memory block includes a local memory array LMA, a column switch CSW for connecting a selected pair of bit lines in the local memory array LMA to common data lines CDL and ZCDL, and a memory cell.
  • Sense amplifier SA that widens the data signal read on the common data lines CDL and ZCDL from the data line, a data latch circuit DLT that latches the read data that is widened by the sense amplifier SA, a read / write control signal WE and a write data WD
  • a write amplifier WA for writing data to the selected memory cell based on the data, an input circuit IBF for receiving the write data WD and the read / write control signal WE, and a switching control signal from the redundant decoder 118 Write selector W—SEL, which determines which signal of the input circuit IBF in of the adjacent memory block is selected according to Memory blocks of the data latch D L T adjacent accordance switching control signal from the coder 1 1 8, and a like reading selector R- S E L to determine whether to select a signal of the shift.
  • the pulse generation circuit 115 is a one-shot having a variable delay stage VDL Y1.
  • a pulse generator is provided, and the write pulse width can be adjusted by determining the amount of delay in the variable delay stage VDLY 1 by the adjustment signal from the adjustment decoder 117a.
  • the timing circuit 116 includes a variable delay stage VDLY 2, and the sense amplifier is activated by determining the amount of delay in the variable delay stage VDLY 2 by the adjustment signal from the adjustment decoder 117a. It is configured so that the timing can be adjusted.
  • a write selector W that enables a data bit to be shifted between adjacent memory blocks in one direction (for example, from right to left, that is, from the side having no redundant memory block).
  • SEL and read selector R If a SEL is provided and there is a memory block containing a failure, it is replaced with an adjacent memory block, and the memory block used for replacement is replaced with a further adjacent memory block. To be able to rescue only one memory block containing. In each memory block, only one memory cell is selected, and data of bits corresponding to the number of memory blocks can be read and written simultaneously.
  • the ID of the memory block with the defective bit in the fuse set in the setting circuit shown in Fig. 5 (identification code ) And the repair address are set in pairs, and by transferring them to the RAM macro cell, the replacement of the defective block by the redundant circuit is automatically performed. For example, if a failure bit is found in the memory block BLK 4 of the macro cell whose macro cell type is “B” and the macro cell number is “3”, “0” is added to the 13 fuse sets shown in FIG. 0 1 0 0 1 1 0 0 0 1 0 1 "may be set.
  • the transfer of the fuse setting information from the setting circuit 10 to the RAM macro cell is performed when the system starts up.
  • a mode signal TMODE (0: 2) externally supplied to the memory diagnostic controller 20 is set to "000".
  • the memory diagnostic controller 20 recognizes that it is necessary to transfer the fuse setting information from the setting circuit 10 to the RAM macro cell.
  • the trigger signal TRIG is asserted to a high level, and the transfer of the setting information is started.
  • the information is read serially, converted to parallel, and transferred to the RAM macrocell via the memory control bus 30.
  • the RAM macro cell completes the transfer of the fuse setting information to the reception latch circuit by fetching the data on the memory control bus 30 into the reception latch circuit.
  • the trigger signal TRIG is negated to the oral level
  • the memory test circuit 40 composed of BIST can be replaced with a TAP (Test Access Port) controller specified by a JTAG (Joint Test Action Group).
  • the configurations of the memory diagnostic controller 20 and the fuse setting circuit 10 are the same as those of the embodiment shown in FIG. In this case, an automatic transfer instruction of the fuse setting circuit is prepared as one of the JTAG instructions, and the state of the TAP controller 50 is transited from "Updata-IR" to "Run_test ZId1e". Then, the control signal from the TAP controller to the memory diagnostic controller 20 is asserted. When the self-control signal is asserted, the memory diagnostic controller 20 is configured to automatically transfer information set in the fuse setting circuit 10.
  • RAM macro cell test-Other modes such as transferring data from external pins to the RAM macro cell and resetting the reception latch circuit in the RAM macro cell, can be defined and executed in JTAG option instructions. It is also possible to configure.
  • a test of the memory unit is performed in a first step.
  • the logic unit is tested while the defect information is held in the register in the third step, and the fourth step after the first to third steps is performed.
  • the first to fourth steps may be performed as a probing inspection step in which the semiconductor device is executed in a state where the semiconductor device is in a closed state, so that the manufacturing process can be simplified. Is obtained.
  • a test pattern generation circuit for testing the memory unit and the logic unit, and a test pattern generation circuit
  • a memory test circuit for performing a repair analysis in accordance with a test result of the memory unit by a path, and a fuse circuit for storing defect information formed by the memory test circuit; Address register in which the defect information set in the memory circuit and the defect information formed in the memory test circuit are selectively input.
  • a detection circuit and a latch circuit for determining whether or not the identification code matches the identification code are provided.
  • the memory unit is constituted by a plurality of units, and the defect information is transferred from the fuse circuit to the plurality of memory units via a bus having a plurality of signal lines.
  • the present invention mainly applied to the case where the invention made by the present inventor is applied to an LSI such as a microprocessor having a plurality of built-in RAMs, which is the application field in which the invention is based, is applied to the present invention.
  • the present invention is not limited to this, and can be widely used for a semiconductor device having an internal circuit in which a defect is remedied by information set by a fuse circuit or a circuit function is changed and a manufacturing method thereof. .
  • the defect can be remedied by the information set by the fuse circuit.
  • the present invention can be widely used for semiconductor devices having an internal circuit whose circuit function is changed or its manufacturing method.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Procédé de production d'un dispositif à semi-conducteur doté d'une unité mémoire possédant des cellules de mémoire et une unité logique. Ledit procédé consiste premièrement à tester l'unité mémoire, deuxièmement à mettre en mémoire les informations concernant un défaut, le cas échéant, des cellules de mémoire dans un registre, troisièmement à tester l'unité logique tandis que les informations concernant un défaut se trouvent en mémoire dans le registre et quatrièmement, après les trois premières étapes, à créer un circuit fusible pour conserver les informations de défaut en fonction des informations de défaut se trouvant en mémoire dans le registre.
PCT/JP2001/009245 2001-01-25 2001-10-22 Procede de production d'un dispositif a semi-conducteur et dispositif a semi-conducteur ainsi obtenu WO2002059902A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002560140A JPWO2002059902A1 (ja) 2001-01-25 2001-10-22 半導体装置の製造方法と半導体装置

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JP2001-017253 2001-01-25
JP2001017253 2001-01-25

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WO2002059902A1 true WO2002059902A1 (fr) 2002-08-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009048669A (ja) * 2007-08-13 2009-03-05 Toshiba Corp 半導体記憶装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260198A (ja) * 1999-03-11 2000-09-22 Toshiba Corp 半導体メモリ装置及び半導体メモリ装置搭載システム
JP2001035187A (ja) * 1999-07-21 2001-02-09 Hitachi Ltd 半導体装置およびその冗長救済方法
JP2001266589A (ja) * 2000-03-21 2001-09-28 Toshiba Corp 半導体記憶装置およびそのテスト方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260198A (ja) * 1999-03-11 2000-09-22 Toshiba Corp 半導体メモリ装置及び半導体メモリ装置搭載システム
JP2001035187A (ja) * 1999-07-21 2001-02-09 Hitachi Ltd 半導体装置およびその冗長救済方法
JP2001266589A (ja) * 2000-03-21 2001-09-28 Toshiba Corp 半導体記憶装置およびそのテスト方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009048669A (ja) * 2007-08-13 2009-03-05 Toshiba Corp 半導体記憶装置

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JPWO2002059902A1 (ja) 2004-05-27

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