WO2002054491A2 - Cu-pad/bonded/cu-wire with self-passivating cu-alloys - Google Patents
Cu-pad/bonded/cu-wire with self-passivating cu-alloys Download PDFInfo
- Publication number
- WO2002054491A2 WO2002054491A2 PCT/US2001/043960 US0143960W WO02054491A2 WO 2002054491 A2 WO2002054491 A2 WO 2002054491A2 US 0143960 W US0143960 W US 0143960W WO 02054491 A2 WO02054491 A2 WO 02054491A2
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- WO
- WIPO (PCT)
- Prior art keywords
- pad
- alloy
- wire
- layer
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions
- the invention relates to wire bonding of Cu-Pads with Cu- wires using self-passivating Cu-alloys.
- the self-passivation layer resulting from the dopant rich Cu-alloy protects the Cu from corrosion and oxidation.
- the exposed Cu layer would be highly susceptible corrosion and oxidation.
- the common layered surface finish metallurgies for circuit carrier wirebonding applications are of a nickel (Ni) underplating coating covered by a surface overplating coating layer of gold (Au) , palladium (Pd) , or silver (Ag) .
- These layered surface finish treatments inhibit diffusion of underlying copper (Cu) circuit metallization to the surface of the overplate and prevent subsequent oxidation of the wirebond pad surfaces .
- Considerable oxidation of pad surfaces prior to wirebonding can otherwise result in both inability to wirebond with high yield and deterioration of wirebond interconnection reliability.
- Use of these overplating treatments on copper pads has been used to provide both high yield and high reliability wirebond interconnections.
- US Patent 5,632,438 disclose a direct chip attachment process for aluminum wirebonding on copper circuitization comprising: passing one integrated circuit chip to a carrier; applying to the carrier an attached integrated circuit chip an aqueous cleaning solution containing citric and oxalic acid based additives; applying to the carrier and attached integrated circuit chip a rinse; and wirebonding on copper circuitization carried by the carrier.
- a method for improving bond ability for deep-submicron integrated circuit packages is disclosed in US Patent 6,110,816.
- the method comprises: providing a semiconductor substrate having a top electrically conducting layer, and an overlying layer covering the top electrically conducting layer, and a photoresist applied to the overlying layer; patterning the photoresist to form an array of submicron size holes; etching openings through the overlying layer to the top electrically conducting layer, and forming a rough textured surface profile in the top electrically conducting layer through the opening of the overlying layer; and depositing a passivation film over the overlying layer and forming wiring pad windows for wire ball bonding.
- One object of the present invention is to provide Cu-wire bonded to Cu-pads in a manner so as to provide good bond quality and low resistance, in which the Cu is characterized by self-passivation.
- Another object of the present invention is to provide Cu- wire bonded on Cu-pads in a manner so as to provide good bond quality and low resistance, whereby the Cu-wire bonded on Cu- pads is resistant to corrosion and oxidation due to use of self-passivating Cu-alloys.
- a further object of the present invention is to provide Cu-wire bonded on Cu-pads to provide good bond quality and lower resistance, by using Cu-wire and Cu-pads fabricated to 100% out of Cu-alloys, to provide Cu-wire bonded to Cu-pads, where the Cu is resistant to corrosion and oxidation due to use of self-passivating Cu-alloys.
- a yet further object of the present invention is to provide, Cu-wire bonded to Cu-pads, in which the wire is either a solid Cu-alloy wire or a bi-layer Cu-wire, with an inner core consisting of the Cu-alloy and the outer core being pure Cu, so as to provide good bondability and bond quality upon bonding the copper wire to Cu-pads, to achieve self- passivation from the Cu-alloy.
- a further object yet still of the present invention is to provide Cu-wire bonded to Cu-pads wherein the Cu-wire is a bi- layer and the Cu-pad is a bi-layer (Cu-alloy seed layer + pure Cu-fill) to achieve self-passivation and therefore resistance to corrosion and oxidation.
- good bondability and good bond quality coupled with resistance to corrosion and oxidation is obtained when wire bonding of Cu-pads with Cu- wires is performed using Cu-alloys (Cu-Al, Cu-Mg, and Cu-Li) .
- FIG. 1 shows a Cu-alloy wire prior to bonding with a Cu- pad, in which the Cu pad is surrounded by a Cu-alloy, which is surrounded by a liner, all of which is disposed in a dielectric.
- FIG. 2 shows a Cu-alloy wire after wirebonding and annealing to a Cu-pad, in which the formed bond is either a ball or wedge, and in which there is a dopant rich interface layer characterized by self-passivation, as shown by the X's.
- the wirebonding of Cu-pads with Cu-wires using self-passivating Cu-alloys for making a semiconductor device or integrated circuit is prepared by the following process sequence : a) Patterning a (dual-) damascene structure in dielectric to form the wiring and the bond pads; b) Depositing a metallic liner (PVD, CND , electroless, or other art known method (this step may be optional by using the optimum amount of Cu-alloy) ; c) Depositing Cu-alloy as seed-layer for final Cu-fill
- dielectric cap layer (Cu-diffusion barrier, Si- ⁇ itride, Blok or other art known methods) . It is possible to eliminate this dielectric diffusion barrier totally and continue the processing with Si0 2 deposition or the deposition of other dielectric materials (e.g. low k materials) .
- dielectric cap layer (Cu diffusion barrier, Si- ⁇ itride, Blok or other art known methods) ; 8) Annealing (temperature range: 250°C-450°C) to form self-passivating dopant rich layer at the Cu-dielectric cap layer interface and at the Cu-liner interface.
- Post CMP annealing in a temperature range: 250 °C- 400 °C, this temperature is lower when compared to 9) .
- the post cap layer anneal is approximately 50 °C to form a partially self-passivating dopant rich layer at the Cu-surface and at the Cu-liner interface. It is beneficial to start with a gradual temperature increase to suppress hillock formation. After the initial (partial) formation of a dopant-rich surface layer the hillock formation is significantly reduced;
- the dielectric cap layer (Cu diffusion barrier, Si-Nitride, Blok or other art known methods) . It is possible to eliminate this dielectric diffusion barrier totally and continue the processing with Si0 2 deposition or the deposition of other dielectric materials (e.g. low k materials) ;
- Post cap layer annealing (temperature range: 300 °C - 450 °C, approximately 50 °C higher than 7) post CMP anneal, to form the final self-passivation layer on the liner and cap layer interface.
- This approach with the two anneal steps 7) and 8) is beneficial with respect to hillock formation and adhesion.
- an additional step may be introduced to form the self-passivating/protective layer on the probed Cu surface. Shortly before bonding, this layer is removed by wet cleans in order to have a clean Cu-pad surface for optimum bond quality.
- FIG. 1 depicts a Cu-alloy wire 10 prior to bonding with the Cu-pad 11.
- the Cu-pad is surrounded by a Cu-alloy 12, which in turn is separated from the dielectric 13 by a liner 14.
- a polyimide 15 may be deposited on top of the dielectric.
- the passivated dopant rich interface layer 16 and self-passivated Cu-surface 17, both of which are designated by X' s are formed.
- the self passivation is around the Cu-alloy, around the bond ball or wedge 18, and at the juncture of the pad and wire joinings.
- This dopant rich self-passivating layer is free from hillock structures and protects the Cu from corrosion, oxidation and out-diffusion of Cu into the surrounding semiconductor device areas .
- the Cu-alloys may be Cu- Al, Cu-Mg, Cu-Li as well as other well-known Cu-alloys, and the concentration of the non-Cu doping material from the other component of the Cu-alloy will range from about 0.1 to about 5.0% atomic weight percent of the Cu-alloy.
- Wirebonding of Cu-pads with Cu-wires using self- passivating Cu-alloys is particularly important for improving bondability coupled with protecting the Cu from corrosion and oxidation by virtue of the self-passivation induced by the invention process.
- the Cu-pads with Cu-wires using self- passivating Cu-alloys provides comparable bond quality and low resistance to pure Cu-wire bonded on pure Cu-pads and also provides the self-passivation effect not obtained with pure Cu-wire bonded on pure Cu-pads.
- the bi- layer Cu-wire in combination with a bi-layer Cu-pads exhibits optimum characteristics of self-passivation + low resistance and high bond strength.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP01987076A EP1348235A2 (en) | 2000-12-28 | 2001-11-14 | Cu-pad bonded to cu-wire with self-passivating cu-alloys |
| JP2002555483A JP3737482B2 (ja) | 2000-12-28 | 2001-11-14 | 自己不動態化Cu合金を用いて接着されたCuパッド/Cuワイヤ |
| KR1020037008825A KR100542120B1 (ko) | 2000-12-28 | 2001-11-14 | 집적 회로 구조체와 그 마련 공정 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/751,479 | 2000-12-28 | ||
| US09/751,479 US6515373B2 (en) | 2000-12-28 | 2000-12-28 | Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2002054491A2 true WO2002054491A2 (en) | 2002-07-11 |
| WO2002054491A3 WO2002054491A3 (en) | 2003-06-05 |
Family
ID=25022157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2001/043960 Ceased WO2002054491A2 (en) | 2000-12-28 | 2001-11-14 | Cu-pad/bonded/cu-wire with self-passivating cu-alloys |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6515373B2 (enExample) |
| EP (1) | EP1348235A2 (enExample) |
| JP (1) | JP3737482B2 (enExample) |
| KR (1) | KR100542120B1 (enExample) |
| CN (1) | CN1296997C (enExample) |
| WO (1) | WO2002054491A2 (enExample) |
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| JP3980807B2 (ja) * | 2000-03-27 | 2007-09-26 | 株式会社東芝 | 半導体装置及び半導体モジュール |
| KR100717667B1 (ko) * | 2000-09-18 | 2007-05-11 | 신닛뽄세이테쯔 카부시키카이샤 | 반도체용 본딩 와이어 및 그 제조 방법 |
| US6970939B2 (en) * | 2000-10-26 | 2005-11-29 | Intel Corporation | Method and apparatus for large payload distribution in a network |
| US20030127716A1 (en) * | 2002-01-09 | 2003-07-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Single layer wiring bond pad with optimum AL film thickness in Cu/FSG process for devices under pads |
| US6805786B2 (en) | 2002-09-24 | 2004-10-19 | Northrop Grumman Corporation | Precious alloyed metal solder plating process |
| US7015580B2 (en) * | 2003-11-25 | 2006-03-21 | International Business Machines Corporation | Roughened bonding pad and bonding wire surfaces for low pressure wire bonding |
| US6897147B1 (en) | 2004-01-15 | 2005-05-24 | Taiwan Semiconductor Manufacturing Company | Solution for copper hillock induced by thermal strain with buffer zone for strain relaxation |
| US7851358B2 (en) * | 2005-05-05 | 2010-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low temperature method for minimizing copper hillock defects |
| DE102005044510B4 (de) * | 2005-09-16 | 2011-03-17 | Infineon Technologies Ag | Halbleiterbauteil mit Vorderseitenmetallisierung sowie Verfahren zu dessen Herstellung und Leistungsdiode |
| EP1783829A1 (en) * | 2005-11-02 | 2007-05-09 | Abb Research Ltd. | Method for bonding electronic components |
| US7205673B1 (en) * | 2005-11-18 | 2007-04-17 | Lsi Logic Corporation | Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing |
| US8344524B2 (en) * | 2006-03-07 | 2013-01-01 | Megica Corporation | Wire bonding method for preventing polymer cracking |
| TWI370515B (en) * | 2006-09-29 | 2012-08-11 | Megica Corp | Circuit component |
| US20090008796A1 (en) * | 2006-12-29 | 2009-01-08 | United Test And Assembly Center Ltd. | Copper on organic solderability preservative (osp) interconnect |
| US7911061B2 (en) * | 2007-06-25 | 2011-03-22 | Infineon Technologies Ag | Semiconductor device |
| US8030775B2 (en) | 2007-08-27 | 2011-10-04 | Megica Corporation | Wirebond over post passivation thick metal |
| US20100181675A1 (en) * | 2009-01-16 | 2010-07-22 | Infineon Technologies Ag | Semiconductor package with wedge bonded chip |
| US20100200981A1 (en) * | 2009-02-09 | 2010-08-12 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method of manufacturing the same |
| WO2010112983A1 (en) * | 2009-03-31 | 2010-10-07 | Stmicroelectronics (Grenoble 2) Sas | Wire-bonded semiconductor package with a coated wire |
| US8432024B2 (en) * | 2010-04-27 | 2013-04-30 | Infineon Technologies Ag | Integrated circuit including bond wire directly bonded to pad |
| JP5213146B1 (ja) * | 2012-10-03 | 2013-06-19 | 田中電子工業株式会社 | 半導体装置接続用銅ロジウム合金細線 |
| EP2808873A1 (de) * | 2013-05-28 | 2014-12-03 | Nexans | Elektrisch leitfähiger Draht und Verfahren zu seiner Herstellung |
| KR102100372B1 (ko) | 2013-08-28 | 2020-04-14 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 |
| JP6250864B2 (ja) * | 2015-03-10 | 2017-12-20 | 三菱電機株式会社 | パワー半導体装置 |
| CN113026009A (zh) * | 2021-03-29 | 2021-06-25 | 广东禾木科技有限公司 | 钝化液、提高金属材料键合性能的方法、键合丝、应用 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4761386A (en) * | 1984-10-22 | 1988-08-02 | National Semiconductor Corporation | Method of fabricating conductive non-metallic self-passivating non-corrodable IC bonding pads |
| US4676827A (en) * | 1985-03-27 | 1987-06-30 | Mitsubishi Kinzoku Kabushiki Kaisha | Wire for bonding a semiconductor device and process for producing the same |
| US5134460A (en) * | 1986-08-11 | 1992-07-28 | International Business Machines Corporation | Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding |
| JP2659714B2 (ja) * | 1987-07-21 | 1997-09-30 | 株式会社日立製作所 | 半導体集積回路装置 |
| JPH04164332A (ja) * | 1990-10-29 | 1992-06-10 | Matsushita Electron Corp | 半導体装置 |
| US5371654A (en) * | 1992-10-19 | 1994-12-06 | International Business Machines Corporation | Three dimensional high performance interconnection package |
| US5622608A (en) * | 1994-05-05 | 1997-04-22 | Research Foundation Of State University Of New York | Process of making oxidation resistant high conductivity copper layers |
| US5766379A (en) * | 1995-06-07 | 1998-06-16 | The Research Foundation Of State University Of New York | Passivated copper conductive layers for microelectronic applications and methods of manufacturing same |
| EP0751567B1 (en) * | 1995-06-27 | 2007-11-28 | International Business Machines Corporation | Copper alloys for chip interconnections and method of making |
| US6037257A (en) * | 1997-05-08 | 2000-03-14 | Applied Materials, Inc. | Sputter deposition and annealing of copper alloy metallization |
| US6387805B2 (en) * | 1997-05-08 | 2002-05-14 | Applied Materials, Inc. | Copper alloy seed layer for copper metallization |
| US6249055B1 (en) * | 1998-02-03 | 2001-06-19 | Advanced Micro Devices, Inc. | Self-encapsulated copper metallization |
| US6153521A (en) * | 1998-06-04 | 2000-11-28 | Advanced Micro Devices, Inc. | Metallized interconnection structure and method of making the same |
| ATE316426T1 (de) * | 1998-06-30 | 2006-02-15 | Semitool Inc | Metallisierungsstrukturen für mikroelektronische anwendungen und verfahren zur herstellung dieser strukturen |
| US6218302B1 (en) * | 1998-07-21 | 2001-04-17 | Motorola Inc. | Method for forming a semiconductor device |
| US6281127B1 (en) * | 1999-04-15 | 2001-08-28 | Taiwan Semiconductor Manufacturing Company | Self-passivation procedure for a copper damascene structure |
| US6329722B1 (en) * | 1999-07-01 | 2001-12-11 | Texas Instruments Incorporated | Bonding pads for integrated circuits having copper interconnect metallization |
| US6339022B1 (en) * | 1999-12-30 | 2002-01-15 | International Business Machines Corporation | Method of annealing copper metallurgy |
-
2000
- 2000-12-28 US US09/751,479 patent/US6515373B2/en not_active Expired - Lifetime
-
2001
- 2001-11-14 CN CNB018216528A patent/CN1296997C/zh not_active Expired - Fee Related
- 2001-11-14 EP EP01987076A patent/EP1348235A2/en not_active Withdrawn
- 2001-11-14 KR KR1020037008825A patent/KR100542120B1/ko not_active Expired - Fee Related
- 2001-11-14 JP JP2002555483A patent/JP3737482B2/ja not_active Expired - Fee Related
- 2001-11-14 WO PCT/US2001/043960 patent/WO2002054491A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002054491A3 (en) | 2003-06-05 |
| JP3737482B2 (ja) | 2006-01-18 |
| US6515373B2 (en) | 2003-02-04 |
| JP2004517498A (ja) | 2004-06-10 |
| EP1348235A2 (en) | 2003-10-01 |
| CN1296997C (zh) | 2007-01-24 |
| US20020084311A1 (en) | 2002-07-04 |
| KR20040018248A (ko) | 2004-03-02 |
| KR100542120B1 (ko) | 2006-01-11 |
| CN1484857A (zh) | 2004-03-24 |
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