WO2002043290A2 - Procede et dispositif de multiplexage de paquets de donnees - Google Patents

Procede et dispositif de multiplexage de paquets de donnees Download PDF

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Publication number
WO2002043290A2
WO2002043290A2 PCT/IB2001/002761 IB0102761W WO0243290A2 WO 2002043290 A2 WO2002043290 A2 WO 2002043290A2 IB 0102761 W IB0102761 W IB 0102761W WO 0243290 A2 WO0243290 A2 WO 0243290A2
Authority
WO
WIPO (PCT)
Prior art keywords
pointer
entry
connection
address
address information
Prior art date
Application number
PCT/IB2001/002761
Other languages
German (de)
English (en)
Other versions
WO2002043290A3 (fr
Inventor
Martin Götzer
Original Assignee
Marconi Communications Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Communications Gmbh filed Critical Marconi Communications Gmbh
Priority to EP01997912A priority Critical patent/EP1340405A2/fr
Priority to JP2002544894A priority patent/JP2004515115A/ja
Priority to AU2002219424A priority patent/AU2002219424A1/en
Priority to CA002430943A priority patent/CA2430943A1/fr
Publication of WO2002043290A2 publication Critical patent/WO2002043290A2/fr
Publication of WO2002043290A3 publication Critical patent/WO2002043290A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
    • H04J3/247—ATM or packet multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Definitions

  • the present invention provides a method for multiplexing data packets and a multiplexer which is inexpensive and with little are realizable and scalable due to the amount of memory. Another advantage of the invention is that it allows transparent virtual paths, ie that the evaluation of a VCI value in the multiplexer can either be permitted or prevented.
  • the task of the multiplexer 2 is to use this input address information to generate destination address information and to send it out again together with the cell, on the basis of which the output transmission path 4a, 4b, 4c or 4d suitable for forwarding the cell is selected can and on the basis of which a correspondingly constructed node, which forms the other termination of the selected output transmission link, can in turn again perform address translation and forwarding.
  • Each output transmission link 4a, 4b, 4c and 4d is assigned an output interface 6a, 6b, 6c, 6d, which among the ATM cells output by the multiplexer 2 based on their destination address information determined, which are intended for the respectively assigned transmission path and forwards it to the transmission path.
  • step S9 this used bit is used to check whether the entry found is valid or not. If not, a retransmission can be requested as in the check in step S3. If so, the entry is evaluated in order to generate a destination address information for the packet and the one provided with this destination address information . Output packet in step S10.
  • the entry with the address X of the pointer table 15 is assigned to the virtual path VPO. It has a used bit ÜB with the logical value "true”, a sequence pointer F-PTR with the value Y and a pointer type bit PTB, which indicates that the sequence pointer points to the connection table. Since with the finding of a reference on the connection table 16 the evaluation of the input address information is completed, the element FS has the value 0, and F-LSB can have any value.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Selon la présente invention, des paquets de données renfermant une information d'adresse (VPI, VCI) sont reçus au niveau d'un connecteur d'entrée (5a, 5b, 5c, 5d) d'un noeud (1). Afin de trouver une information de voie d'acheminement pour ce paquet de données, l'information d'adresse est décomposée (S1) en une partie de début et une partie suivante, la partie de début étant utilisée (S2) en tant qu'adresse pour l'adressage d'un tableau de pointeurs (15), lequel tableau contient des entrées définissant la façon dont la partie suivante doit être exploitée. L'entrée peut comporter un pointeur sur un tableau de connexion, contenant l'information de voie d'acheminement (S4, V), ou sur une autre entrée du tableau de pointeurs (S4, Z).
PCT/IB2001/002761 2000-11-24 2001-11-23 Procede et dispositif de multiplexage de paquets de donnees WO2002043290A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP01997912A EP1340405A2 (fr) 2000-11-24 2001-11-23 Procede et dispositif de multiplexage de paquets de donnees
JP2002544894A JP2004515115A (ja) 2000-11-24 2001-11-23 データパケットを多重化する装置及び方法
AU2002219424A AU2002219424A1 (en) 2000-11-24 2001-11-23 Method and device for multiplexing data packets
CA002430943A CA2430943A1 (fr) 2000-11-24 2001-11-23 Procede et dispositif de multiplexage de paquets de donnees

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10058457.8 2000-11-24
DE2000158457 DE10058457A1 (de) 2000-11-24 2000-11-24 Verfahren und Vorrichtung zum Multiplexen von Datenpaketen

Publications (2)

Publication Number Publication Date
WO2002043290A2 true WO2002043290A2 (fr) 2002-05-30
WO2002043290A3 WO2002043290A3 (fr) 2002-08-08

Family

ID=7664564

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2001/002761 WO2002043290A2 (fr) 2000-11-24 2001-11-23 Procede et dispositif de multiplexage de paquets de donnees

Country Status (6)

Country Link
EP (1) EP1340405A2 (fr)
JP (1) JP2004515115A (fr)
AU (1) AU2002219424A1 (fr)
CA (1) CA2430943A1 (fr)
DE (1) DE10058457A1 (fr)
WO (1) WO2002043290A2 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0680236A1 (fr) * 1994-04-29 1995-11-02 International Business Machines Corporation Dispositif pour convertir des valeurs d'entrée en des valeurs de sortie correspondantes
EP0833257A2 (fr) * 1996-09-27 1998-04-01 Motorola, Inc. Procédé et dispositif pour rechercher en parallèle un circuit d'antémémoire
GB2325321A (en) * 1997-05-12 1998-11-18 Applied Marketing & Technology Associative memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2507756B2 (ja) * 1987-10-05 1996-06-19 株式会社日立製作所 情報処理装置
SE515275C2 (sv) * 1992-12-14 2001-07-09 Ericsson Telefon Ab L M Paketdatanät

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0680236A1 (fr) * 1994-04-29 1995-11-02 International Business Machines Corporation Dispositif pour convertir des valeurs d'entrée en des valeurs de sortie correspondantes
EP0833257A2 (fr) * 1996-09-27 1998-04-01 Motorola, Inc. Procédé et dispositif pour rechercher en parallèle un circuit d'antémémoire
GB2325321A (en) * 1997-05-12 1998-11-18 Applied Marketing & Technology Associative memory

Also Published As

Publication number Publication date
WO2002043290A3 (fr) 2002-08-08
AU2002219424A1 (en) 2002-06-03
JP2004515115A (ja) 2004-05-20
DE10058457A1 (de) 2002-06-13
CA2430943A1 (fr) 2002-05-30
EP1340405A2 (fr) 2003-09-03

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