GB2325321A - Associative memory - Google Patents

Abstract

An associative memory comprises: first and second associative memory sections S1, S2, each of which is operable to receive an input word (VPI, VCI Fig. 2) and to output an address (S1, S2) at which that word is stored within the memory section concerned, and a logic unit (L) which has a first mode of operation in which the outputs from both memory sections are enabled, and a second mode of operation in which the output from only one of the memory sections is enabled. Circuit details of the logic unit (L) linking sections (S1, S2) is described (Fig. 4). The memory may be used in an asynchronous transfer mode (ATM) telecommunications system where the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier) fields are to be compared in an associative memory array. Thus the VPI and VCI data can be held separately.

Description

ASSOCIATIVE MEMORIES The present invention relates to associative memories, in particular, but not exclusively, to associative memories for use in an asynchronous transfer mode (ATM) telecommunications system.

Asynchronous Transfer Mode (ATM) is rapidly emerging as the leading cell-based switching technology for high-bandwidth, connection-oriented and connection less networking for both local and publicly switched networks. The market is growing rapidly, and ail the major network equipment suppliers offer a range of ATM products.

A high-bandwidth networking standard has become an important requirement with the growth of the Internet and intranets. On-line service access is now by far the slowest aspect of computer use. Processing speeds have increased by orders of magnitude, while dial-up data access has languished in the doldrums.

ATM is currently implemented at 155MBits/s. 622MBitls systems are under development. The next standard data rate is planned at 2.5GBits/s. These bandwidths allow the transfer of real-time video and audio data, and enable video-conferencing, interactive video, and highspeed data access. Clearly, there is a market need for such a technology.

ATM transmits data by dividing it into cells, each consisting of 53 octets.

While the data, or payload, comprises 48 of the octets, the remaining 5 octets form the header which holds information about what the cell is and how it should be routed through the network.

The connection information includes virtual path and virtual channel identification. The data is sent from one endpoint to another via connecting points. The information in the header is contained in the VPI (virtual Path Identifier) and VCI (Virtual Channel Identifier) fields. A VC and VP link exists between an endpoint and connecting point, and between a connecting point and a connecting point. VPI and VCI information relates to a single link. At each connecting point the VPI and VCI may be translated for that particular link.

Each VPI and VCI on a transmission path must be unique. Therefore, the transmission path across one link uses VPls and VCls independently of other links. Each connecting point, or switch, maps incoming VPls and VCls to outgoing VPls and VCls.

This approach of ascribing values dynamically to VPls and VCls means that each source and destination within an ATM network does not need its own unique address, as it does in other networking protocols such as Ethernet. Thus the number of bits needed to identify an ATM connection is reduced because the values can be reused from one link to another.

Switches will remap a VCI or VPI if the incoming value is already in use on that link.

Connections can be established for either virtual channels, which are individual connections, or for virtual paths, which contain groups of channels. Therefore, an ATM switch must be able to handle both virtual channel connections (VCCs) and virtual path connections (VPCs) and be able to distinguish between the two.

VCCs and VPCs are defined between endpoints, and are a concatenated list of VP and VC links. VCC routing is determined by the combination of the VPI and VCI fields, while VPC routing is determined by the VPI only.

The VCI field is 16 bits and the VPI is 8 bits.

Another field in the ATM cell header is the 4-bit GFC (Generic Flow Control) field. This field is generally not used, but may be used for cell routing purposes in the future. Therefore, the information in the header that can be used for data routing are the GFC, VPI, VCI fields. Data in the cell header also identifies the payload type (PT), call loss priority (CLP) and a header error check (HEC).

The entire ATM cell is shown in Figure 1 of the accompanying drawings.

Accordingly, there is a need for fast look-up of information associated with an incoming cell, and that is done through its VPI and/or VCI. The incoming VPINCI are used to access a table which holds information about each connection, including the outgoing VPINCI. The width of the concatenated GFCNPINCI fields is 28 bits. This total field width represents an address space of 256M locations, of which only a few thousand would be occupied.

While hashing techniques cut the number of locations needed to hold the required data, presently proposed systems use associative memories in which non-contiguous addressing leads to a deterministic response. The system only requires as many associative memory locations as are needed to support a particular number of connections.

In associative, or content addressable memories (CAMs), the incoming data, referred to as the comparand, is compared against all valid locations in the CAM array in a single cycle. If there is a match with one of the contents, the address of that content is output along with a flag indicating a successful comparison. In this respect, the CAM acts in the exact opposite way to a RAM in which an address is fed in and data is read out from or written in to the addressed location.

If the data in the CAM contains any repeated values then a multiple response can occur. Multiple responses are resolved through a priority encoder. In systems where data is always unique the priority encoder is unnecessary.

A CAM array works by having a precharged match line for each word in the array. All cells are wire-NORed onto the match line. If any one or more cells mismatchs with the corresponding bit of the comparand, the match line is discharged. Therefore, a LOW logic state on the match line after a compare cycle indicates a mismatched memory location while a HIGH indicates a match at that location.

To access data associated with the matching location, the address output from the CAM can be used to address an external RAM, or the match line can be connected directly to the word line of a RAM array. In this way the values stored in the CAM array become the address values for the RAM, and they can be non-contiguous. Non-contiguous addressing leads to highly efficient data storage and retrieval in sparse data structures.

However, in previously-considered CAM-oriented systems, the look-up table is accessed twice, once to check the VPI and VCI fields together, and once for the VPI alone. The first access checks for VC connections, while the second checks for VP connections. This procedure requires two complete access cycles. Moreover, in some cases current practice uses hash tables rather than fully associative look-up in content addressable memory (CAM).

In the slower ATM systems, at 155MBits/s, the header translation process can be handled in software, including checking for both VC and VP connections. The demands imposed by 622MBits/s and 2.5GBits/s require that a more efficient approach be taken.

Cell times for 1 55MBits/s, 622MBits/s and 2.5GBits/s are as follows: ATM Bit Rate Cell Time 1 55MBits1s 2735ns 622MBits/s 682ns 2.5GBits/s 170ns The previously-considered systems are thus inefficient in that two accesses into the look-up table are required, and twice the processing of the retrieved information.

According to one aspect of the present invention there is provided an associative memory comprising: first and second associative memory sections, each of which is operable to receive an input word and to output an address at which that word is stored within the memory section concerned; and a logic unit operatively connected with the first and second memory sections, which has a first mode of operation in which the outputs from both memory sections are enabled and a second mode of operation in which the output from only one of the memory sections is enabled.

According to a second aspect of the present invention, there is provided an associative memory comprising: first and second associative memory sections, each of which is operable to receive a respective input word and to output an indication as to whether that word is stored within the memory section concerned; and a logic unit which, when a flag associated with a pair of input words to the two memory sections takes a first value, controls the first and second memory sections such that they indicate whether the pair of input words are both stored in the respective memory sections, and which, when the flag takes a second value, controls the first and second memory sections such that they indicate whether the first input word is stored in the first memory section.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 shows a schematic view of an ATM cell structure; Figure 2 shows a schematic diagram of an associative memory array embodying the present invention; Figure 3 shows a block logic diagram of part of the array of Figure 2; and Figure 4 shows a more detailed logic diagram for the unit shown in Figure 3.

As will be apparent from the following specific description of an embodiment of the invention, a memory embodying the present invention can be used with an ATM system. However, it will be readily apparent that such a memory array can be used in any suitable application, in particular applications requiring fast selective access to two or more stored data words. In the described embodiment, the two stored data words are the virtual path indicator and virtual channel indicator fields.

Embodiments of the present invention allow single cycle access into the header translation look-up table where VPC and VCC information can coexist. The storage mechanism differentiates between the two types of connection.

A VCC requires the VPI and VCI fields to be compared in an associative memory array, while a VPC requires only the VPI field to be compared.

A conventional approach would be to compare the concatenated VPI and VCI fields in a homogeneous block of associative memory during the first phase of the process, and then compare the VPI field, with the VCI field masked from comparison, during the second phase.

However, in an embodiment of the invention, the associative memory is divided into two sections across its width, and additional logic and storage is provided to link each word across the two sections of the array. Thus, VPI and VCI data can be held separately. The logic linking the two sections of the associative memory stores information as to which type of connection is held at each location, which in turn determines how the separate VPI and VCI fields are compared with the incoming VPINCI. A location that is designated as a VCC compares the concatenated VPINCI fields. A location that is designated as a VPC will only compare the VPI field and will ignore the VCI.

The user sets up a connection by writing a new value to the memory array. It is written as either a VCC or as a VPC. The storage information in the linking logic is automatically written to indicate the type of connection.

The overhead associated with this method is in the extra silicon area taken up by the linking logic. This overhead can be as little as one bit of storage and a single logic gate. Therefore, for an array that is 28 bits wide, there will be an increase of about 4% in silicon area for the associative memory array. Typically, the associative memory array is 50% of the entire silicon area, so the total increase of area will be about 2%.

Referring to Figure 2, the following pseudo-code describes the processing in the linking logic: If location k stores a VCC Then Compare VPI + VCI with Sl(k) + S2(k) Else Compare VPI with S1(k) Note that the "+" operator in the pseudo-code represents the concatenation function.

There are many possible logical structures that could be used to implement embodiments of the invention. The following logic represents only one such implementation. It comprises a single element of storage and a logic gate. Figure 3 shows two sections of associative memory storage, S1 and S2, and the logic, G, that links them and its storage element, SL.

Figure 3 represents location k. Associative memory section S1 holds the VPI and associative memory section S2 holds the VCI. Sl(k)(x) is bit x of S1 in the k th location, S2(k)(y) is bit y of S2 in the k th location. SL(k) is the storage associated with the linking logic and G(k) is the logic gate that controls the linking for location k. Ml(k) is the match line for location k of associative memory section SI, and M2(k) is the match line for location k of associative memory section S2. W(k) is the common word line for location k. Bl(x) and /Bl(x) are the differential bit lines for bit x in associative memory section S1, B2(y) and /B2(y) are the differential bit lines for bit y in associative memory section S2. BL and /BL are the differential bit lines for the storage associated with the linking logic.

There are p bits in the VPI field and q bits in the VCI field.

Each associative memory section S1 and S2 operates in a conventional associative memory manner. That is with reference to associative memory section SI, when the comparand BI is applied to memory section S1, the outputs from the elements S?(k)(l) to Sl(k)(p) cause the match line M1(k) to go high when the comparand bit corresponds to the bit stored in the storage element concerned. Any one storage element can cause M1(k) to go low when that bit does not match the corresponding bit of the comparand B1. Similarly in associative memory section S2 the storage elements S2(k)(l) to S2(k)(q) act in an identical manner when compared to the comparand B2. The second associative memory section S2 has an output M2(k) which can be pulled low by any one of the storage elements not matching the comparand bit concerned.

Thus when a match occurs in either section S1 or S2 the respective match line M1(k) or M2(k) is sent high. A mismatch causes the match line concerned to be pulled low.

When the SL(k) output, Q(k), is LOW, the logic state of M2(k) is conveyed to M1 (k) via gate G(k). If M2(k) is LOW because one or more bits in S2(k) does not match the corresponding bit in the comparand field conveyed on B2(y) for 1 s y s q, it will cause Ml(k) to be LOW at location k because of the mismatch in the VCI field of VPINCI. If M2(k) is HIGH because all bits in S2(k) match the comparand field conveyed on B2(y) for 1 s y s q, then the logic state of Ml(k) will be determined by the comparison of S1(k) with the comparand field conveyed on B1(x) for 1 s x s p. Under this circumstance, if there is one or more bits in S1(k) that mismatchs with the comparand field conveyed on B1(x) for 1 S x < p, then Ml(k) will be LOW at location k because of the mismatch in the VPI field of VPINCI at location k; if all bits in SI (k) match the comparand field conveyed on Bl(x) for 1 S x < p, then Ml(k) will be HIGH, indicating a match in VPINCI at location k.

When the SL(k) output, Q(k), is HIGH, the logic condition on M2(k) is isolated from Ml(k) by G(k), and Ml(k) will only be LOW if one or more bits in Sl(k) mismatchs with the comparand field conveyed on B1(x) for 1 s x < p, indicating a mismatch in the VPI field of VPINCI at location k.

If all bits in Sl(k) match the comparand field conveyed on Bl(x) for 1 < x S p, then Ml(k) will be HIGH, indicating a match in the VPI field of VPINCI at location k. Any mismatch in the VCI field is ignored.

Therefore, the logic level written into the storage element SL(k) determines whether the kth location responds as a VP or VC connection.

If it is LOW the location holds a VCC, if it is HIGH the location holds a VPC.

Note that the user need not have direct control over the BL and /BL lines when writing a new value into the CAM. Instead, the CAM can provide two write instructions: WRITE~VPC and WRITE~VCC. The logic value written to the linking logic storage element is determined by the control logic of the CAM. Therefore, the linking logic storage element is entirely transparent to the system designer, and no explicit data need be written to set SL(k).

A detailed implementation of one possible circuit that will provide the necessary functions for the linking logic and storage element is shown in Figure 4.

Inverter gates N1 and N2, and transistors T1 and T2 form a conventional static storage cell. The logic levels on the differential bit lines BL and /BL are written to the cell when W(k) is HIGH. Transistors T3, T4 and T5 form a NOR gate. Transistor T6 inverts the signal and drives the Ml(k) line. Note that M1(k) is the main match line of location k, and is used as the access enable for associated data.

Embodiments of the invention provide a method and apparatus whereby VP and VC connections can coexist in a fully associative look-up table in high-speed ATM switches. This approach results in doubling the speed at which the look up is performed, and halves the amount of processing associated with the accessed data.

The method relies on partitioning of a CAM array into two sections with logic linking the two halves. A storage element per location determines the type of connection stored at that location. The operation of the mechanism is entirely transparent to the system designer. Data is written to a location when a connection is set up within the switch; the instruction that is used to write the data determines the type of connection that is established.

The storage element that determines the connection type, and the associated logic, fits into the pitch of the array, thereby causing only about a 2% increase in silicon area usage.

Hardware acceleration provided by a CAM using this mechanism will prove to be very useful to designers faced with the task of handling data at the rates required by high-speed ATM systems.

This technique would find application in any system where decision making is based on two criteria, one being a logical subset of the other.

An extension to the principal would include any multi-decision process with a hierarchical structure to the elements of the decision process. In other words, any associative process that can be subdivided into a hierarchy of logically related subprocesses could use linking logic to determine the scope of associativity across the subfields of comparison.

Claims (9)

1. An associative memory comprising: first and second associative memory sections, each of which is operable to receive an input word and to output an address at which that word is stored within the memory section concerned; and a logic unit which has a first mode of operation in which the outputs from both memory sections are enabled, and a second mode of operation in which the output from only one of the memory sections is enabled.

2. An associative memory comprising: first and second associative memory sections, each of which is operable to receive a respective input word and to output an indication as to whether that word is stored within the memory section concerned; and a logic unit which, when a flag associated with a pair of input words to the two memory sections takes a first value, controls the first and second memory sections such that they indicate whether the pair of input words are both stored in the respective memory sections1 and which, when the flag takes a second value, controls the first and second memory sections such that they indicate whether the first input word is stored in the first memory section.

3. A memory as claimed in claim 1 or 2, wherein the logic unit comprises a storage element for storing information relating to the mode of operation, and a logic element for performing the said mode of operation.

4. A memory as claimed in claim 3, wherein the storage element stored one bit of information, and the logic element is an OR gate.

5. A memory as claimed in claim 3 or 4, wherein the storage element stores information indicative of whether either or both memory sections are to be accessed.

6. A memory as claimed in claim 3, 4 or 5, wherein the information stored in the storage element is updated automatically in dependence upon the information stored in the associative memory sections.

7. A memory as claimed in claim 3, 4 or 5, wherein the information stored in the storage element can be updated by a user.

8. An associative memory as claimed in any one of claims 1 to 7, for use in an asynchronous mode telecommunications systems, wherein the first memory section stores virtual path information and the second memory section stores virtual channel information.

9. An associative memory substantially as hereinbefore described with reference to Figures 2, 3 and 4 of the accompanying drawings.