WO2002009193A1 - Ensemble comportant un magnetotransistor, procede de production d'un ensemble comportant un magnetotransistor et procede pour mesurer un champ magnetique - Google Patents

Ensemble comportant un magnetotransistor, procede de production d'un ensemble comportant un magnetotransistor et procede pour mesurer un champ magnetique Download PDF

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Publication number
WO2002009193A1
WO2002009193A1 PCT/DE2001/002535 DE0102535W WO0209193A1 WO 2002009193 A1 WO2002009193 A1 WO 2002009193A1 DE 0102535 W DE0102535 W DE 0102535W WO 0209193 A1 WO0209193 A1 WO 0209193A1
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WO
WIPO (PCT)
Prior art keywords
arrangement according
doped
arrangement
region
area
Prior art date
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PCT/DE2001/002535
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German (de)
English (en)
Inventor
Ning Qu
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Robert Bosch Gmbh
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Filing date
Publication date
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Publication of WO2002009193A1 publication Critical patent/WO2002009193A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices

Definitions

  • the invention relates to an arrangement with a magnetotransistor with a doped semiconductor substrate and a layer sequence of doped semiconductor layers based on the doped semiconductor substrate, electrical contacts being available on the surface of the arrangement, so that at least two transistors can be realized with the arrangement.
  • the invention further relates to a method for producing an arrangement with a magnetotransistor.
  • the invention further meets a loading method "for measuring a magnetic field.
  • Generic magnetotransistors can be used to measure a magnetic field. This takes advantage of the fact that the strength of the currents flowing in the two transistors of the arrangement depends on the strength of the magnetic field parallel to the surface of the arrangement. The reason for this dependency lies in the steering of the moving charge carriers within the semiconductor structure by the Lorentz force.
  • FIG. 1 An example of a lateral bipolar magnetotransistor (LMT) of the prior art is shown in cross section in FIG.
  • the illustration uses the example of a pnp magnetotransistor, although all statements apply to an npn magnetotransistor while reversing the charge sign.
  • the arrangement is based on a p-doped semiconductor substrate 110.
  • An n-doped well 112 is diffused into this p-doped semiconductor substrate 110.
  • three p-doped wells 114, 116, 118 are diffused into the n-doped well 112.
  • the three p-doped wells 114, 116, 118 are also each provided with three metal contacts 122, 124, 126.
  • Two metal contacts 128, 130 are arranged on the surface of the n-doped well 112.
  • the arrangement is symmetrical to a system plane 132 which is perpendicular to the layer sequence. This symmetry relates both to the geometry of the arrangement and to the respective doping concentrations of the p- or n-doped regions.
  • the electrode 124 is used as the emitter electrode.
  • the outer electrodes 128, 130 are connected as base electrodes, and the electrodes 122 and 126 work as collector electrodes of the two pnp transistors on the left and right of the plane of symmetry 132.
  • a left lateral pnp transistor which has an emitter contact 124 at the emitter zone 116, a base contact 128 at the base zone 112 and a collector contact 122 at the collector zone 114
  • a right pnp transistor which has an emitter contact 124 at the emitter zone 116, a base contact 130 at the base zone 112 and a collector contact 126 at the collector zone 118.
  • the arrangement results in a parasitic vertical pnp transistor, which consists of the emitter zone 116, the base zone 112 and the p-type substrate 110, which acts as a collector zone.
  • collector currents 134, 136 which are different, the difference depending on the strength of the magnetic field components mentioned.
  • the current difference between the currents which are tapped at the right collector electrode 122 or the left collector electrode 126 can be used as an output signal for the measurement of the magnetic field can be used.
  • Magnetotransistors of this type when used as a magnetic field sensor, show high sensitivity, good linearity and low noise.
  • the arrangement it is also possible to use the arrangement not only to measure the size of the magnetic field, but also the direction of the field.
  • a disadvantage of the arrangement shown in FIG. 4, however, is that a lateral current is already present in the region of the surface of the arrangement, which results from charge carriers which were emitted directly from the emitter zone 116 laterally into the p-doped base zone. Since these charge carriers remain unaffected by a magnetic field component running parallel to their direction of movement, they make no contribution to the magnetic sensitivity of the component.
  • FIG. 5 shows a further embodiment of a prior art magnetotransistor in cross section, in which these lateral currents in the vicinity of the chip surface are effectively suppressed.
  • the arrangement according to FIG. 5 largely corresponds to that from FIG. 4, the same reference symbols denoting the same elements.
  • an n-doped ring 138 is provided around the emitter zone 116, which suppresses the hole injection from the p-doped emitter zone 116 into the n-doped base zone in the vicinity of the chip surface.
  • the sensitivity of the component can be considerably improved by this reduction in the lateral current flow along the chip surface.
  • Such a "suppressed side-wall injection magnetotransistor" (SSIMT) is described, for example, in R.
  • a disadvantage of the arrangements of the prior art according to FIGS. 4 and 5 is the high power consumption of the arrangements, which results from the large substrate current 140.
  • the emitter electrode 124 is grounded, and negative voltages are applied to the base electrodes 128, 130 and the collector electrodes 122, 126, respectively. If a negative voltage is also applied to the substrate electrode 120, the vertical parasitic pnp transistor 116, 112, 110 is enabled to amplify current, and a collector current 140 flows to the substrate electrode 120.
  • a positive voltage is applied to the substrate electrode 120, the transition between the p-substrate 110 and the n-doped base zone 112 is polarized in the direction of flow, and the substrate current flows from the p-substrate 110 to the n-doped base zone 112.
  • the size of this into one The substrate current 140 of the magnetotransistor flowing in the other direction depends on the structure of the magnetotransistor and the operating conditions. It can reach values which are an order of magnitude higher than the collector currents 134, 136 which are essential for the measurement and which are to be regarded as useful currents. Examples of the ratio of the substrate current to the collector currents are given in C.
  • the invention builds on the generic arrangement according to claim 1 in that a first region on the surface of the arrangement with a first doping type (n or p) is embedded in a second region on the surface of the arrangement with a second doping type (p or n) is that the second region with the second doping type (p or n) is embedded in a third region on the surface of the arrangement with the first doping type (n or p) and that the first doping type (n or p) is different from the second doping type (p or n) differs.
  • this arrangement it is possible to significantly increase the sensitivity with regard to a magnetic field measurement by applying suitable potentials to the individual areas at suitable locations.
  • this increase in sensitivity results from the reduction of a lateral current in the region of the chip surface.
  • no ring structure is required.
  • the lateral current in the area of the chip surface is reduced in that the emitter zone and the collector zone are not in the same base trough as in the case of a conventional magnetotransistor (see FIG. 4 and FIG. 5).
  • the electrons must first flow vertically from the first area to the third area. Only then can the current flow off to the side.
  • the pronounced vertical current is responsible for increasing the sensitivity.
  • the strength of the substrate current by means of suitable potentials in the respective areas.
  • the invention is particularly advantageous in that the third area provides collector properties for the transistors, the second area provides basic properties for the transistors and the first area provides emitter properties for the transistors.
  • the first area provides an emitter contact
  • the second area provides two base contacts
  • the third area provides two collector contacts. Two transistors with a common emitter contact are thus realized. Therefore, the collector currents of the two transistors can be used as measurement signals for a magnetic field measurement.
  • the substrate preferably has a contact.
  • a suitable potential on the substrate relative to the potentials on the other contacts, the. significantly reduce unwanted substrate flow.
  • Suitable potentials can prevent a vertical parasitic transistor from being formed as in a conventional magnetotransistor, so that it is possible for only a reverse current to flow as the substrate current with suitable wiring. This is then in a wide th temperature range is smaller than the collector current, which is the actual useful current for the measurement signal.
  • the transition between the third region and the layer below it is preferably polarized in the blocking direction. This poling is made available by applying the appropriate potentials to the substrate and to the other contacts of the arrangement.
  • the barrier layer creates an insulation effect with regard to a parasitic vertical substrate current.
  • the arrangement has a pnpnp layer sequence. There is therefore an arrangement of five layers, so that an arrangement of high flexibility is provided by suitable doping of the layers and by suitable selection of the applied potentials.
  • the invention is particularly advantageous in that a first n-doped well is provided in a p-doped semiconductor substrate, and in the first n-doped well the third region is provided as a p-doped well, in the third region the second region is provided as an n-doped well and that the first area is provided as a p-doped well in the second region.
  • This structure of troughs arranged successively in a semiconductor substrate has proven itself in magnetotransistors. An arrangement with contact points on a chip surface is obtained, which provides satisfactory results in terms of mechanical and electrical stability.
  • the geometric arrangement with a well-defined position of the contacts the chip surface is particularly advantageous for magnetic field measurement.
  • the first n-doped well provides an insulation layer.
  • the insulating property of the first n-doped well results in an advantageous reduction in the substrate current.
  • the lateral currents, the difference of which is used as the measurement signal when measuring a magnetic field flow above the insulation layer and, because of the greatly reduced substrate current, they provide a stable measurement variable for the magnetic field.
  • the insulation layer has two contacts.
  • the conditions within the doped semiconductor layers can be influenced by applying suitable potentials to the insulation layer, for example by forming barrier layers.
  • the contacts are preferably metal contacts. Metal contacts have proven themselves for the wiring of semiconductor chips.
  • the transition between the first n-doped well and the p-substrate is polarized in the reverse direction. This is achieved by applying the suitable potentials to the electrodes of the first n-doped well and the electrode of the p-doped substrate. If the electrodes of the first n-doped well lie on ground, a negative voltage on the substrate electrode leads to the advantageous barrier layer, which Formation of a vertical parasitic substrate current suppressed.
  • the arrangement has an npnp layer sequence. It is therefore also possible to implement the invention with four layers, so that even with this simpler structure it is possible to significantly increase the sensitivity with regard to a magnetic field measurement compared to the prior art.
  • the vertical parasitic substrate current can also be implemented without the provision of a separate insulation layer.
  • the third region is provided as a p-doped well, that in the third region the second region is provided as an n-doped well and that in the second region the first region is provided as p -doped tub is provided.
  • a structure of troughs arranged successively in a semiconductor substrate is possible, which has proven itself in the case of magnetotransistors. Such a structure is particularly advantageous in terms of stability, production and ease of contact.
  • the third region is preferably partially surrounded by an insulation region.
  • This isolation area thus defines the collector area of the transistors. It is therefore not necessary to adequately size the collector area into a substrate from the outset. Rather, the size of the collector area can be determined by the insulation area. It is preferred if the insulation region is a p-doped well. In this way, the insulation region which adjoins the substrate forms a "short-circuited" p-region with the latter.
  • the insulation area is realized by Si0 2 insulation.
  • the arrangement can thus be designed flexibly, so that the manufacturing possibilities and the areas of application can be taken into account.
  • transition between the second region and the third region is polarized in the blocking direction. This achieves the advantageous reduction of the substrate current in this embodiment with an npnp layer sequence even without an additional insulation layer adjacent to the substrate.
  • Diffusion gives reliable results, both with regard to the accuracy of the geometry of the arrangement and with regard to the doping concentrations.
  • the arrangement is preferably symmetrical to a plane which is perpendicular to the layer sequence.
  • the accuracy of this symmetry is provided particularly well by a diffusion process. It is useful because in the absence of a magnetic field, identical lateral currents flow in both pnp transistors, while there is a disturbance in the case of an effective magnetic field the symmetry of the current flow comes. As a result, different collector currents can be measured, this difference then serving as a measurement signal for the magnetic field measurement.
  • the arrangement is preferably monolithically integrated with an evaluation circuit. This creates a compact component that is inexpensive to manufacture.
  • the invention further consists in a method for producing an arrangement according to the invention, in which a standard raw wafer is assumed. This is particularly useful with respect to the monolithic integration ', together with an evaluation circuit. Furthermore, the use of standard raw wafers is efficient since they can be purchased.
  • the invention also consists in a method in which a standard raw wafer with a first type of doping with an epitaxial layer of the opposite type of doping is assumed.
  • the epitaxial layer of the opposite type of doping can therefore take on the role of the collector region without having to be diffused into the substrate at the beginning of the manufacturing process.
  • the collector area can be defined by an insulation area.
  • the invention further consists in a method for measuring a magnetic field using an arrangement according to the invention. The method is particularly advantageous for the reason that the substrate current is largely negligible compared to the collector current, and this in a wide temperature range, which demonstrably extends to at least 125 ° C.
  • the method is also advantageous since the sensitivity is increased by avoiding lateral surface currents.
  • the method according to the invention therefore makes it possible to reliably measure particularly small magnetic fields or particularly small changes in the magnetic field.
  • the invention is based on the surprising finding that the inventive embedding of the doped regions provides one another with a magnetotransistor which can be produced cost-effectively and which is distinguished by high sensitivity and good stability. It is possible to greatly reduce the substrate current compared to known component structures without using SOI technology or selective etching of the substrate. Without a complex SSIMT structure, the sensitivity of the arrangement is of the same order of magnitude or even higher than in the case of such structures.
  • FIG. 1 shows an arrangement according to the invention in sectional view
  • Figure 2 shows a further arrangement according to the invention in section
  • Figure 3 shows another arrangement according to the invention in sectional view
  • Figure 4 shows an arrangement of the prior art in a sectional view
  • Figure 5 shows a further arrangement of the prior art in a sectional view.
  • Figure 1 shows an arrangement according to the invention in sectional view.
  • the arrangement is based on a p-doped semiconductor substrate 10.
  • a p-raw wafer can be used, which consists of a p-substrate without an n-epitaxial layer.
  • a first n-doped well 12 is diffused into this p-doped semiconductor substrate 10.
  • a first p-doped well 14 is diffused.
  • a second n-doped well 18 is diffused into the first p-doped well 14.
  • a second p-doped well 16 is diffused into this second n-doped well 18.
  • the second p-doped well 16 serves as an emitter zone.
  • the second n-doped well 18 serves as the base zone.
  • the first p-doped well 14 serves as a collector zone. There are two metal contacts 22, 26 on the collector zone 14, which are used as collector electrodes. On the second n-doped well 18 there are two metal contacts 28, 30, which are used as base electrodes. There is a metal contact 24 on the second p-doped well 16, which is used as an emitter electrode.
  • the first n-doped well 12 serves as an insulation layer. This insulation layer has two metal contacts 42, 44.
  • a metal contact 20 is also arranged on the p-doped substrate 10.
  • suitable potentials to the collector electrodes 22, 26, the electrodes 42, 44 of the insulation layer 12 and the electrode 20 of the p-substrate 10, so that the respective semiconductor junctions 14, 12 and 12, 10 are polarized in the reverse direction significantly reduce the parasitic vertical substrate current 40. If negative voltages are applied to the collector electrodes 22, 26 and the electrodes 42, 44 of the insulation layer 12 are grounded, then the transition between the p-doped collector zone 14 and the n-doped insulation layer 12 is in blocking operation.
  • the transition between the n-doped insulation layer 12 and the p-doped substrate 10 is also in blocking operation. There is therefore no vertical parasitic transistor, and only a very small reverse current flows as the substrate current 40, which is smaller in a wide temperature range than the collector current 34, 36 to be called the useful current.
  • the arrangement according to FIG. 1 can be used as a magnetic field sensor as described below. Negative voltages of the same level are applied to the left collector electrode 22 and the right collector electrode 26 with respect to the emitter electrode 24. In the left base electrode 28 and in the right base electrode 30, currents of the same height are fed. As a result, charge carriers (here: holes) of. the p-doped emitter zone 16 injected into the n-doped base zone 18. While a small part of the injected holes in the n-doped base zone 18 recombine with electrons, the majority of the holes continue to flow to the p-doped collector zone 14.
  • charge carriers here: holes
  • the holes first have to flow vertically into the p-doped collector zone 14 and then laterally further to the left collector electrode 22 or to right collector electrode 26. A lateral current flow in the area of the chip surface is therefore avoided.
  • the "orderly" vertical current flow of the holes from the emitter zone 16 through the base zone 18 into the collector zone 14 leads to a high sensitivity to a magnetic field parallel to the chip surface, without the need for SSIMT structures.
  • the relative sensitivity can be greater than 40% / Tesla at room temperature.
  • Figure 2 shows a further arrangement according to the invention in a sectional view.
  • the arrangement is based on a p-doped semiconductor substrate 10.
  • An n-doped epitaxial layer 14, 14 ' is arranged on this p-doped semiconductor substrate 10.
  • a standard IC raw wafer, which consists of a p-substrate and an n-epitaxial layer, can therefore be used as the starting point for the production of this arrangement.
  • a first p-doped well is diffused into the n-epitaxial layer 14, 14 ′ as an insulation layer 46. This encloses the area 14 and separates the remaining area 1 'of the n-epitaxial layer.
  • the insulation layer 46 together with the p-doped substrate 10 forms a "short-circuited" p-region.
  • a p-doped region 18 is diffused into the n-doped region 14 as a trough.
  • An n-doped well 16 is diffused into this p-doped well 18. This serves as an emitter zone.
  • the second p-doped well 18 serves as the base zone.
  • the n-doped well 14 serves as a collector zone. At the collector zone 14 there are two metal contacts 22, 26, which are used as collector electrodes. There are two metal contacts 28, 30 on the p-doped well 18, which are used as base electrodes.
  • a metal contact 24 on the n-doped well 16 which is used as an emitter electrode.
  • two NPN transistors 16, 18, 14 are available on both the left and the right side of the arrangement.
  • a metal contact 20 is also arranged on the p-doped substrate 10.
  • Figure 3 shows a further arrangement according to the invention in a sectional view.
  • the arrangement is also based on a p-doped semiconductor substrate 10.
  • a p-type raw wafer which consists of a p-type substrate without an n-epitaxial layer, can therefore be used as the starting point for the production of this arrangement.
  • An n-doped well 14 is diffused into this p-doped semiconductor substrate 10.
  • a p-doped region 18 is diffused into the n-doped region 14 as a trough.
  • An n-doped well 16 is diffused into this p-doped well 18. This serves as an emitter zone.
  • the second p-doped well 18 serves as the base zone.
  • the n-doped well 14 serves as a collector zone. At the collector zone 14 there are two metal contacts 22, 26, which are used as collector electrodes. There are two metal contacts 28, 30 on the p-doped well 18, which are used as base electrodes. There is a metal contact 24 on the n-doped well 16, which is used as an emitter electrode. Thus, two NPN transistors 16, 18, 14 are available on both the left and the right side of the arrangement. Furthermore, a metal contact 20 is also arranged on the p-doped substrate 10. By applying suitable potentials to the collector electrodes 22, 26 and the electrode 20 of the p-substrate 10, so that the semiconductor junction 14, 10 in Polarity is reversed, the parasitic vertical substrate current 40 can be significantly reduced.
  • the lowest potential is applied to the electrode 20 of the p-doped substrate 10. If a positive potential is applied to the electrodes 22, 26 of the collector region 14, the transition between the n-collector region 14 and the p-substrate 10 is polarized in the blocking direction. If a higher potential is applied to the electrodes 22, 26 of the collector region 14 than to the electrodes 28, 30 of the base region 18, the transitions between the n-collector region 14 and the p-base region 18 are also polarized in the blocking direction. There is therefore no vertical parasitic transistor, and only a very small reverse current flows as the substrate current 40, which in a wide temperature range is smaller than the collector current 34, 36 to be called the useful current.
  • FIG. 2 and FIG. 3 can be used as a magnetic field sensor as described below.
  • Positive voltages of the same level are applied to the left collector electrode 22 and the right collector electrode 26 with respect to the emitter electrode 24.
  • Positive currents of the same height are fed into the left base electrode 28 and the right base electrode 30.
  • charge carriers here: electrons
  • the electrons must first flow vertically into the n-doped collector zone 14 and then laterally further to the left collector electrode 22 or to the right collector electrode 26. A lateral current flow in the region of the chip surface is therefore avoided.
  • the "orderly" vertical current flow of the electrons from the emitter zone 16 through the base zone 18 into the collector zone 14 leads to high sensitivity to a magnetic field parallel to the chip surface, without the need for SSLMT structures.
  • the relative sensitivity at room temperature can be greater than 40% / Tesla.
  • FIG. 1, FIG. 2 and FIG. 3 are symmetrical with respect to a plane of symmetry 32, both with regard to their geometry and with regard to the doping concentrations.
  • the consequence of this is that the currents 34, 36 are identical in magnitude in the absence of a magnetic field component parallel to the chip surface.
  • the difference in the lateral currents 34, 36 resulting from a magnetic field and the resulting difference in the collector currents can therefore be used as a measurement signal for a magnetic field.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Measuring Magnetic Variables (AREA)

Abstract

L'invention concerne un ensemble comportant un magnétotransistor avec un substrat semi-conducteur (10) dopé sur lequel se trouve une série de couches de semi-conducteurs (12, 14, 18, 16) dopées. Sur la surface dudit ensemble, deux contacts électriques sont à disposition, de telle sorte que l'on peut réaliser avec cet ensemble au moins deux transistors, une première zone (16) de la surface de cet ensemble présentant un premier type de dopage (n ou p) et étant intégrée dans une seconde zone (18) de ladite surface, qui présente un second type de dopage (p ou n), et cette seconde zone (18), laquelle présente le second type de dopage (p ou n), étant incorporée dans une troisième zone (14) de la surface de l'ensemble, laquelle présente le premier type de dopage n ou p. Le premier type de dopage (n ou p) est différent du second type de dopage (p ou n). L'invention concerne en outre un procédé permettant de réaliser un ensemble selon l'invention, ainsi qu'un procédé pour mesurer un champ magnétique.
PCT/DE2001/002535 2000-07-25 2001-07-07 Ensemble comportant un magnetotransistor, procede de production d'un ensemble comportant un magnetotransistor et procede pour mesurer un champ magnetique WO2002009193A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2000136007 DE10036007B4 (de) 2000-07-25 2000-07-25 Anordnung mit einem Magnetotransistor, Verfahren zum Herstellen einer Anordnung mit einem Magnetotransistor und Verfahren zum Messen eines Magnetfeldes
DE10036007.6 2000-07-25

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Publication number Priority date Publication date Assignee Title
EP1620742A2 (fr) 2003-04-28 2006-02-01 Knowles Electronics, LLC Systeme et procede de detection d'un champ magnetique
DE102004016992B4 (de) * 2004-04-02 2009-02-05 Prema Semiconductor Gmbh Verfahren zur Herstellung eines Bipolar-Transistors

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US4999692A (en) * 1987-05-12 1991-03-12 The Governors Of The University Of Alberta Semiconductor magnetic field sensor
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US4292642A (en) * 1978-01-18 1981-09-29 U.S. Philips Corporation Semiconductor device
EP0097850A1 (fr) * 1982-06-15 1984-01-11 LGZ LANDIS & GYR ZUG AG Capteur de champ magnétique
US4999692A (en) * 1987-05-12 1991-03-12 The Governors Of The University Of Alberta Semiconductor magnetic field sensor
JPH04320065A (ja) * 1991-04-18 1992-11-10 New Japan Radio Co Ltd トランジスタ型磁気センサ
US5837590A (en) * 1994-09-22 1998-11-17 Texas Instruments Incorporated Isolated vertical PNP transistor without required buried layer

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KORDIC S: "SENSITIVITY OF THE SILICON HIGH-RESOLUTION 3-DIMENSIONAL MAGNETIC-FIELD VECTOR SENSOR", TECHNICAL DIGEST OF THE INTERNATIONAL ELECTRON DEVICES MEETING LOS ANGELES , DEC 7-10 1986, NEW YORK,IEEE,US, pages 188 - 191, XP000012523 *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 156 (E - 1341) 26 March 1993 (1993-03-26) *
SCHNEIDER M ET AL: "INTEGRATED FLUX CONCENTRATOR IMPROVES CMOS MAGNETOTRANSISTORS", PROCEEDINGS OF THE WORKSHOP ON MICRO ELECTRICAL MECHANICAL SYSTEMS. (MEMS). AMSTERDAM, JAN. 29 - FEB. 2, 1995, NEW YORK, IEEE, US, vol. WORKSHOP 8, 29 January 1995 (1995-01-29), pages 151 - 156, XP000555259, ISBN: 0-7803-2504-4 *

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