Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
  • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/528—Layout of the interconnection structure
  • H01L23/5283—Cross-sectional geometry
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• This invention relates to integrated circuit devices using copper for interconnecting discrete circuit components as part of the back-end-of-the-line processing of semiconductive silicon wafers, and particularly, to modifications in wafer processing needed to protect the copper during chemical etching when the via is etched before the trench in a dual Damascene process.
• Copper is a very viable material as the back-end-of-the-line metal when the single or dual Damascene processes are used.
• the Damascene process makes use of a series of trenches formed in an insulating layer. After the trenches are overfilled with copper, a chemical mechanical polishing process (CMP) is used to remove the overfill.
• CMP chemical mechanical polishing process
• Trenches are to be distinguished from vias. Trenches are extended grooves, typically extending parallel to the top surface of the silicon chip, that are patterned to interconnect circuits on the same level of the back-end-of-the-line process whereas vias are holes, typically extending normal to the surface, that are patterned to connect the metal lines from layer to layer.
• Present technology uses a 'trench first' approach.
• the 'via first' approach was compromised because of the need for multiple layers of a relatively thick silicon nitride film.
• the silicon nitride which protected the copper during processing had to, by necessity, remain behind in many of the active areas. These silicon nitride layers, however, resulted in a substantial increase in the dielectric properties of the stack and degraded the performance of the circuit. If the silicon nitride films were made thinner, they would degrade during the via etch. Also, the via etch could etch into the oxide that defines the trench. Even small changes in the line definition can cause serious reliability problems when 0.25um ground rules are in place.
• silicon nitride is used both as a protective layer for the copper and as an etch stop.
• the 'trench first' approach also has its limitations. These limitations are associated with the photolithographic processing of the wafer. The difficulties occur when the trench configurations lead to differences in photoresist thicknesses. The thickness variations are seen in either broad trenches (wide lines) or very dense trenches (closely spaced narrow lines) as required, for example, by DRAMS and cause printing distortions of the via images.
• the present invention seeks to provide a protective layer of silicon nit ⁇ de over the copper while using a novel approach for assuring that the silicon nitride is not damaged during the simultaneous etching of the vias and trenches.
• This invention relates to the use of the preferred 'via first' approach for forming vias (openings, holes) and trenches (grooves) in a passivating layer by using the double Damascene process.
• a contact metallurgy is deposited into a patterned glass layer (e.g., boron phospho silicate glass (BPSG)] and the glass is planarized.
• BPSG boron phospho silicate glass
• a different insulating material such as silicon oxide, is then deposited onto the glass layer and patterned to form shallow via openings aligned with the contacts. The vias are filled with copper and the surface is planarized with a chem-mech polish.
• a thin silicon nitride layer is deposited onto the planarized insulator surface to act as a barrier layer/etch stop.
• An Si ⁇ 2 layer is deposited over the silicon nitride layer and patterned by a conventional photolithographic technique to form therein via holes aligned with the earlier vias.
• an unconventional use is advantageously made of an anti- reflective coating material (ARC) which is spun onto the wafer.
• the coating of ARC fills the vias and covers the rest of the surface with a thin ARC layer.
• photoresist is spun onto the wafer and patterned to form the trench configuration.
• the Si ⁇ 2 layer, which contains the vias, is etched again to form the trenches.
• the ARC material is also etched but at a rate different from the SiO2-
• This ARC plug protects the silicon nitride from degrading which, in turn, protects the underlying copper because the etchant never comes into contact with the copper.
• one feature of the invention is the use of a silicon nitride film to protect the copper during the etching of the insulating layers.
• this silicon nitride layer should be thin so that the increase in the dielectric properties of the stack is kept to a minimum.
• Another feature of the invention is on the use of an anti-reflective coating (ARC) to protect the silicon nitride layer.
• ARC anti-reflective coating
• photoresist materials are used as protective layers in addition to providing a photolithographic medium for component definition of the silicon, insulators and metals.
• a related feature of the invention involves the etching of the ARC layer so as to insure that it is not entirely removed from the vias. After the etching of the vias and trenches has been completed, the ARC coating is removed as part of the photoresist strip process.
• the present invention is directed to a method for forming over a semiconductive wafer, which contains therein and/or thereon devices having conductive contact regions, an interconnection pattern that uses copper in at least some vias and some trenches through insulating layers overlying a top surface of the semiconductor wafer.
• the method comprises the steps of: forming a first insulating layer over the device; forming vias from a top surface of the first insulating layer therethrough with the vias being in communication with the contact regions of the device; filling the vias with a conductor; forming a second insulating layer over the first insulating layer; forming vias through the second insulating layer which are in communication with the conductor filled vias in the first insulating layer; filling the vias through the second insulating layer with copper; forming a third insulating layer over a top surface of the second insulating layer; forming a fourth insulating layer over a top surface of the third insulating layer, the fourth insulating layer having a different etch characteristic than the third insulating layer; patterning and etching the fourth insulating layer to form vias therethrough which are separated from the copper-filled vias through the second insulating layer by the third insulating layer but are aligned with the vias through the second insulating layer; forming an anti
• the present invention is directed to a method for forming over a semiconductive wafer an interconnection pattern that is in insulating layers overlying the semiconductive wafer and that includes copper lines in trenches extending parallel to a top surface of the wafer and copper fill in vias that extend vertically through insulating layers.
• the method comprises the steps of: forming over a top surface of the semiconductive wafer a first insulating layer; forming trenches in a top surface of the first insulating layer and forming vias, which are in communication with the trenches, from bottoms of the trenches through the first insulating layer such that same are in communication with the contact regions of the device; overfilling the vias and trenches of the first insulating layer with contact metal and planarizing to leave a first planar surface over the semiconductive wafer; forming over the metal-filled first insulating layer a second insulating layer; forming vias and trenches in the second insulating layer and overfilling the vias and trenches with copper; forming a second planar surface on the copper-filled second insulating layer; forming a silicon nitride layer over the planarized surface; depositing a third insulating layer over the silicon nitride layer, said third insulating layer having a different etch rate than the silicon nitrid
• FIGS. 1-6 shows a portion of a semiconductive wafer at successive stages of processing in accordance with an exemplary embodiment of the invention to provide metal-filled vias and trenches as parts of the interconnection pattern of conductors of the integrated circuit formed in the semiconductive wafer.
• both vias and trenches be etched into the silicon oxide or silica glass insulating layers between different levels of the conductive interconnection pattern.
• both the vias and trenches are in place before the copper is deposited. It is advantageous to fill both during one deposition process to reduce process complexity. Silicon nitride film that is in place to protect the first level of metal must be removed subsequently so that there is a metal to metal contact between the first level copper lines and the first vias.
• FIG. 1 shows a portion of a silicon wafer 100 over which there has been formed an insulating (dielectric) layer 10, typically of boron phospho silicate glass (BPSG).
• Wafer 100 is shown with an insulated gate field effect transistor formed in and over a top surface 100a thereof.
• the field effect transistor (device) comprises diffused regions 12a and 12c, the drain and source regions, respectively, and a gate region 12b which is over a dielectric gate layer 13 that lies on the top surface 100a of wafer 100 and is centered between the regions 12a and 12c.
• the dielectric layer 13 and gate region 12b are first formed with the region 12b serving as a mask which allows for the regions 12a and 12c to be self aligned to the gate region 12b.
• Conventional photoprocessing is done to pattern layer 10 followed by etch processes to form vias (openings) through layer 10 to expose the diffusion regions 12a and 12c and the gate region 12b.
• vias openings
• trenches are etched into a top surface 10a of layer 10.
• the vias and trenches in the layer 10 are then overfilled with metal 16a, 16b, and 16c, typically tungsten (W), and chem-mech polished to achieve a planar surface 10a.
• Conventional photoresist and etching of the layer 18 provides vias and trenches which are overfilled with copper 22a, 22b, and 22c to provide metal to metal contact with the tungsten 16a, 16b, and 16c, respectively.
• the first Damascene process is completed with a top surface 18a of layer 18 being planarized with a chem-mech polish.
• FIG. 2 shows the wafer 100 after an insulating layer 24, typically 50nm PECVD of silicon nitride, has been deposited onto surface 18a to act as an etch barrier/cap layer, and an insulating layer 26, typically Si ⁇ 2, has been deposited over a top surface 24a of the silicon nitride layer 24.
• Photoresist (not shown) is then spun onto the layer 26. After the photoresist is patterned, the layer 26 is reactively ion etched to open vias 28a, 28b, and 28c.
• a post etch treatment which is used to remove the photoresist and exposed portions of layer 26, stops on the silicon nitride barrier layer 24. This process provides a high degree of selectivity which gives a sharp end point with no reactive ion etch (RIE) lag and allows the vias 28a, 28b, and 28c to be fully opened.
• RIE reactive ion etch
• FIG. 3 shows the wafer 100 after a relatively thin anti-reflexive coating 30 has been spun onto the wafer 100 to cover the surfaces and to fill the vias 28a, 28b, and 28c in layer 26. It is important to insure that the vias 28a, 28b, and 28c are filled so that no voids are present.
• cross sections of a processed wafer show that the ARC material fills the trenches 28a, 28b, and 28c to about three fourths of its height.
• the ARC material grade 1100A
• the ARC material is baked (first at 95 °C and then at 180 °C) and non-selectively RIE'd from the surface of the Si ⁇ 2 26 with C4F8 + O2 for 40 seconds.
• a layer of photoresist 32 typically DUV30 MCSIII/JSR 130/6250, is then spun onto the wafer 100 and patterned to result in openings 31a, 31b, and 31c which expose portions of layer 30.
• Opening 31a which is wider than via 28a, is located over and in communication with via 28a.
• Opening 31b, which is wider than via 28b is located over and in communication with via 28b.
• Opening 31c which is wider than via 28c, is located over and in communication with via 28c.
• a low selective reactive ion etch uses a combination of C4F8, Ar, and O2, is used to etch the exposed portions of ARC layer 30 to expose portions of layer 26 which are then also etched. This results in the formation of trenches 36a, 36b, and 36c which are in communication with vias 28a, 28b, and 28c, respectively.
• FIG. 4 shows that ARC plugs 30a, 30b, and 30c remaining in the bottom of the vias 28a, 28b, and 28c, respectively, after this etch. This is because the ARC material is removed at a slower rate than the Si ⁇ 2 of layer 26. This prevents the Si ⁇ 2 etching ambient from touching the silicon nitride layer 24.
• FIG. 4 also shows that oxide layer 26 has been etched to integrate the trenches 36a, 36b, and 36c with the vias 28a, 28b, and 28c, respectively.
• the etching of the oxide layer 26, when the ARC material 30 is in the vias, is achieved without the formation of 'fences' by tailoring the etch process to be compatible with the etching of both the Si ⁇ 2 and the ARC material instead of just the Si ⁇ 2- Fences are formed when the etchant removes material from the via at different rates depending on the material location. For example, it is possible to find a different etch rate for the ARC material in the center of the via when compared with the ARC material at the ARC/oxide interface.
• a post etch treatment for 20-40 seconds removes the remaining ARC material 30a, 30b, and 30c from the vias 28a, 28b, and 28b, respectively.
• the silicon nitride layer 24 is then selectively etched away using CHF3 + O2 for about 35 seconds. It is to be noted that ⁇ all of the trenches, although wider than the vias in which they are in communication, do not have to extend over more than one side of a via. After the normal cleaning steps have been completed the structure of FIG. 4 is ready for metal fill with copper.
• FIG. 5 shows the wafer 100 after the via/trench openings 28a/36a, 28b/36b have been overfilled with electroplated copper 40.
• FIG. 6 shows the wafer 100 after a resulting top surface 42 has been planarized using a chem-mech polish to remove the excess copper leaving conductors 40a, 40b, and 40c.
• FIG. 6 also illustrates the result of the completed dual Damascene process for this level of metallization.
• the insulating layers can be other than silicon dioxide and the metal contacting the device of the semiconductive body could be aluminum.
• some or all of the trenches need not be used with the vias extending completely through an insulating layer.
• the novel process of the present invention can be implemented starting at the trench portions of the first level of conductors with the metal 16a, 16b, and 16c being tungsten in the vias and being cooper in the trenches.

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• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 2001
  • 2001-07-02 JP JP2002507438A patent/JP2004503089A/ja active Pending
  • 2001-07-02 KR KR10-2002-7018006A patent/KR100474605B1/ko not_active Expired - Lifetime
  • 2001-07-02 WO PCT/US2001/021161 patent/WO2002003457A2/en active IP Right Grant
  • 2001-07-02 TW TW090116395A patent/TW519725B/zh not_active IP Right Cessation

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