JP2004503089A - 銅のメタライゼーションに関するビアファーストのデュアルダマシン法 - Google Patents

銅のメタライゼーションに関するビアファーストのデュアルダマシン法 Download PDF

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Publication number
JP2004503089A
JP2004503089A JP2002507438A JP2002507438A JP2004503089A JP 2004503089 A JP2004503089 A JP 2004503089A JP 2002507438 A JP2002507438 A JP 2002507438A JP 2002507438 A JP2002507438 A JP 2002507438A JP 2004503089 A JP2004503089 A JP 2004503089A
Authority
JP
Japan
Prior art keywords
insulating layer
layer
forming
vias
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002507438A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004503089A5 (enrdf_load_stackoverflow
JP2004503089A6 (ja
Inventor
ブラズ,ガブリエラ
シュレーダー,ウヴェ,パウル
ハロウェイ,ケレン,リン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of JP2004503089A publication Critical patent/JP2004503089A/ja
Publication of JP2004503089A6 publication Critical patent/JP2004503089A6/ja
Publication of JP2004503089A5 publication Critical patent/JP2004503089A5/ja
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2002507438A 2000-06-30 2001-07-02 銅のメタライゼーションに関するビアファーストのデュアルダマシン法 Pending JP2004503089A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60854000A 2000-06-30 2000-06-30
US09/608,541 2000-06-30
PCT/US2001/021161 WO2002003457A2 (en) 2000-06-30 2001-07-02 Via first dual damascene process for copper metallization

Publications (3)

Publication Number Publication Date
JP2004503089A true JP2004503089A (ja) 2004-01-29
JP2004503089A6 JP2004503089A6 (ja) 2004-08-05
JP2004503089A5 JP2004503089A5 (enrdf_load_stackoverflow) 2005-02-03

Family

ID=24436949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002507438A Pending JP2004503089A (ja) 2000-06-30 2001-07-02 銅のメタライゼーションに関するビアファーストのデュアルダマシン法

Country Status (4)

Country Link
JP (1) JP2004503089A (enrdf_load_stackoverflow)
KR (1) KR100474605B1 (enrdf_load_stackoverflow)
TW (1) TW519725B (enrdf_load_stackoverflow)
WO (1) WO2002003457A2 (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102454363B1 (ko) 2020-08-24 2022-10-14 주식회사 세움피엔에프 운동기구의 수평 이동 장치
KR102491980B1 (ko) 2021-01-05 2023-01-27 최순복 필라테스용 레더바렐
CN113394184B (zh) * 2021-06-09 2022-06-17 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
US11876047B2 (en) 2021-09-14 2024-01-16 International Business Machines Corporation Decoupled interconnect structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6127258A (en) * 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2000150644A (ja) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp 半導体デバイスの製造方法
IL147301A0 (en) * 1999-06-30 2002-08-14 Intel Corp Method of projecting an underlying wiring layer during dual damascene processing

Also Published As

Publication number Publication date
WO2002003457A3 (en) 2002-06-06
WO2002003457A2 (en) 2002-01-10
TW519725B (en) 2003-02-01
KR20030020324A (ko) 2003-03-08
KR100474605B1 (ko) 2005-03-10

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