KR100474605B1 - 구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스 - Google Patents

구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스 Download PDF

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Publication number
KR100474605B1
KR100474605B1 KR10-2002-7018006A KR20027018006A KR100474605B1 KR 100474605 B1 KR100474605 B1 KR 100474605B1 KR 20027018006 A KR20027018006 A KR 20027018006A KR 100474605 B1 KR100474605 B1 KR 100474605B1
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KR
South Korea
Prior art keywords
insulating layer
vias
layer
copper
forming
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Expired - Lifetime
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KR10-2002-7018006A
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English (en)
Korean (ko)
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KR20030020324A (ko
Inventor
브라스가브리엘라
슈뢰더우베폴
할로웨이카렌린
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
인피네온 테크놀로지스 아게
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Publication of KR20030020324A publication Critical patent/KR20030020324A/ko
Application granted granted Critical
Publication of KR100474605B1 publication Critical patent/KR100474605B1/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR10-2002-7018006A 2000-06-30 2001-07-02 구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스 Expired - Lifetime KR100474605B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US60854000A 2000-06-30 2000-06-30
US09/608,540 2000-06-30
US09/608,541 2000-06-30
PCT/US2001/021161 WO2002003457A2 (en) 2000-06-30 2001-07-02 Via first dual damascene process for copper metallization

Publications (2)

Publication Number Publication Date
KR20030020324A KR20030020324A (ko) 2003-03-08
KR100474605B1 true KR100474605B1 (ko) 2005-03-10

Family

ID=24436949

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-7018006A Expired - Lifetime KR100474605B1 (ko) 2000-06-30 2001-07-02 구리 금속 배선용 비아 퍼스트 듀얼 다마신 프로세스

Country Status (4)

Country Link
JP (1) JP2004503089A (enrdf_load_stackoverflow)
KR (1) KR100474605B1 (enrdf_load_stackoverflow)
TW (1) TW519725B (enrdf_load_stackoverflow)
WO (1) WO2002003457A2 (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220025480A (ko) 2020-08-24 2022-03-03 주식회사 세움피엔에프 운동기구의 수평 이동 장치
KR20220098929A (ko) 2021-01-05 2022-07-12 최순복 필라테스용 레더바렐

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113394184B (zh) * 2021-06-09 2022-06-17 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
US11876047B2 (en) 2021-09-14 2024-01-16 International Business Machines Corporation Decoupled interconnect structures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904565A (en) * 1997-07-17 1999-05-18 Sharp Microelectronics Technology, Inc. Low resistance contact between integrated circuit metal levels and method for same
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6127258A (en) * 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2000150644A (ja) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp 半導体デバイスの製造方法
IL147301A0 (en) * 1999-06-30 2002-08-14 Intel Corp Method of projecting an underlying wiring layer during dual damascene processing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220025480A (ko) 2020-08-24 2022-03-03 주식회사 세움피엔에프 운동기구의 수평 이동 장치
KR20220098929A (ko) 2021-01-05 2022-07-12 최순복 필라테스용 레더바렐

Also Published As

Publication number Publication date
WO2002003457A3 (en) 2002-06-06
WO2002003457A2 (en) 2002-01-10
TW519725B (en) 2003-02-01
KR20030020324A (ko) 2003-03-08
JP2004503089A (ja) 2004-01-29

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