Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76819—Smoothing of the dielectric

Definitions

• the invention relates to a method for applying a structured insulation layer to a metal layer, in which insulation material is applied to the metal layer, cover material is applied to the insulation layer, and insulation material and cover material are etched in a plasma etching process.
• an insulation layer serves to insulate the lower metal layer from a further upper metal layer subsequently applied to the insulation layer.
• contact openings are introduced into the insulation layer before the upper metal layer is applied.
• An oxide layer TEOS is often used as the insulation layer, which is planarized before the upper metal layer is applied.
• TEOS oxide layer
• FIG. 3a shows a substrate 110 on the left side, on which two structured metal tracks 112 are arranged. After the structuring of this first metal layer 112, an oxide layer (TEOS) 114 is deposited, as is shown on the right side of FIG. 3a.
• TEOS oxide layer
• FIG. 3b shows a first coating of the arrangement for the purpose of planarization.
• the left side of FIG. 3b corresponds to the right side of FIG. 3a.
• FIG. 3c A first plasma etching process is shown in FIG. 3c.
• the left side of FIG. 3c corresponds to the right side of FIG. 3b.
• the lacquer 116 and the oxide layer 114 are etched to a predetermined minimum thickness at approximately the same etching rate.
• the planarized oxide layer 114 shown on the right-hand side of FIG. 3c is thus obtained.
• the plasma etching process is set, for example by a suitable choice of the oxygen concentration, so that the etching rates with respect to the lacquer layer 116 and the oxide layer 114 are as identical as possible. In this way, in the I- If the surface of the lacquer layer 116 is mapped onto the surface of the oxide layer 114.
• FIG. 3d A second oxide deposition is illustrated in FIG. 3d.
• the left side of FIG. 3d corresponds to the right side of FIG. 3c.
• a total oxide layer 114, 118 with an at least almost planar surface is obtained.
• FIG. 3e shows a further step for applying a lacquer layer 120.
• the left side of FIG. 3e corresponds to the right side of FIG. 3d.
• the second lacquering here results in a lacquer layer 120 on the oxide layer 114, 118.
• FIG. 3f shows how the lacquer layer 120 is structured by photolithography.
• the photolithography process creates openings 122 in the lacquer layer 120.
• the left side of FIG. 3f corresponds to the right side of FIG. 3e.
• the final state after a photolithography process is shown on the right-hand side of FIG. 3f, the varnish layer 120 now having openings 122, so that the oxide layer 114, 118 is partially exposed.
• FIG. 3g shows the first step of the plasma etching process for producing the contact holes in the oxide layer 114, 118.
• the left side of FIG. 3g corresponds to the right side of FIG. 3f.
• a first isotropic plasma etching step cools 124 into the surface of the oxide layer 114, 118 in the region of the holes 122 in the lacquer layer 120.
• FIG. 3h illustrates a further plasma etching step. The same situation is shown on the left side of FIG. 3h as on the right side of FIG. 3g.
• the contact holes in the oxide layer 114, 118 are completely etched by an anisotropic etching process, which now consist of an isotropic part 124 and an anisotropic part 126.
• FIG. 3i shows that the remaining lacquer layer 120 is removed by a plasma astrip process.
• the left side of FIG. 3i corresponds to the right side of FIG. 3h.
• the lacquer 120 is removed by the plasma stripping process, so that the result is an oxide layer 114, 118 which is arranged on a metal layer 112 and has partially flattened contact holes 124, 126.
• the flattening of the upper edge of the hole in the area 124 of the contact holes 124, 126 ensures good edge coverage of the further upper metal layer which is later deposited in the respective holes 124, 126.
• the method shown in FIG. 3 provides a well planarized insulation layer; however, due to the large number of process steps, it is very difficult.
• the upper hole edge of the contact holes is only partially flattened. In principle, there is a fear that the likelihood of defects will increase due to the large number of procedural steps.
• the invention builds on the generic method according to claim 1 in that the cover material is structured after it has been applied to the insulation layer and that a plasma etching process is carried out after the structure of the cover material, a structured and planarized insulation layer being produced. It is therefore no longer necessary, according to the present invention, to first carry out a first plasma etching process after applying the covering material to the insulation layer, subsequently to rebuild the oxidation layer by means of a further oxide deposition, to apply a layer of lacquer again and to structure it first in order to achieve the desired structure to introduce the oxide layer. Rather, it is possible to structure the cover material after it has been applied to the insulation layer and to produce the desired structure of the insulation layer in the subsequent plasma etching process. It should be noted that the thickness of the oxide layer is sufficiently large before the top layer is applied; for example, this thickness could correspond approximately to the sum of the oxide layers applied separately in the prior art.
• the cover material is preferably lacquer. Varnishes can be applied to an oxide layer in a simple manner, and they are particularly suitable for representing a mask.
• cover material is structured by photolithography. In this way, the most precise structures can be produced, which are then positively reflected in the precision of tightly packed integrated circuits.
• the insulation layer is preferably an oxide layer (TEOS). Oxide layers have proven themselves as insulation layers in tightly packed integrated circuits.
• the ratio of the cover material etching rate to the insulation material etching rate being 1 + 0.4.
• the plasma etching process has several steps, at least one isotropic depression being etched into the insulation layer in a first step, at least one anisotropic depression being etched into the insulation layer in a second step, one being etched in a third step Planarization takes place and in a fourth step the anisotropic depression is etched into a through hole.
• the contact holes can be designed in a particularly controlled manner.
• a suitable choice of the layer thicknesses and the etching parameters advantageously provides rounded contact holes on their surface.
• the plasma etching process has several steps, the ratio of the cover material etching rate to the insulation material etching rate being greater than 1 in a first step, the cover material being etched primarily and at least one step being defined in the insulation layer, in a second step Step the ratio of the cover material etching rate to the insulation material etching rate is 1 + 0.4, at least one depression being etched into the insulation layer and planarization taking place, in a third step the depression is etched further over a fixed period and in a fourth step the recess is etched into a through hole.
• the first step removal of the covering material can be ensured, while in the second step, by appropriately selecting the ratio of the covering material etching rate to the insulation material etching rate, the etching of a depression in the insulation layer is started and planarization takes place.
• the ratio of the etching rates is no longer decisive; rather, the deepening is etched further over a fixed period.
• the etching rate ratio is irrelevant, and it is only important that the contact holes are etched completely.
• the plasma etching process has several steps, the ratio of the cover material etching rate to the insulation material etching rate being less than 1 in a first step, with at least one step being defined in the insulation layer over a fixed period of time, in a second step the Ver- ratio of the covering material etching rate to the insulation material etching rate is greater than 1, primary covering material being etched, in a third step the ratio of the covering material etching rate to the insulation material etching rate being 1 + 0.4, at least one recess being etched into the insulation layer and planarization taking place, in a fourth step over a fixed period of time the recess is etched further to a through hole and in a fifth step the recess is etched to completion.
• a step is therefore first defined in the insulation layer over a fixed period of time, with only a small amount of covering material being removed by the plasma etching process.
• the insulation material is applied by single deposition.
• it may also be useful to carry out the deposition of the insulation material in several steps, in view of the process economy it is sometimes preferable to use the insulation material to reduce the number of process steps in one step.
• the covering material that remains after the plasma etching process may be removed by plasma strips.
• the actual plasma The etching process can therefore be designed so variably with regard to the applied layer thicknesses and the etching rate ratios that even at the end of the plasma etching process, cover material still remains on the insulation layer. This is then removed by plasma strips.
• the method according to the invention is then further developed by applying a further upper metal layer to the finished arrangement of metal layer and insulation layer.
• the contact holes rounded on the surface are particularly suitable for applying the additional metal layer, since they ensure good edge coverage.
• the method can thus ultimately serve to produce a frequently required multilayer metallization with insulation layers in between.
• the invention is based on the surprising finding that the production process can be simplified by combining the planarizing and the etching of the contact holes. Nevertheless, satisfactory results are obtained, particularly with regard to the shape of the contact holes. By reducing the number of procedural steps in the manufacture of the integrated circuits, the number of defects is reduced, which results in a higher yield.
• the shape of the contact holes can be influenced on the basis of the present invention by varying the process parameters, for example the type of lacquer, the type of implementation of the photolithography, the thickness of the layers and the parameters of the plasma etching process, in particular with regard to the ratio of the Etch rates.
• the desired rounding of the contact holes also results in their widening. This broadening can be compensated for by adapting the dimensions in the exposure mask used in the lithography, which is used in the structuring of the resist mask.
• FIG. 1 cross-sectional sketches of layer sequences which occur in a first embodiment of the method according to the invention
• FIG. 2 cross-sectional sketches of layer sequences which occur in a second embodiment of the method according to the invention.
• FIG. 1 method steps of a first embodiment of the method according to the invention are illustrated by different outlined layer structures.
• FIG. 1 a shows a cross-section of a substrate 10 with two structured metal tracks 12 arranged thereon. This arrangement shown on the left-hand side of FIG Metal tracks 12 an oxide layer 14 is arranged.
• the comparison with the corresponding illustration in FIG. 3a shows that the oxide layer 14 from FIG. 1a has a greater thickness than the oxide layer 114 from FIG. 3a.
• the thickness of the oxide layer 14 can correspond to the sum of the thicknesses of the two deposits of oxide layers of the prior art according to FIG. 3.
• FIG. 1b The application of a lacquer layer 16 is shown in FIG. 1b.
• the left part of Figure 1b corresponds to the right part of Figure la.
• a lacquer layer 16 is shown in addition to the substrate 10, the metal tracks 12 and the oxide layer 14.
• FIG. 1c This illustration is shown again on the left side of FIG. 1c.
• a lithography process is carried out after the application of the lacquer layer 16. This is shown in Figure lc.
• holes 22 can be seen in the lacquer layer which cover the upper Expose the surface of the oxide layer 14 in certain areas.
• FIG. 1d A first step of a plasma etching process is shown in FIG.
• the left side of FIG. 1d corresponds to the right side of FIG. 1c.
• an isotropic etching process takes place, which is chosen to be somewhat shorter than the isotropic etching process of the prior art explained in connection with FIG. 3g.
• the isotropic etching process results in cavities 24 in the surface of the oxide layer 14 in the region of the through holes 22 through the lacquer layer 16.
• FIG. 1 shows an anisotropic etching as a further step in the plasma etching process.
• the left side of the figure le corresponds to the right side of the figure ld.
• An anisotropic depression 26 as a continuation of the cavities 24 is additionally shown on the right in FIG.
• Figure If shows a further step of the plasma etching process for planarization and for further formation of the depressions 24, 26 in the oxide layer 14.
• the left side of the figure If corresponds to the right side of the figure le.
• a planarized layer sequence of substrate 10, metal tracks 12 and oxide layer 14 with depressions 24, 26 is shown on the right-hand side of FIG. 1f. It can already be seen that the depressions 24, 26 are rounded off on the surface.
• FIG. 1g shows how the arrangement is finally etched.
• the left side of Figure 1g corresponds to the right side of Figure 1f.
• Recesses 24, 26 are developed so that through holes 28 are formed through the oxide layer 14 with advantageously rounded edges.
• the speed of the removal of the respective layers or the ratio of the removal rates depends essentially on the parameters of the plasma etching process. By suitable choice and Variegated ⁇ tion of these parameters, the layers in the various steps selectively and specifically removed, which ultimately improves the precision in the manufacturing process.
• FIG. 2 An example of a multi-stage plasma etching process as part of the method according to the invention, in which the parameters of the etching process are changed during the method, is shown in FIG. 2.
• the left side in FIG. 2a corresponds to the left side in FIG.
• the planarization step shown in FIG. 2a is carried out by plasma etching.
• the etching parameters are set such that the lacquer layer 16 is preferably etched. Only one step 30 is etched into oxide layer 14. On the right-hand side of FIG. 2a it can be seen that the lacquer layer 16 has already been significantly removed, while only the minor step 30 mentioned is present in the oxide layer.
• FIG. 2b now shows how the process continues with other etching parameters.
• the left representation in FIG. 2b corresponds to the right representation in FIG. 2a.
• the etching parameters are selected so that the lacquer etching rate corresponds approximately to the oxide etching rate. consequently a high degree of planarization is obtained and, at the same time, the depressions 30 are further developed in the oxide layer 14.
• FIG. 2c A further step of the plasma etching process is shown in FIG. 2c.
• the left side of Figure 2c corresponds to the right side of Figure 2b.
• the depressions 30 are developed by further etching; the result is shown on the right side of FIG. 2c. Now the etching rates are no longer critical.
• a fixed time can be set for the method step corresponding to FIG. 2c.
• FIG. 2d the depressions 30 are developed into through holes 28.
• the left side of Figure 2d corresponds to the right side of Figure 2c.
• the finished through hole 28 is shown on the right-hand side of FIG. 2d.
• the ratio of the etching rate of lacquer and oxide layer is irrelevant in this process step.
• the layer sequences shown on the right sides of FIG. 1g and FIG. 2d form the starting point for the application of a further metallization layer.
• the contact holes rounded on the surface are particularly suitable for the application of the additional metal layer, since they ensure good edge coverage.
• the method can thus ultimately serve to produce a frequently required multilayer metallization with intermediate insulation layers.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Drying Of Semiconductors (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Laminated Bodies (AREA)

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Publications (1)

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Family Applications (1)

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Citations (4)

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• 2000
  • 2000-06-30 DE DE10031876A patent/DE10031876A1/de not_active Ceased
• 2001
  • 2001-05-22 JP JP2002507434A patent/JP2004503087A/ja active Pending
  • 2001-05-22 WO PCT/DE2001/001956 patent/WO2002003453A1/de active Application Filing
  • 2001-05-22 US US10/312,516 patent/US20030164351A1/en not_active Abandoned
  • 2001-06-18 IT IT2001MI001280A patent/ITMI20011280A1/it unknown

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