WO2001065700A1 - Decoder - Google Patents
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- WO2001065700A1 WO2001065700A1 PCT/JP2001/001417 JP0101417W WO0165700A1 WO 2001065700 A1 WO2001065700 A1 WO 2001065700A1 JP 0101417 W JP0101417 W JP 0101417W WO 0165700 A1 WO0165700 A1 WO 0165700A1
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- WIPO (PCT)
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- decision
- soft decision
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3738—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with judging correct decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3746—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with iterative decoding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
Definitions
- the present invention relates to a decoder that performs a decoding process on encoded data.
- a decoder that performs decoding processing of received data by performing error correction processing involving hard decision processing to determine whether received data is logical '0' or logical '1' Rather than dividing the voltage between the 'L' level representing logic '0' and the 'H' level representing logic '1' into several levels, the actual received data is Since the decoder that decodes the received data has higher error correction accuracy by performing the error correction processing that involves the soft decision processing, the decoder that performs such soft decision processing Is generally used. Also, conventionally, in mobile communication and the like, in order to efficiently transmit a plurality of data through a physically determined channel, a part of the data is coded according to a predetermined rule in a transmitting encoder.
- the decoder on the receiving side receives the data sequence with a part of the data deleted according to the above predetermined rule.
- the deleted data is added, and a data sequence to which the same data is added is received, the added same data is deleted, and the data is decoded by performing error correction processing. I have.
- the communication path in an actual communication system is easily affected by noise due to a situation where the intensity of the received radio wave fluctuates rapidly (fading), and therefore, the received data has an 'L' level representing a logic '0'. And the voltage of the 'H' level representing the logic '1'.
- the error correction accuracy of the decoder involving the above soft decision processing decreases, or the time required to converge to the desired error correction accuracy becomes longer. May be You.
- the reliability of some data in the received data is reduced.
- a data series with added data there may be a case where only the same data with low reliability is selected due to the procedure for deleting the same data according to a predetermined rule.
- the same data with high reliability will be discarded, and as a result, the error correction capability will decrease and the transmitted data will be accurately decoded. It can be difficult.
- Japanese Patent Application Laid-Open No. H10-303059 proposes a technique for correcting a bit sequence after completion of error correction processing.
- FIG. 5 is a block diagram of a decoder proposed in Japanese Patent Application Laid-Open No. 10-37059.
- the decoder 100 shown in FIG. 5 includes a demodulation unit 110, a Viterbi decoding unit 120, a CRC unit 130, and a bit inversion unit 140.
- Received data Y modulated by a predetermined modulation scheme is input to demodulation means 110 in a predetermined data sequence unit.
- the demodulation means 110 demodulates the input received data Y, generates soft decision data based on the amplitude and phase of the waveform representing the received data Y, and sends it to the Viterbi decoding means 120. Output to
- the Viterbi decoding means 120 performs error correction processing on the basis of the soft decision data output from the demodulation means 110 in accordance with a predetermined algorithm predetermined with the transmitting side, and generates a bit sequence.
- the data is decoded, the reliability information is added to the data of the bit sequence, and the data is output to the CRC means 130.
- the CRC means 130 performs a CRC check on the input bit sequence data. As a result of the CRC test, if it is determined that there is no error, the data of the bit sequence is output as decoded data D. On the other hand, when it is determined that there is an error, the data of the bit sequence is output to the bit inversion means 140.
- the bit inversion means 140 performs bit inversion on the input bit series data in the order of decreasing the sum of the reliability information of the bit to be inverted to form a new bit.
- the sequence data is generated and fed back to the CRC means 130. In this way, the processing by the CRC means 130 and the bit inversion means 140 is repeated until it is determined that there is no error, thereby improving the error correction accuracy and converging to the desired error correction accuracy. The time required to do so is reduced.
- the repetition processing by the CRC means 130 and the bit inversion means 140 is used because it is based on the bit sequence data subjected to the hard decision processing from the Viterbi decoding means 120. It does not consider the characteristics of the demodulation algorithm, and therefore lacks the accuracy of error correction. In addition, the number of bit inversions may increase, and the time required for the entire decoding process may increase. Disclosure of the invention
- the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a decoder that can enhance error correction capability and decode data with high accuracy.
- a first decoder among the decoders of the present invention that achieves the above object is an error correction processing unit that performs an error correction process involving a soft decision process, and a hard decision result determination unit that determines whether the hard decision result is correct or not.
- a soft-decision data correction unit that forcibly corrects low-reliability data in the data series over a period of time indicating high reliability
- the first decoder of the present invention forcibly corrects low-reliability data among soft-decision data to data indicating high reliability and performs error correction processing.
- the error correction process is performed according to a predetermined algorithm determined in advance. Therefore, it is expected that the effect of bit inversion will appear in multiple correction bits compared to the conventional technology for inverting the bits of a bit sequence that has been subjected to hard decision processing, reducing error correction accuracy and processing time. Is achieved.
- the soft-decision data correction unit corrects data having higher reliability in order from data having lower reliability. .
- the soft decision data correction unit corrects the data by a predetermined number of times even when the hard decision result determination unit determines that the hard decision result is incorrect. You may.
- the processing is rounded up a predetermined number of times, thereby shortening the processing time.
- a second decoder among the decoders of the present invention that achieves the above object is a soft decision data generation unit that demodulates received data to generate soft decision data;
- An identical data detector for detecting a plurality of identical data,
- one soft decision data corresponding to the same data is obtained.
- An error correction processing unit for performing an error correction process on the soft decision data processed by the same data processing unit.
- the transmission order of the original data is basically random due to in-leave processing and the like. For this reason, even if the reliability of certain data among the plurality of identical data in the received data is reduced due to the occurrence of faging, etc. Data reliability is often high.
- the second decoder of the present invention has been made focusing on this point of view.
- the second decoder of the present invention obtains one piece of soft decision data from a plurality of pieces of soft decision data corresponding to a plurality of pieces of the same data in received data, and performs error correction on the one piece of soft decision data. Because processing is performed, fusing on the communication path Even if the reliability of one of a plurality of repeatedly transmitted identical data in the received data is low, an error occurs using other highly reliable data. Correction processing is performed. Therefore, the error correction capability is enhanced, and data can be decoded with high accuracy.
- the same data processing unit may generate a plurality of soft decision data corresponding to a plurality of the same data generated by the soft decision data generation unit. It is preferable that the soft decision data having the highest reliability among them is adopted as one soft decision data corresponding to the same data.
- the soft decision data having the highest reliability among the plurality of soft decision data the soft decision data for performing the error correction process can be easily obtained.
- the same data processing unit may generate an average value of a plurality of soft decision data corresponding to a plurality of the same data generated by the soft decision data generation unit. It is also a preferred embodiment that the data is adopted as one piece of soft decision data corresponding to the same data.
- soft decision data for performing error correction processing can be obtained with high accuracy.
- the second decoder includes a hard decision processing unit that obtains a hard decision result of the soft decision data generated by the soft decision data generation unit,
- Soft decision data corresponding to the same data may be generated.
- FIG. 1 is a block diagram of the decoder according to the first embodiment of the present invention.
- FIG. 2 is a block diagram of a decoder according to the second embodiment of the present invention.
- FIG. 3 is a block diagram of a decoder according to the third embodiment of the present invention.
- FIG. 4 is a block diagram of a decoder according to the fourth embodiment of the present invention.
- FIG. 5 is a block diagram of a decoder proposed in Japanese Patent Application Laid-Open No. 10-37059. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram of the decoder according to the first embodiment of the present invention.
- the decoder 10 shown in FIG. 1 includes a demodulator 11, a memory 12, a soft decision decoder 13, an error correction processor 14, a CRC 15, and data correction control. Part 16 is provided.
- Received data Y modulated by a predetermined modulation scheme is input to demodulation section 11 in error correction block units.
- the demodulation unit 11 demodulates the input received data Y and generates soft decision data based on the amplitude and phase of the waveform representing the received data Y.
- the soft-decision data of 7 values in which the voltage between the 'L' level voltage representing logic '0' and the 'H' level voltage representing logic '1' is divided into seven levels of voltage Description will be made assuming that 0 to 6 are handled.
- the soft-decision data 6,0 corresponds to data indicating high reliability according to the present invention
- the soft-decision data 3 corresponds to low-reliability data.
- the soft decision data generated by the demodulation unit 11 is sorted in the order of smaller distance (lower reliability) from the soft decision data 3, which is the intermediate data, and is stored in error correction block units.
- the distance between soft decision data 4 and the intermediate data is 4 to 3 and 1
- the distance between soft decision data 6 and the intermediate data is 6 ⁇ 3 and 3 Yes
- soft-decision data 4 has a smaller distance from intermediate data than soft-decision data 6. Therefore, in the memory 12, the soft decision data 4 and the soft decision data 6 are stored in this order, that is, in the order of low reliability.
- memory 1 2 Alternatively, other data storage means such as a register may be used.
- the soft-decision data correction unit 13 corrects the soft-decision data in error correction block units as described later. At the first time, one block of soft decision data from the memory 12 is output to the error correction processing unit 14 as it is.
- the error correction processing unit 14 performs error correction processing on one block of soft decision data output from the soft decision data correction unit 13 according to a predetermined algorithm predetermined with the transmitting side. Outputs a binary bit sequence.
- the CRC unit 15 performs a CRC check of the bit sequence data, and if it determines that there is no error, outputs the bit sequence data as decoded data D. On the other hand, when it is determined that there is an error, the fact is transmitted to the data correction control circuit 16.
- the soft decision data correction unit 13 When the data correction control circuit 16 receives from the CRC unit 15 that it is determined that there is an error, the soft decision data having the lowest reliability among the soft decision data for one block described above (The soft-decision data correction unit 13 is controlled so that the soft-decision data having the smallest distance from the intermediate data) is corrected to the soft-decision data 6 with high reliability.
- the soft decision data correction unit 13 corrects the soft decision data having the lowest reliability into the soft decision data 6.
- the soft-decision data for one block corrected by the soft-decision data correction unit 13 is subjected to error correction processing again by the error correction processing unit 14 according to a predetermined algorithm. As a result, new bit sequence data is generated, and then the CRC check is performed again in the CRC unit 15.
- the new bit sequence data is output as decoded data D.
- the fact is transmitted to the data correction control circuit 16.
- the data correction control circuit 16 When the data correction control circuit 16 receives again from the same unit 15 that it is determined that there is an error, the data correction control circuit 16 replaces the soft decision data with the lowest reliability with the other high reliability data.
- the soft decision data correction unit 13 is controlled to correct the soft decision data to 0.
- the soft decision data correction unit 13 corrects the soft decision data having the lowest reliability to the soft decision data 0, then performs error correction processing in accordance with a predetermined algorithm in the error correction processing unit 14, and performs CRC correction in the CRC unit 15. Perform CRC check. If it is determined that there is no error, the bit sequence is output as decoded data D.
- the soft-decision data with the lowest reliability next to the soft-decision data with the lowest reliability described above are corrected to 6,0 Correct one after another in the order of the judgment data. Even if it is determined that there is an error, the decoding result may be obtained by performing correction a predetermined number of times. In this way, the processing time is short.
- bit sequence data for one block contains more than one soft decision data to be corrected
- some or all of the soft decision data to be corrected may be corrected. May be. If all are corrected at the same time, the processing time will be shorter.
- the soft decision data having low reliability is forcibly corrected to 6,0, which is a soft decision data indicating that the reliability is high, and a predetermined value determined in advance with the transmission side is used.
- Error correction processing is performed according to the algorithm. Therefore, compared with the conventional technique of inverting the bits of the bit sequence subjected to the hard decision processing, the error correction accuracy is further improved and the processing time is further shortened.
- the error when it is determined that there is an error by the CRC check, the error is corrected by forcibly correcting the soft decision data 6, 0 indicating that the reliability is high in the order of the soft decision data having the low reliability. Corrections are made. Therefore, the error correction processing is performed efficiently in the order of the uncertain data, and the processing time is further reduced.
- error correction processing is performed by correcting soft decision data 6, 0 in the order of soft decision data having low reliability for all soft decision data, but has the lowest reliability.
- the error correction processing may be performed by correcting only the soft decision data to the soft decision data 6,0. It is not only possible to correct soft decision data with low reliability to 6,0, but also to intermediate data such as 4,5. In this way, the processing time can be further reduced.
- FIG. 2 is a block diagram of the decoder according to the second embodiment of the present invention.
- the decoder 20 shown in FIG. 2 includes a demodulation unit 21, a repetition bit detection & grouping unit 22, a repetition bit processing unit 23, and an error correction processing unit 24.
- the demodulation unit 21 corresponds to the soft decision data generation unit according to the present invention.
- This demodulation unit 2 1 Receive data Y is input.
- the received data ⁇ is repeatedly processed for the same data on the transmitting side, and the data is sequentially written to a memory and then read out from the memory by a predetermined algorithm, thereby stirring the order of the data.
- This is a data sequence that is processed and further modulated by a predetermined modulation method.
- the demodulation unit 21 demodulates the received data ⁇ and generates a soft decision based on the amplitude and phase of the waveform representing the received data ⁇ .
- a seven-value soft decision data is obtained by dividing the voltage between the 'L' level voltage representing logic '0' and the 'H' level voltage representing logic '1' into seven levels of voltage. Evening 0 to 6 will be explained. Typically, soft decision data 6,0 corresponds to data with high reliability, and soft decision data 3 corresponds to data with low reliability.
- the repetitive bit detection & grouping unit 22 corresponds to the same data detection unit according to the present invention.
- the soft decision data from the demodulation unit 21 is input to the repetitive bit detection & grouping unit 22.
- the repetitive bit detection & grouping unit 22 detects which soft decision data bits of the input soft decision data are repeated according to the above-described algorithm, and detects the detected bit values.
- the soft decision data is grouped into one group.
- the repetitive bit processing unit 23 corresponds to the same data processing unit according to the present invention, and among the soft decision data grouped into one, the soft decision data having the highest reception level, that is, The soft decision data with the highest reliability among the plurality of soft decision data corresponding to the same data is adopted as one soft decision data corresponding to the same data.
- soft-decision data grouped into one 6,..., 3,..., 5,..., 5,..., 6 (... is the data due to the interleaved effect, 3 is the fading or
- the soft decision data 6 that is the longest distance from the soft decision data 3, which is the intermediate data is used. In this way, only one soft decision data with the highest reliability is adopted from one group.
- the error correction processing section 24 performs error correction processing using the highly reliable soft decision data 6 output from the repetition bit processing section 23 by a known technique such as Viterbi decoding or one-point decoding. To generate binary bit sequence data, A CRC check of the bit sequence is performed, and if no error is determined, the bit sequence data is output as decoded data D. On the other hand, when it is determined that there is an error, the error correction processing unit 24 further performs error correction.
- the decoder 20 of the present embodiment obtains one piece of soft decision data from a plurality of pieces of soft decision data corresponding to the same data in the received data Y, and Since error correction processing is performed for the soft decision data, if the communication path includes a section where the radio wave condition is poor due to fading, etc., the received data Y out of a plurality of identical data repeatedly transmitted Even if the reliability of certain data is low, the error correction process is performed using the data with the highest reliability. Therefore, the error correction capability is enhanced, and data can be decoded with high accuracy. Also, the repetition bit processing unit 23 outputs the soft decision data having the highest reliability among the plurality of soft decision data corresponding to the plurality of identical data generated by the demodulation unit 21 to the same data. Since it is adopted as one soft decision data corresponding to the evening, soft decision data for performing error correction processing can be easily obtained.
- FIG. 3 is a block diagram of a decoder according to the third embodiment of the present invention.
- the decoder 30 shown in FIG. 3 is different from the decoder 20 of the first embodiment in the repetitive bit processing unit 33.
- the repetitive bit processing unit 33 converts the average value of the plurality of soft decision data corresponding to the plurality of identical data generated by the demodulation unit 21 into one soft value corresponding to the same data. Adopted as judgment data.
- the error correction processing unit 24 performs error correction using the soft decision data 5 to convert the binary bit sequence data. Generate and perform CRC check to obtain decoded data D.
- the repetitive bit processing unit 33 since the repetitive bit processing unit 33 employs an average value of a plurality of soft decision data, it is necessary to perform error correction processing. The accuracy of the soft decision data increases. Further, a decoder according to a fourth embodiment of the present invention will be described.
- FIG. 4 is a block diagram of a decoder according to the fourth embodiment of the present invention.
- the decoder 40 shown in FIG. 4 is provided with a hard decision processing unit 45 that obtains a hard decision result during a soft decision. Also, based on the hard decision result in the hard decision processing unit 45 of the plurality of soft decision data corresponding to the plurality of identical data generated by the demodulation unit 21, the soft decision corresponding to the same data is performed. A repetitive bit processing unit 43 for generating data is also provided.
- the decoder 40 determines whether all of the soft decision data grouped into one by the iterative bit detection & grouping unit 22 is logical '0' or logical '1' in the hard decision processing unit 45. Then, the result of the hard decision and the soft decision data received from the iterative bit detection & grouping unit 22 are repeated and passed to the bit processing unit 43. Then, the repetitive bit processing unit 43 employs soft decision data corresponding to the logic having the larger number of the logic “0” and the logic “1” that have been subjected to the hard decision processing. For example, when the hard decision processing is performed on the soft decision data 6, 3, 5, 5, and 6 grouped into one, the hard decision data 1,?
- 1, 1, 1 (Since soft decision data 3 is intermediate data, it does not belong to either 0 or 1).
- up to four of the five soft decision data 6, 3, 5, 5, and 6 are determined to be hard decision data 1, so that the soft decision data 6 corresponding to the hard decision data 1 is finally determined.
- an error correction processing section 24 performs error correction processing using the soft decision data 6 to generate a binary bit sequence data, and performs a CRC check to obtain decoded data D.
- the decoder 40 of the fourth embodiment performs hard decision on a plurality of soft decision data and generates soft decision data for performing error correction processing based on the result of the hard decision. Therefore, simple arithmetic processing is required as compared with a case where a plurality of soft-decision data are arithmetically processed to obtain soft-decision data for performing error correction processing.
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- Detection And Prevention Of Errors In Transmission (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01906308A EP1176726A4 (en) | 2000-03-02 | 2001-02-26 | DECODER |
US09/959,339 US7080307B2 (en) | 2000-03-02 | 2001-02-26 | Error correction decoder with correction of lowest soft decisions |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2000056992A JP4319317B2 (ja) | 2000-03-02 | 2000-03-02 | 復号器 |
JP2000-56992 | 2000-03-02 | ||
JP2000058847A JP4319318B2 (ja) | 2000-03-03 | 2000-03-03 | 復号器 |
JP2000-58847 | 2000-03-03 |
Publications (1)
Publication Number | Publication Date |
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WO2001065700A1 true WO2001065700A1 (en) | 2001-09-07 |
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Family Applications (1)
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PCT/JP2001/001417 WO2001065700A1 (en) | 2000-03-02 | 2001-02-26 | Decoder |
Country Status (2)
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EP (1) | EP1176726A4 (ja) |
WO (1) | WO2001065700A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US7577899B2 (en) * | 2006-02-13 | 2009-08-18 | Harris Corporation | Cyclic redundancy check (CRC) based error correction method and device |
CN107086898A (zh) * | 2017-04-19 | 2017-08-22 | 江苏卓胜微电子有限公司 | 联合纠错方法和装置 |
CN108551382B (zh) * | 2018-03-23 | 2021-06-25 | 重庆思柏高科技有限公司 | 一种通信数据纠错方法及装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000165260A (ja) * | 1998-11-27 | 2000-06-16 | Yrp Ido Tsushin Kiban Gijutsu Kenkyusho:Kk | 復号装置 |
JP2000183758A (ja) * | 1998-12-10 | 2000-06-30 | Sony Internatl Europ Gmbh | 復号装置及び復号方法、並びに符号化装置及び符号化方法 |
JP2000201085A (ja) * | 1999-01-05 | 2000-07-18 | Ntt Mobil Communication Network Inc | 符号化方法および復号方法 |
JP2001044855A (ja) * | 1999-08-02 | 2001-02-16 | Matsushita Electric Ind Co Ltd | ターボ復号装置及び繰り返し復号方法 |
-
2001
- 2001-02-26 WO PCT/JP2001/001417 patent/WO2001065700A1/ja not_active Application Discontinuation
- 2001-02-26 EP EP01906308A patent/EP1176726A4/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000165260A (ja) * | 1998-11-27 | 2000-06-16 | Yrp Ido Tsushin Kiban Gijutsu Kenkyusho:Kk | 復号装置 |
JP2000183758A (ja) * | 1998-12-10 | 2000-06-30 | Sony Internatl Europ Gmbh | 復号装置及び復号方法、並びに符号化装置及び符号化方法 |
JP2000201085A (ja) * | 1999-01-05 | 2000-07-18 | Ntt Mobil Communication Network Inc | 符号化方法および復号方法 |
JP2001044855A (ja) * | 1999-08-02 | 2001-02-16 | Matsushita Electric Ind Co Ltd | ターボ復号装置及び繰り返し復号方法 |
Non-Patent Citations (2)
Title |
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See also references of EP1176726A4 * |
SHIBUTANI A, SUDAA H, ADACHI F: "DECODING-COMPLEXITY REDUCTION ON TURBO-CRC CONCATENATED CODE IN W-CDMA MOBILE RADIO", DENSHI JOHO TSUSHIN GAKKAI RONBUNSHI. B - TRANSACTIONS OF THEINSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATIONENGINEERS. B, DENSHI JOHO TSUSHIN GAKKAI; TSUSHIN SOSAIETI, TOKYO, JP, 8 March 1999 (1999-03-08), JP, pages 540 - 542, XP002947254, ISSN: 1344-4697 * |
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EP1176726A1 (en) | 2002-01-30 |
EP1176726A4 (en) | 2004-10-13 |
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