WO2001061744A1 - Procede de fabrication de dispositif a semi-conducteurs - Google Patents

Procede de fabrication de dispositif a semi-conducteurs Download PDF

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Publication number
WO2001061744A1
WO2001061744A1 PCT/JP2000/000828 JP0000828W WO0161744A1 WO 2001061744 A1 WO2001061744 A1 WO 2001061744A1 JP 0000828 W JP0000828 W JP 0000828W WO 0161744 A1 WO0161744 A1 WO 0161744A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
chip
mounting
element chip
passive element
Prior art date
Application number
PCT/JP2000/000828
Other languages
English (en)
Japanese (ja)
Inventor
Akio Ishizu
Kazutoshi Takashima
Shiro Oba
Yoshihiko Kobayashi
Tsutomu Ida
Shigeru Haga
Susumu Takada
Iwamichi Koujiro
Original Assignee
Hitachi, Ltd.
Hitachi Tohbu Semiconductor, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP2000/000828 priority Critical patent/WO2001061744A1/fr
Priority to AU2000224628A priority patent/AU2000224628A1/en
Priority to TW089106119A priority patent/TW550766B/zh
Priority to AU32308/01A priority patent/AU3230801A/en
Priority to KR1020027010498A priority patent/KR100689129B1/ko
Priority to PCT/JP2001/001091 priority patent/WO2001061754A1/fr
Priority to US10/129,305 priority patent/US6852553B2/en
Priority to CNB018033148A priority patent/CN1222036C/zh
Publication of WO2001061744A1 publication Critical patent/WO2001061744A1/fr
Priority to US10/983,689 priority patent/US6946306B2/en
Priority to US11/178,423 priority patent/US20050250254A1/en

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/481—Disposition
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Definitions

  • the present invention relates to a semiconductor manufacturing technique, and more particularly to a technique that is effective when applied to a method for manufacturing a high-frequency module (high-frequency power amplifier).
  • a high-frequency power amplifying device called a high-frequency module (also referred to as an RF module or an RF power module) in which surface-mounted chip components such as a chip capacitor and a chip resistor and a semiconductor pellet for bare chip mounting are mounted
  • a high-frequency module also referred to as an RF module or an RF power module
  • surface-mounted chip components such as a chip capacitor and a chip resistor and a semiconductor pellet for bare chip mounting are mounted
  • Japanese Patent Application Laid-Open No. H10-128808 (Numanami) describes the structure and electrical characteristics of a high-frequency module and a large number of individual units for assembling a plurality of high-frequency modules collectively. It describes the structure of the substrate and the like.
  • a method of mounting a cap on a hybrid IC is described in, for example, Japanese Patent Application Laid-Open No. Hei 6-307207 (Morizumi). It describes how to attach caps to singulated substrates.
  • Japanese Patent Application Laid-Open No. H10-12808 does not describe marks such as letters and symbols attached to the cap, and further describes a method of attaching the cap to the multi-piece board in detail, a chip component ( There is no description of mounting techniques such as electronic components) and semiconductor pellets, and solder printing and solder potting methods on multi-cavity boards.
  • Japanese Patent Application Laid-Open No. Hei 6-320707 does not describe a method of mounting a cap on a multi-cavity substrate.
  • An object of the present invention is to provide a method for manufacturing a semiconductor device which reduces the number of manufacturing steps and rationalizes a manufacturing line.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device which aims to reduce manufacturing costs. To provide.
  • Still another object of the present invention is to provide a method for manufacturing a semiconductor device which reduces material costs.
  • a method for manufacturing a semiconductor device includes the steps of: disposing a passive element chip and an active element chip on a wiring board and mounting the passive element chip and the active element chip on the wiring board; Attaching a cap with a mark to the wiring board, and covering the passive element chip and the active element chip with the cap.
  • the method of manufacturing a semiconductor device includes the steps of: disposing a passive element chip and an active element chip on a wiring board and mounting the passive element chip and the active element chip on the wiring board;
  • the above-mentioned recognition mark of the cap having the recognition mark on the surface is inspected, and after the inspection, a non-defective product cap is attached to the wiring board, and the passive element chip and the active element chip are covered by the cap. And a process.
  • a non-defective mark, a defective mark, or a cap of a defective mark such as a cap of another mark is attached because a non-defective cap is attached to the wiring board after inspecting the recognition mark of the cap having the recognition mark. Can be prevented.
  • the defective cap for the recognition mark is not attached, so that the production line can be streamlined.
  • the method of manufacturing a semiconductor device of the present invention is a method of mounting a passive element chip and an active element chip on a wiring board of a multi-piece board on which a plurality of wiring boards are formed. Arranging the passive element chip and the active element chip on the wiring board of the multi-piece substrate and mounting the passive element chip and the active element chip on a non-defective wiring board; The cap Covering the passive element chip and the active element chip with the cap by attaching only to a non-defective wiring board.
  • a passive element chip and an active element chip are mounted only on a wiring board of a multi-cavity board that has been inspected, thereby omitting work on this defective portion in a semiconductor device manufacturing process. be able to.
  • a passive element chip and an active element chip are mounted on a wiring board and assembled, and solder is printed on the passive element chip terminals of the wiring board.
  • solder printing After the solder printing, a step of applying solder to the concave portion of the wiring board by potting, a step of disposing the passive element chip on the wiring board, and a step of attaching the active element chip to the wiring board. Arranging the passive element chip and the active element chip on the wiring board by solder connection by performing solder reflow.
  • solder is printed on the passive element chip terminals of the wiring board, and then the solder is applied to the recesses of the wiring board by potting, so that the solder printing is performed first. It is possible to prevent the solder mask from being stained by the solder.
  • the method of manufacturing a semiconductor device includes a step of mounting a passive element chip and an active element chip on a wiring board, and assembling the passive element chip on the wiring board. After disposing the passive element chip, the method includes a step of disposing the active element chip in the recess of the wiring board, and a step of mounting the passive element chip and the active element chip on the wiring board by soldering. Things.
  • the passive element chip and the active element chip are mounted on a wiring board and assembled, and the plurality of wiring boards are defined by dividing grooves. Disposing the passive element chip on the wiring board of the multi-cavity board; and placing the active element chip in a recess of the wiring board. Disposing; mounting the passive element chip and the active element chip on the wiring board by soldering; and avoiding the dividing groove by potting a plurality of recesses of the wiring board. Applying the sealing resin and sealing the active element chip with resin.
  • the method of manufacturing a semiconductor device is characterized in that a passive element chip and an active element chip are mounted on a wiring board and assembled, and the wiring of the multi-piece board on which a plurality of the wiring boards are formed is provided. Disposing the passive element chip and the active element chip on a substrate and mounting the passive element chip and the active element chip on the wiring board; and supporting a hook engageable with the wiring board. Attaching the cap to the multi-piece substrate by obliquely inserting one of the hook supports of the cap provided with the hook support portions facing each other into a hook hole of the multi-piece board. The cap for covering the chip for the passive element and the chip for the active element on the wiring board of the multi-piece substrate.
  • the passive element chip and the active element chip are mounted on a wiring board and assembled, and the passive element chip is arranged on the selected wiring board.
  • the above-mentioned wiring board and the active element chip are mounted in combination so that the characteristics of the semiconductor device fall within an allowable range.
  • FIGS. 1A and 1B are views showing an example of an embodiment of the structure of a high-frequency module assembled by the method for manufacturing a semiconductor device according to the present invention, wherein FIG. 1A is a perspective view, FIG. 1B is a cross-sectional view, and FIG. Fig. 3 is a bottom view showing the structure of the high-frequency module shown in Fig. 3, and Fig. 3 is a manufacturing process diagram showing an example of the assembly procedure in the method for manufacturing the high-frequency module shown in Fig. 1-Fig.
  • FIGS. 3A and 3B are diagrams showing an example of the structure of a substrate to be inserted and a defective mark wiring substrate, (a) is a perspective view of a multi-piece substrate, (b) is a plan view of the defective mark wiring substrate during component mounting inspection, and (c).
  • FIG. 7A is a plan view illustrating a movement trajectory on a wiring board
  • FIG. 7B is a perspective view illustrating a movement trajectory on a multi-cavity board
  • FIG. FIG. 7A is a plan view illustrating a movement trajectory on a wiring board
  • FIG. 7B is a perspective view illustrating a movement trajectory on a multi-cavity board
  • FIG. FIG. 7A is a plan view illustrating a movement trajectory on a wiring board
  • FIG. 7B is a perspective view illustrating a movement trajectory on a multi-cavity board
  • FIG. 3 is a view showing an example of an embodiment of a substrate structure in a solder printing step and a solder potting step of the method of manufacturing a semiconductor device according to the present invention, wherein (a) is a plan view of a multi-piece substrate before solder formation; (B) is the wiring board before solder formation FIG. 8C is a plan view of the wiring board after solder printing and solder potting.
  • FIG. 8 is an embodiment of the structure of the component mounting apparatus used in the component mounting step of the semiconductor device manufacturing method according to the present invention.
  • FIGS. 9A and 9B are views showing an example of the structure, wherein FIG. 9A is an external perspective view, FIG. 9B is a block diagram of the configuration, and FIG.
  • FIG. 1 is a view showing an example of an embodiment, in which (a) is an external perspective view, (b) is a configuration block diagram, and FIG. 10 is a diagram showing a method of manufacturing a semiconductor device according to the present invention.
  • FIG. 1 is a view showing an example of an embodiment of a structure of a substrate.
  • (A) is a plan view of a substrate after mounting components
  • (b) is a plan view of a substrate after mounting a pellet
  • FIG. Of the board structure at the time of component position detection in the automatic appearance inspection process of 1A is a plan view of a multi-piece substrate, FIG.
  • FIGS. 3A and 3B are diagrams illustrating an example of an embodiment of a substrate structure, in which FIG. 3A is a plan view of a multi-piece substrate, FIG. 3B is a plan view of a wiring substrate, and FIG. FIGS. 3A and 3B are diagrams illustrating an example of an embodiment of a structure of a cap used in a cap insertion step, in which FIG. 1A is a plan view, FIGS. 1B and 1C are side views, and FIG. FIG.
  • FIG. 15 shows an example of a method of recognizing hook holes of a multi-piece substrate in a cap insertion step of a method of manufacturing a semiconductor device according to the present invention.
  • (A) is a front view showing a recognition state
  • (b) is a hook hole of a multi-piece board. Plan view, the implementation of cap transferring method in cap ⁇ process of the manufacturing method of FIG. 1 6
  • FIG. 17 is a diagram showing an example of an embodiment of a cap insertion method in a cap insertion step of a method of manufacturing a semiconductor device according to the present invention
  • FIG. FIG. 18B is a principle diagram
  • FIG. 18B is a diagram showing the state of the cap inserted in FIG. 17A
  • FIG. 19 is a method of manufacturing a semiconductor device of the present invention.
  • FIGS. 3A and 3B are views showing an example of a state after a cap is inserted in a cap insertion step of FIG. 1A, wherein FIG. 2A is a front view, FIG. 2B is an enlarged partial cross-sectional view of a wiring board, and FIG. An example of the operation of the cap mounting device after cap insertion in the cap insertion process of the manufacturing method is shown. Operation principle diagram, FIG.
  • FIG. 21 is an output characteristic diagram showing an example of a characteristic inspection result in a characteristic selection step of the semiconductor device manufacturing method of the present invention
  • FIG. 22 is a pellet characteristic inspection of the semiconductor device manufacturing method of the present invention
  • FIG. 14 is a diagram showing a pellet grade showing an example of an inspection result.
  • FIGS. 1 and 2 show the structure of a semiconductor device (high-frequency module 1)
  • FIG. 3 shows a procedure for assembling the high-frequency module 1
  • FIG. This will be described with reference to the cross-sectional view of the wiring board and the drawing of the defective mark wiring board shown in FIG.
  • the semiconductor device assembled by the method for manufacturing a semiconductor device according to the first embodiment shown in FIGS. 1 and 2 is a high-frequency power amplifier, which is called a high-frequency module 1 (also referred to as a high-frequency power module).
  • the cap 4 is superimposed on the main surface (upper surface) of the substrate 2, and has a flat rectangular structure in appearance.
  • semiconductor pellets 21 active element chips
  • chip components 22 passive element chips
  • surface-mounted or surface-mounted components such as surface-mount type chip capacitors and chip resistors and passive components.
  • the outer edge of the cap 4 coincides with or is located inside the outer edge of the wiring board 2.
  • the cap 4 has a structure in which a metal plate is drawn into a rectangular box shape and has a peripheral wall 3 protruding along the lower surface periphery.
  • the cap 4 is provided with hook support arms (hook support portions) 17 protruding downward from the peripheral wall 3 at the center on both sides thereof. Further, inside the tip side of the hook support arm 17, a protruding hook claw 18 also formed by molding is provided. The hook 19 and the hook support arm 17 form a hook 19 which is a locking portion having elasticity.
  • the thickness of the cap 4 is, for example, about 0.1 mm, and is formed of a nickelless nickel silver (an alloy of nickel, copper, and zinc), a nickel-plated phosphor bronze, or the like. This enhances the wettability with the solder.
  • a recess 15 In the center of both sides of the wiring board 2, there is formed a recess 15 in which the hook support arm 17 is disposed. At the bottom of the recess 15 is a further recessed hook 16. The hook claw 18 of the hook 19 is formed and is engaged with the hook portion 16.
  • the hook support arm 17 does not protrude outside the recess 15 when the hook claw 18 is hooked on the hook portion 16.
  • the hook support arm 17 is formed of a metal plate, an elastic force can be applied to the hook 19. Accordingly, the tip of the peripheral wall 3 of the cap 4 comes into contact with the main surface of the wiring board 2, and the hook 4 is elastically hooked on the back surface of the wiring board 2, so that the cap 4 is attached to the wiring board 2. It can be fixed securely.
  • the cap 4 can be easily removed.
  • the locking portion between the wiring board 2 and the cap 4 may have another structure.
  • a plurality of external terminals 5 are provided on the back surface of the wiring board 2, and these external terminals 5 are provided on both sides in the longitudinal direction of the back surface of the wiring board 2. They are arranged at almost constant intervals, and one row (upper row shown in Fig. 2) has, from left to right, an input terminal (P in) 6, a ground terminal (GND) 7, and a ground terminal ( GND) 8 and gate bias terminal (Vg) 9 are provided, and the other column (lower column shown in FIG. 2) has output terminals (P out) 10 from left to right. , A ground terminal (GND) 11, a ground terminal (GND) 12, and a power supply terminal (Vdd) 13 are provided.
  • the side of the wiring board 2 corresponding to the input terminal 6, the gate bias terminal 9, the output terminal 10 and the power supply terminal 13 is arranged from the front side to the back side as shown in FIG.
  • An end face through hole 20 is provided at every position. This is because when mounting the high-frequency module 1 on a mounting board such as a printed wiring board, each external terminal 5 is connected to the electrode portion on the back surface of the wiring board 2 and the through hole 20 on the side face of the side face. As a result, the high-frequency module 1 can be reliably mounted.
  • a region extending so as to partition the four ground terminals 7, 8, 11 and 12 is provided with a mounting bonding material used when mounting the high-frequency module 1 (for example, , Solder) is provided with a resist film 14 made of a material that does not wet.
  • the chip component 22 is mounted on the surface of the wiring board 2, and the recess 2a which is a cavity formed on the surface of the wiring board 2 is provided in the recess 2a.
  • the pellet 21 is mounted via the solder connection part 26.
  • the chip part 22 is formed with a solder fillet 25 to form an electrode for the chip part of the wiring board 2 shown in FIG. 5 (b).
  • 2 b terminal for a chip for passive element
  • the pad which is the surface electrode is connected to the board side terminal of the wiring board 2 by a wire 24 such as a gold wire. 2 Connected to i.
  • the semiconductor pellet 21 and the wires 24 are resin-sealed with a sealing resin 23 such as an epoxy resin.
  • the size of the high-frequency module 1 is, for example, 8 mm in width, 12.3 mm in length, and 1.8 mm in height.
  • the high-frequency module 1 is assembled by the assembly procedure (manufacturing process) shown in Fig. 3.
  • Each process consists of solder printing for mounting chip components (Step S1, Figure 4 (a)) and solder potting for mounting semiconductor pellets (Step S2, Figure 4 ( b)), component mounting for mounting chip components 22 (Step S3, FIG. 4 (c)), mounting of pellets for mounting semiconductor pellet 21 (Step S4, FIG. 4 (d)), Solder reflow (including cleaning (Step S5)), automatic appearance inspection after reflow (Step S6), wire bonding (Step S7, Fig. 4 (e)), appearance inspection after wire bonding (Step S5) Step S 8), resin application (step S 9, FIG.
  • Multi-cavity board 27 is divided into wiring board 2 which is a single board Substrate division (Step SI 1) that the high-frequency module - a characteristic evaluation of the Le 1 (Step S 1 2, Fig. 4 (h)) and the high frequency module 1 of the taping (Step S 1 3, FIG. 4 (i)).
  • step S10 from the solder printing in step S1 to the insertion of the cap (including the marking) in step S10, the multi-piece board 27 on which the plurality of wiring boards 2 are formed is formed.
  • step S11 the multi-piece board 27 is divided into wiring boards 2 which are individual boards, and as a result, the characteristic selection and the steps in step S12 are performed.
  • the taping of S 13 is performed in the form of the high-frequency module 1 having the wiring board 2.
  • the manufacturing cost and material cost of the high-frequency module 1 can be reduced by manufacturing the multi-cavity substrate 27 without dividing it into the individual wiring boards 2 until the final stage of the assembly process of the high-frequency module 1 In addition, a smooth assembly can be achieved, and the production line can be streamlined.
  • assembly is performed by applying the following method.
  • the chip component 22 and the semiconductor pellet 21 are placed only on the wiring board 2 of the inspected multi-cavity board 27 shown in FIG. Is mounted on a non-defective wiring board 2, thereby In the cap insertion process of S 1 ⁇ , the cap 4 is attached only to the non-defective wiring board 2.
  • the inspection of the wiring board 2 of the multi-piece board 27 at the delivery (purchase) stage (this inspection may be performed in advance by the board maker, and the inspected board may be delivered, or Blocks that are determined to be defective in either case (whichever may be performed later), that is, wiring board 2, are marked with a defect mark 2e as shown in FIG. 5 (a), and a series of subsequent steps (step S3 In the process from mounting of the component to insertion of the cap in step S10), the defective mark 2e is recognized in each process, and the work on the wiring board 2 on which the defective mark 2e is formed is omitted.
  • the manufacturing cost of the high-frequency module 1 can be reduced.
  • the board failure at the stage of delivering a multi-cavity board is, for example, an electrical failure such as a circuit open due to a short circuit or disconnection of the circuit, or a poor appearance such as a warp or short circuit in the appearance.
  • the defective mark 2e is not melted by washing after soldering, and in order to facilitate pattern recognition, a mark ink for a semiconductor or the like is used. Do.
  • each process is inspected to recognize a process defective product which has become a defective product in the process, and a defective mark 2 e is attached to the wiring board 2 which has become a process defective product.
  • a defective mark 2 e is attached to the wiring board 2 which has become a process defective product.
  • the defect mark 2e is recognized by pattern recognition in the component mounting process in step S3 shown in FIG.
  • the chip component 22 is not mounted on the wiring board 2 which is detected and becomes a defective block.
  • step S4 the defective mark 2e is detected by pattern recognition and the wiring board 2 which becomes a defective block is provided with the semiconductor pellet 21. Do not mount.
  • the defective mark 2e is detected by pattern recognition and counted as defective without performing the inspection.
  • the block (wiring board 2) determined to be defective in the automatic appearance inspection is provided with a defective mark 2e made of quick-drying ink by coating or the like as shown in FIG. 5 (c).
  • step S7 the defective mark 2e at the time of delivery and the defective mark 2e at the time of appearance inspection after mounting the component pellet are detected by pattern recognition, and the wiring board 2 which becomes a defective block is detected. Do not perform wire bonding. Further, in the appearance inspection after the wire bonding in step S8, as shown in FIG. 5 (d), a defective mark 2e made of quick-drying ink is applied as wire bonding appearance defects as shown in FIG. 5 (d).
  • the defective mark 2e at the time of delivery, the defective mark 2e at the time of appearance inspection after mounting the part pellet, and the defective mark 2e at the time of appearance inspection after wire bonding are pattern-recognized.
  • the resin is not applied to the wiring board 2 which is detected as a defective block and becomes a bad block.
  • step S10 the defective mark 2e at the time of delivery, the defective mark 2e at the time of appearance inspection after mounting the component 'pellet', and the defective mark 2e at the time of appearance inspection after wire bonding are patterned.
  • a cap is not inserted into the wiring board 2 that is detected by recognition and becomes a defective block.
  • step S11 the presence or absence of the cap 4 is detected by a sensor or the like, and the wiring board 2 with the cap 4 is stored as a good product, while the cap 4 is not attached. Wiring board 2 is treated as defective.
  • the manufacturing cost of the high-frequency module 1 can be reduced.
  • the multi-cavity substrate 27 is, for example, a ceramic substrate of multilayer wiring, and its size is, for example, 78.75 when 40 wiring substrates 2 are formed. m mx 75.0 mm.
  • the multi-piece substrate 27 may be a glass epoxy substrate other than the ceramic substrate.
  • each wiring board 2 of the multi-cavity board 27 has a surface as shown in FIG. 5 (b) according to the number of semiconductor pellets 21 and chip parts 22 mounted on the bare chip.
  • One or a plurality of recesses 2a for mounting a semiconductor pellet and chip component electrodes 2b for mounting chip components are formed, and as shown in FIG.
  • step S1 solder printing in step S1 is performed on the multi-piece substrate 27 shown in FIG. 7 (a).
  • solder printing is performed on the chip component electrode 2b (see FIG. 5 (b)) on the surface 27a of the wiring board 2 shown in FIG. 7 (b) in the multi-piece board 27, and FIG. a) and a printed solder pattern 2c as shown in FIG. 7 (c) is formed.
  • the solder printing is, for example, screen printing using a solder mask.
  • step S2 After the solder printing, the solder potting shown in step S2 is performed.
  • solder is applied to the concave portion 2a of each wiring board 2 of the multi-piece board 27 by potting, and the potting is applied as shown in FIGS. 4 (b) and 7 (c). Form solder 2 f.
  • the nozzle 2 8 As shown in FIG. 6, as a movement trajectory 29 of the nozzle 28 when the solder is ejected from the solder potting nozzle 28, the nozzle 2 8 is moved between adjacent recesses 2a in the wiring board 2 in the shortest distance and in a continuous operation (single-stroke operation) as shown in FIG. 6 (a), and as shown in FIG. 6 (). However, it is moved in a shortest distance and also in a continuous operation (single-stroke operation) with respect to another adjacent wiring substrate 2 in the multi-cavity substrate 27.
  • the movement trajectory 29 of the nozzle 28 is controlled by a mounting position coordinate program. To set.
  • solder printed solder pattern 2c
  • solder is printed on the chip component electrodes 2b of the wiring board 2
  • solder is potted on the recesses 2a of the wiring board 2.
  • the potting time can be shortened as a result, and thus the throughput of the solder potting process can be reduced. Can be improved.
  • step S3 of FIG. 3 After that, the components are mounted in step S3 of FIG. 3, and after the components are mounted, the pellet is mounted in step S4.
  • the component mounting device 30 transfers a large number of chip components 22 to the wiring board 2 of the circuit board 27, and mounts the chip components 22 on the wiring board 2, as shown in FIG. 8 (b).
  • the first component supply unit 31 component supply unit
  • the first component supply unit 31 that can send out the stored chip parts 22 (see Fig. 5 (c)) for each type (for example, product type)
  • Component supply section 3 2 component supply section
  • XY stage 34 supporting multi-cavity board 27, and mounting head section 33 mounting chip component 22 on XY stage 34
  • a board transfer section 35 for transferring the multi-piece board 27.
  • the first component supply unit 31 and the second component supply unit 32 are, for example, a tape feeder or a bulk feeder, and can be freely slid in the direction parallel to the board transfer direction of the board transfer unit 35. Have been.
  • the components A, B, C, D, E, and F) are supplied to the wiring board 2 for each component supply unit and are arranged.
  • the chip component 22 is mounted on the wiring board 2 as shown in FIG. 4 (c) and FIG. 10 (a).
  • the chip component 22 in the first component supply section 31 are mounted on the entire multi-piece board 27, and then all the chip components 22 in the second component supply section 32 are multi-piece boards 2. 7 Installed on the whole.
  • the moving distance of the first component supply unit 31 and the second component supply unit 32 can be reduced, and as a result, the throughput of the component mounting time can be improved.
  • Each component can be mounted.
  • the printed solder pattern 2 c formed on the chip component electrode 2 b of the wiring board 2 is recognized and the chip component electrode 2 b is formed on the printed solder pattern 2 c. Place.
  • the terminals of the chip component 22 and the electrode 2b for the chip component are securely soldered via the printed solder pattern 2c due to the self-alignment effect of the printed solder pattern 2c. Therefore, even when the printed solder pattern 2c is formed to be displaced from the chip component electrode 2b, it is possible to prevent the occurrence of defects such as component standing and component floating, which are likely to occur at that time.
  • the pellet mounting device 36 transfers a large number of semiconductor pellets 21 to the recess 2 a of the wiring board 2 of the substrate 27, and places the semiconductor pellet 21 in the recess 2 a of the wiring board 2.
  • a pellet supply system 37 that can send out the stored semiconductor pellets 21 by type (for example, product type), and a semiconductor pellet It comprises a bonding head section 38 for mounting 21, a board transfer section 39 for transferring a multi-piece board 27, and a monitor 40 for displaying the bonding position and the like.
  • the pellet supply system 37 includes, for example, a first pellet supply section 37a, a second pellet supply section 37b, and a third pellet supply section 37, which are four component supply sections. c and a fourth pellet supply unit 37 d are provided, and the component supply unit is, for example, a chip tray, and a rotating block 37 in the pellet supply system 37. attached to e.
  • the method of mounting the semiconductor pellet 21 in the pellet mounting device 36 is, for example, a direct pickup method from a pellet supply unit such as a chip tray or a semiconductor wafer.
  • the semiconductor pellets 21 accommodated therein (here, pellet A, pellet B, pellet). And Pellet D) are supplied to the wiring board 2 for each component supply unit and are arranged.
  • the semiconductor pellet 21 is mounted in the concave portion 2a of the wiring board 2.
  • the rotating block 37e is rotated to rotate the second pellet supply section 3.
  • All of the semiconductor pellets 21 in 7b are mounted on the entire multi-piece substrate 27.
  • the rotary block 37 e is rotated, and the semiconductor pellets 21 of the third pellet supply section 37 c and the fourth pellet supply section 37 d are sequentially taken into a large number, and the whole board 27 is taken. To be mounted on.
  • the edge 2 g of the recess 2 a of the wiring board 2 shown in FIG. 10 (b) is recognized and the semiconductor pellet 21 is placed in the recess 2 a. .
  • the position recognition accuracy of the concave portion 2a can be improved, and as a result, the size of the concave portion 2a can be made slightly larger than the size of the semiconductor pellet 21. Therefore, the rattling of the semiconductor pellet 21 in the concave portion 2a can be reduced, and as a result, the accuracy of the horizontal arrangement and inclination of the semiconductor pellet 21 can be improved. Wear.
  • the pads (surface electrodes) of the semiconductor pellet 21 can be easily recognized at the time of wire bonding, and as a result, defective wire bonding can be reduced.
  • the semiconductor pellet 21 has a higher probability of failure due to stress from the outside than the chip component 22, it is better to mount the semiconductor pellet 21 after mounting the chip component 22. Therefore, the possibility that the semiconductor pellet 21 is damaged can be reduced.
  • step S5 shown in FIG. 3 is performed.
  • solder reflow opening of the multi-piece board 27 is performed, and the chip component 22 and the semiconductor pellet 21 on the wiring board 2 are both connected by soldering.
  • step S6 an automatic appearance inspection in step S6 is performed.
  • the appearance inspection of the multi-cavity substrate 27 just after the riff opening is performed to check whether there is any defect in the riff opening.
  • the position of the mounted component when the position of the mounted component is detected using a laser beam or the like, the position of the mounted component can be accurately recognized by recognizing the stepped portion on the wiring board 2.
  • a through hole 2h shown in FIG. 11 (b) and a surface wiring 2d shown in FIG. 7 (b) formed on the wiring board 2 of the multi-piece board 27 shown in FIG. 11 (a) are recognized.
  • the position of the mounted component can be recognized with high accuracy.
  • step S7 wire bonding shown in step S7 is performed.
  • wire bonding is performed using a wire 24 such as a gold wire, and a pad serving as a surface electrode of the semiconductor pellet 21 and a plurality of corresponding pads are formed.
  • the board side terminal 2 i (see FIG. 5 (b)) of the wiring board 2 of the wiring board 27 is connected with the wire 24.
  • step S8 After that, the appearance inspection shown in step S8 is performed.
  • step S 9 the resin (encapsulating resin 23) shown in step S 9 is applied.
  • the sealing resin 23 is dropped on the concave portion 2 a of the wiring board 2 of the multi-piece board 27 by the potting method, thereby forming the semiconductor.
  • the pellet 21 and the wire 24 are sealed with a sealing resin 23.
  • the sealing resin 23 is applied by potting to the recess 2 a of the wiring board 2, avoiding the dividing groove 27 b of the multi-piece board 27 shown in FIG. 12 (a).
  • the semiconductor pellet 21 is sealed with resin.
  • the sealing resin 23 is not applied to the dividing groove portion 27 b which is a slit for dividing the individual substrate formed on the multi-cavity substrate 27.
  • the encapsulating resin 23 is applied to each individual block, that is, to each wiring board 2 on the multi-cavity board 27.
  • the sealing resin 23 is not applied to the dividing groove portion 27 b of the multi-piece substrate 27, so that the sealing resin 23 is removed from the through hole 2 h shown in FIG. 11B. 23 can be prevented from entering and sneaking into the back surface of the substrate, thereby adversely affecting when the substrate is divided.
  • cap insertion shown in step S10 is performed.
  • the cap 4 shown in FIG. 13 is marked with a mark as shown in FIG. 14 and the UV (Ultra Viol et) Drying, mark 4 Inspection of the mark appearance by pattern recognition of mark 2 and cap insertion are performed by continuous integrated processing, and when inserting the cap, only caps 4 judged as good by the mark appearance inspection are capped. In this way, it is possible to shorten the assembling time in the step of inserting the cap and to prevent the cap 4 with the other mark 42 from being mixed.
  • the UV Ultra Viol et
  • the mark 42 is marked on the cap 4 in the cap introduction step.
  • the cap 4 is made of, for example, a metal.
  • the hook support arm 17 (hook support portion) that supports the hook 19 shown in FIG. 1 and that can be engaged with the wiring board 2 of the multi-piece board 27 It is provided.
  • the mark 42 which is a recognition mark, is, for example, a serial number or a model number of the high-frequency module 1, and is composed of characters and symbols.
  • the mark 4 2 is attached to the surface 4 a of the cap 4.
  • the mark 42 is dried by UV. After drying, the appearance of the mark 42 is inspected by pattern recognition, and the caps 4 having the non-defective marks 42 are selected.
  • the cap mounting device 44 includes an XY table 45 supporting the multi-piece substrate 27, a mounting unit 46 for mounting the cap, and a multi-piece substrate 27 mounted on the XY table 45.
  • a plurality of hook holes 27c (see Fig. 15 (b)), which are recognition points, a recognition camera 47 for imaging the hook holes 27c, and an alignment station 48 for disposing the cap 4 at an angle. Consists of
  • the mounting unit 46 includes a suction collet 46a capable of holding the cap 4 by suction, a first cylinder 46b and a first panel 46c for vertically moving the suction collet 46a, A first slider 46 d to guide the vertical movement of the suction collet 46 a, and a key
  • the pusher 46 i that presses the cap 4 when inserting the cap, the second cylinder 46 e and the second panel 46 f that moves the pusher 46 i up and down, and the vertical movement of the pusher 46 i
  • a second slider 46 g for guiding is provided.
  • the alignment station 48 includes an inclined main jig 48 a for supporting the cap 4 at a predetermined angle and a cap 4 when the cap 4 is inclined and supported by the inclined main jig 48 a.
  • An auxiliary tilting jig 48 b is provided to guide around.
  • the suction collet 46 a When the cap 4 is suction-held from the inclined main jig 48 a by the suction collet 46 a, the suction collet is inclined at the same angle as the inclination angle of the cap 4 at the inclined main jig 48 a.
  • the suction surface 46 j of the suction collet 46 a is formed at the same angle as the angle of the support surface of the main tilting jig 48 a so that the suction collet 46 a can be tilted and held.
  • the multi-cavity substrate 27 is placed on the XY table 45, and thereafter, the recognition An image of the hook hole 27 c of the multi-piece substrate 27 shown in) is detected and its position is detected.
  • the cap 4 determined to be non-defective is supported by being inclined at a predetermined angle by the inclination main jig 48 a of the alignment station 48 of the cap mounting device 44. After that, the cap 4 is held by the suction collet 46 a of the mounting unit 46 while the cap 4 is kept inclined.
  • one of the two hook support arms 17 opposed to each other on the cap 4 and one of the hook support arms 1 ⁇ ⁇ ⁇ ⁇ arranged on the lower side due to the inclination is mounted on the XY table 45 with a large number of pieces.
  • the cap 4 is moved together with the mounting unit 46 so as to be placed on a desired hook hole 27 c of the substrate 27.
  • the hook supporting arm 17 arranged at the lower side due to the inclination of the two hook supporting arms 17 facing the cap 4 is shown in FIG.
  • FIG. 7 (b) of the two hook holes 27c to be inserted, insert into the hook hole 27c on the side where the adjacent cap 4 is not attached.
  • the corresponding hook support arm 17 (here the hook support arm 1 on the A side) is inserted into the hook hole 27 c on the side where the cap 4 is not attached.
  • the suction collet 46a is lowered by the first cylinder 46b on the A side of 46, and the hook 19 of the hook support arm 17 is hooked up by the inclination of the cap 4. Insert at an angle to c.
  • the hook support arm 17 when the hook support arm 17 is inserted, the hook claw 18 of the hook 19 does not come into contact with the hook hole 27 c, thereby preventing damage to the vicinity of the hook hole 27 c in the multi-piece board 27. As a result, the yield and quality of the multi-piece substrate 27 can be improved.
  • the wiring board 2 is inserted into the hook support arm 17 on one side (A side) inserted into the hook hole 27c on the side where the adjacent cap 4 is not attached.
  • the hook support arm 17 on the A side by moving the width 46 k (moving the wiring board 2 of the multi-piece board 27 by moving the XY table 45 from the B side to the A side and moving the set value) Load.
  • the radius is set within the elastic range. It is possible to make it.
  • the radius of the hook support arm 17 on the A side increases the distance between the two hook support arms 17 on the cap 4, and as a result, the hook claw on the hook 19 on the hook support arm 17 on the A side 18 (see FIG. 1) engages with the hooked portion 16 of the wiring board 2 and, as shown in FIG. 18 (b), the hook support arm 17 on the B side (the other side) 17 Are arranged on the other hook holes 27 c of the multi-piece substrate 27.
  • the yield and quality of the multi-piece substrate 27 can be improved.
  • the load applied to the A-side hook support arm 17 by the width adjustment 46 k of the wiring board 2 of the multi-piece board 27 is released, whereby the A-side hook support arm 1 is released.
  • the hook 19 of 7 and the hook 19 of the hook support arm 17 on the B side are engaged with the hooks 16 on both sides of the wiring board 2, respectively.
  • the mounting (attachment) of the multi-piece board 27 of the cap 4 to the wiring board 2 can be completed, and therefore, the multi-piece board of the cap 4 can be completed.
  • Automatic mounting on 27 can be performed easily.
  • the wiring board 2 on which the chip component 22 and the semiconductor pellet 21 are mounted can be covered with the cap 4.
  • the cap 4 is The problem of rattling of step 4 can be eliminated.
  • sealing with the cap 4 can be performed on an integrated assembly line using the multi-cavity substrate 27, mass production efficiency can be improved.
  • the number of steps can be significantly reduced, and a washing step for dirt such as flux can be omitted.
  • the suction collet 46a and the pusher 46i are raised to the original position by using the first slider 46d and the second slider 46g as guides, and returned to their original positions. Further, the mounting unit 46 is moved to the alignment station 48 to complete the cap insertion process.
  • step S11 the board division of step S11 shown in FIG. 3 is performed, and the multi-piece board 27 is divided into individual wiring boards 2 which are individual boards, thereby obtaining a structure as shown in FIG. 4 (h).
  • Each high-frequency module is in the form of 1.
  • step S12 the characteristic selection shown in step S12 is performed to obtain the electrical characteristics of each high-frequency module 1, and the high-frequency module 1 is selected based on the result.
  • module characteristics fluctuate due to variations in the wiring pattern conductor resistance of the ceramic substrate, that is, the wiring substrate 2, variations in the capacitance between the wiring patterns, and variations in the characteristics of the semiconductor pellet 21. Therefore, in the characteristic selection process, the electrical characteristics of the wiring board 2 in the high-frequency module 1 are monitored. Therefore, in assembling the high-frequency module 1, the characteristics of the semiconductor pellet 21 are classified and used in advance. Assembling is performed by selecting the constants of chip components 22 such as a chip capacitor and a chip resistor that are optimal for the combination of the wiring board 2 and the semiconductor pellet 21.
  • the high-frequency module 1 is manufactured.
  • the characteristics can be within an acceptable range, and as a result, a high-quality and stable high-frequency module 1 can be assembled. You.
  • FIG. 21 shows an example of the relationship between the frequency and the output (Pout) in the characteristics of the wiring board 2 of the high-frequency module 1.
  • the output Q (W) in Fig. 21 is the threshold for the pass / fail of the output of the high-frequency module 1
  • the output in the case of the first sample 50 of the high-frequency module 1, the output is sufficiently acceptable in the used frequency band 49. It becomes a good product as the high-frequency module 1.
  • the output in the case of the second sample 51, in the used frequency band 49, the output passes only in about half the area (the lower frequency side area in the used frequency band 49), and the output passes 52, and the remaining about half area In the (higher frequency range in the used frequency band 49), the output failed 53, resulting in a defective high-frequency module 1.
  • Fig. 22 shows an example of the grade classification of the semiconductor pellet 21.
  • the automatic sorting jig-packing machine is used for each semiconductor pellet. Shows the result of grade classification.
  • C iss represents capacitance
  • I dss represents leakage current
  • V th represents threshold voltage.
  • three semiconductors of grades ⁇ ⁇ ⁇ 3, 4 and 8 are shown.
  • the optimal circuit constants can be set by using a combination of pellets 21.
  • step S13 shown in FIG. 3 is performed.
  • a plurality of the selected high-frequency modules 1 are taped, wound and stored on a reel 43 shown in FIG. 4 (i).
  • the productivity is approximately three times that of the conventional assembling method. Further, a price reduction of 50% can be realized.
  • the present invention is not limited to the first and second embodiments of the invention, and the gist thereof is described. It is needless to say that various changes can be made without departing from the scope.
  • the characteristic selection step of the second embodiment the electrical characteristics of the wiring board 2 are monitored, the characteristics of the semiconductor pellet 21 are classified in advance, and the wiring substrate 2 and the semiconductor pellet used are classified.
  • the chip component may be obtained by exchanging 22 or the like.
  • the semiconductor pellet 21 described in the above embodiment may be obtained from a silicon semiconductor wafer, or may be obtained from a gallium or arsenic semiconductor wafer. Further, SOI, GeSi, TFT (Thin Film Transistor) and the like may be used.
  • the method of manufacturing a semiconductor device according to the present invention is applied to a general module product in which chip components such as chip capacitors and chip resistors and a semiconductor pellet formed by bare chip mounting are mounted and assembled using a multi-cavity substrate. It is suitable for the manufacturing method of small-sized portable electronic devices such as mobile phones, and especially suitable for high-frequency modules (high-frequency power amplifiers) mounted on thin portable electronic devices. is there.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

La présente invention concerne un procédé de fabrication de dispositif à semi-conducteurs où le nombre d'opérations de fabrication a été réduit, ce qui permet de rationaliser la ligne de production. En l'occurrence, pour produire un module HF, on monte des microcircuits et des pastilles de semi-conducteurs (21) sur une carte de câblage d'une carte multibloc en cours d'examen (27). Une carte de câblage (2) d'un bloc qui est considéré comme défectueux à l'inspection de la carte multibloc (27) est repérée comme défectueuse (2e). Au cours des opérations d'assemblage après le marquage, la marque de défectuosité (2e) est reconnue et la pièce sur la carte de câblage (2) marquée de la marque de défectuosité (2e) est mise de côté, ce qui permet de rationaliser la ligne de production.
PCT/JP2000/000828 2000-02-15 2000-02-15 Procede de fabrication de dispositif a semi-conducteurs WO2001061744A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
PCT/JP2000/000828 WO2001061744A1 (fr) 2000-02-15 2000-02-15 Procede de fabrication de dispositif a semi-conducteurs
AU2000224628A AU2000224628A1 (en) 2000-02-15 2000-02-15 Method for manufacturing semiconductor device
TW089106119A TW550766B (en) 2000-02-15 2000-03-31 Manufacturing method semiconductor device
AU32308/01A AU3230801A (en) 2000-02-15 2001-02-15 Semiconductor device fabrication method and semiconductor device fabrication device
KR1020027010498A KR100689129B1 (ko) 2000-02-15 2001-02-15 반도체 장치의 제조 방법 및 반도체 제조 장치
PCT/JP2001/001091 WO2001061754A1 (fr) 2000-02-15 2001-02-15 Procede et dispositif de fabrication de dispositifs a semiconducteurs
US10/129,305 US6852553B2 (en) 2000-02-15 2001-02-15 Semiconductor device fabrication method and semiconductor device fabrication apparatus
CNB018033148A CN1222036C (zh) 2000-02-15 2001-02-15 半导体器件制造方法和半导体器件的制造装置
US10/983,689 US6946306B2 (en) 2000-02-15 2004-11-09 Method of manufacturing a semiconductor device and a fabrication apparatus for a semiconductor device
US11/178,423 US20050250254A1 (en) 2000-02-15 2005-07-12 Method of manufacturing a semiconductor device and a fabrication apparatus for a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/000828 WO2001061744A1 (fr) 2000-02-15 2000-02-15 Procede de fabrication de dispositif a semi-conducteurs

Publications (1)

Publication Number Publication Date
WO2001061744A1 true WO2001061744A1 (fr) 2001-08-23

Family

ID=11735685

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/000828 WO2001061744A1 (fr) 2000-02-15 2000-02-15 Procede de fabrication de dispositif a semi-conducteurs

Country Status (3)

Country Link
AU (1) AU2000224628A1 (fr)
TW (1) TW550766B (fr)
WO (1) WO2001061744A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016103791A1 (fr) * 2014-12-26 2016-06-30 シャープ株式会社 Procédé et appareil de montage de capot pour boîtier d'élément semi-conducteur

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653342A (ja) * 1992-07-29 1994-02-25 Toshiba Corp 半導体装置
JPH09252011A (ja) * 1996-01-12 1997-09-22 Toshiba Corp リッド装着装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653342A (ja) * 1992-07-29 1994-02-25 Toshiba Corp 半導体装置
JPH09252011A (ja) * 1996-01-12 1997-09-22 Toshiba Corp リッド装着装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016103791A1 (fr) * 2014-12-26 2016-06-30 シャープ株式会社 Procédé et appareil de montage de capot pour boîtier d'élément semi-conducteur
JPWO2016103791A1 (ja) * 2014-12-26 2017-08-31 シャープ株式会社 半導体素子パッケージのためのキャップ装着方法及びキャップ装着装置

Also Published As

Publication number Publication date
AU2000224628A1 (en) 2001-08-27
TW550766B (en) 2003-09-01

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