TW550766B - Manufacturing method semiconductor device - Google Patents

Manufacturing method semiconductor device Download PDF

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Publication number
TW550766B
TW550766B TW089106119A TW89106119A TW550766B TW 550766 B TW550766 B TW 550766B TW 089106119 A TW089106119 A TW 089106119A TW 89106119 A TW89106119 A TW 89106119A TW 550766 B TW550766 B TW 550766B
Authority
TW
Taiwan
Prior art keywords
wafer
wiring substrate
manufacturing
semiconductor device
passive
Prior art date
Application number
TW089106119A
Other languages
Chinese (zh)
Inventor
Akio Ishizu
Kazutoshi Takashima
Shiro Oba
Yoshihiko Kobayashi
Tsutomu Ida
Original Assignee
Hitachi Ltd
Hitachi Tobu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tobu Semiconductor Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW550766B publication Critical patent/TW550766B/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A kind of method for manufacturing semiconductor device capable of obtaining the decrease of manufacturing process and making reasonable the production line is disclosed in the present invention. The chip component 22 and semiconductor chip 21 are mounted on a wiring substrate 2 of plural checked accommodation substrate 27 so as to assembly the high frequency module. For the wiring substrate 2 of the block that is judged as the bad one during the inspection of plural accommodation substrate 278, bad mark 2e is given such that the operation conducted onto the wiring substrate 2 having the bad mark 2e is omitted by recognizing each carried bad mark in the following series of assembling process. Therefore, it is capable of obtaining rationalization for the manufacturing production line.

Description

550766 A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明説明（1 ) (技術領域） 本發明係關於一種半導體製造技術。特別是，關於一 種適用於高頻模組（高頻電力放大裝置）之製造方法而有 效之技術。 (背景技術） 對於被稱爲實裝晶片電容器或晶片電阻等之表面實裝 型晶片零件，及裸晶片實裝用之半導體小九之高頻模組（ 也稱爲R F模組或R F功率模組）的高頻電力放大裝置， 有如日本特開平1 〇 - 1 2 8 0 8號公報所述，.在該公報 記載有局頻模組之構造與用以一倂裝配電氣特性及複數個 高頻模組之多數個收納基板之構造等。 又，對於拼合積體電路之插接帽之裝設有如日’本特開 平6 - 3 0 2 7 0 7號公報之記載。在該公報記載有對於 個片化之基板之插接帽之裝設方法。 又在日本特開平1 〇 - 1 2 8 0 8號公報，未記載附 於插接帽之文字或記號等之標誌，又也未記載對於多數個 收納基板之插接帽之詳細安裝方法，晶片零件（電子零件 )及半導體小九之搭載方法及對於多數個收納基板之銲劑 印刷或銲劑接合方法等之裝配技術。 又，在日本特開平6-302707號公報，未記載 對於多數個收納基板之插接帽之裝設方法。 卒發明之目的係在於提供一種可謀求刪減製程及製造 生、產線之合理化的半導體裝置之製造方法。 (請先閲讀背面之注意事項再填寫本頁j -訂- -lr. 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4- 550766 A7 _______^__ 五、發明説明（2 ) 又本發明之其他目的係在於提供一種可謀求減低製造 成本的半導體裝置之製造方法。 (請先閲讀背面之注意事項再填寫本頁) 又本發明之其他目的係在於提供一種可減低材料成本 的半導體裝置之製造方法。 本發明之上述及其他目的及新穎之特徵，係由本發明 之專利說明書之記述及所附圖式即可明瞭。 (發明之揭示） 本發明之半導體裝置之製造方法係具有：將上述被動 元件用晶片及上述主動元件用晶片配置於上述配線基板並 將上述被動元件用晶片及上述主動元件用晶片實裝於上述 配線基板之過程；及將認識標誌附於表面之插接帽安裝於 上述配線基板，藉由上述插接帽來覆蓋上述被動元件用晶 片及上述主動元件用晶片之過程。 經濟部智慧財產局員工消費合作社印製 又本發明之半導體裝置之製造方法係具有有：將上述 被動元件用晶片及上述主動元件用晶片配置於上述配線基 板並將上述被動元件用晶片及上述主動元件用晶片實裝於 上述配線基板之過程；及進行認識標誌附於表面之插接帽 之上述認識標誌之檢查，上述檢查後，將良品之插接帽安 裝於上述配線基板，藉由上述插接帽來覆蓋上述被動元件 用晶片及上述主動元件用晶片之過程。 依照本發明，由於在進行附有認識標誌之插接帽之上 述認識標誌之檢查後將良品之插接帽安裝於配線基板，因 此可防止無標誌，標誌不良或是其他標誌之插接帽等不良 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -5- 550766 A7 B7 五、發明説明（3 ) 品插接帽之安裝。 (請先閲讀背面之注意事項再填寫本買) 由此，由於不會安裝有關於認識標誌之不良品插接帽 ’因此可謀求製造成本之合理化。 又本發明之半導體裝置之製造方法，係屬於在形成有 複數配線基板之多數個收納基板之上述配線基板，實裝被 動元件用晶片及主動元件用晶片並加以裝配半導體裝置之 製造方法，其特徵爲具有：在經檢查之上述多數個收納基 板之上述配線基板配置上述被動元件及上述被動元件用晶 片及上述主動元件用晶片，並將上述被動元件用晶片及上 述主動元件用晶片實裝於良品之配線基板之過程；及將插 接帽僅安裝於上述良品之配線基板，藉由上述插接帽來覆 蓋上述被動元件用晶片及上述主動元件用晶片之過程。 依照本發明，由於僅在經檢查之多數個收納基板之配 線基板，實裝被動元件用晶片及主動元件用晶片，在半導 體裝置之製造過程，可省略對於該不良部位之作業。 由此，可謀求刪減製程及製造線之合理化。 結果，可減低半導體裝置之製造成本。 經濟部智慧財產局員工消費合作社印製 又本發明之半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有：在上述配線基板之 被動元件用晶片用端子印刷銲劑之過程；及上述銲劑印刷 後’將銲劑藉由接合塗布於上述配線基板之凹部之過程； 及將上述述被動元件用晶片配置在上述配線基板之過程； 及將上述主動元件用晶片配置在上述配線基板之上述凹部 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6 - 550766 A7 B7 五、發明説明（4 ) 之過程；及進行銲劑溶融熱處理並將上述被動元件用晶片 及上述主動元件用晶片藉由銲劑接合實裝於上述配線基板 程。 依照本發明，由於在配線基板之被動元件用晶片用端 子印刷銲劑，之後，將銲劑藉由接合塗布在配線基板之凹 部，先進行銲劑印刷，因此可防止銲劑印刷時之銲劑遮光 罩藉由銲劑而弄髒。 又’本發明之半導體裝置之製造方法，係屬於在配線 基板實裝被動元件用晶片及主動元件用晶片並加以裝配之 半導體裝置之製造方法，其特徵爲具有：將上述被動元件 用晶片配置在上述配線基板之過程；及 配置上述被動元件用晶片後，將上述主動元件用晶片 配置在上述配線基板之凹部之過程；及將上述被動元件用 晶片及上述主動元件用晶片藉由銲劑接合實裝於上述配線 基板之過程。 又本發明之半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有：將上述被動元件用 晶片配置在複數上述配線基板藉由分割用槽部被區劃形成 之多數個收納基板之上述配線基板之過程；及將上述被動 元件用晶片配置在上述配線基板之凹部之過程；及將上述 主動元件用晶片及上述主動元件用晶片藉由銲劑接合實裝 在上述配線基板之過程；及利用接合避開上述分割用槽部 將上述封閉用樹脂塗布在複數上述配線基板之凹部，俾樹 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) '^衣. -tr填寫太550766 A7 B7 Printed by the Consumer Co-operation of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (1) (Technical Field) The present invention relates to a semiconductor manufacturing technology. In particular, it relates to a technique that is effective for a method for manufacturing a high-frequency module (a high-frequency power amplifier). (Background Art) For surface-mounted chip components called chip capacitors or chip resistors, and high-frequency modules (also called RF modules or RF power modules) for bare-chip mounting of small semiconductors. The high-frequency power amplifying device is described in Japanese Patent Application Laid-Open No. 10-128 8 0. The publication describes the structure of a local frequency module and a method for assembling electrical characteristics and a plurality of high-frequency modules. The structure of a plurality of storage substrates. In addition, the insertion cap of the integrated circuit is described in Japanese Patent Application Publication No. 6-3 0 2 7 0 7. This publication describes a method for mounting a plug cap on a piece of substrate. Also in Japanese Patent Application Laid-Open No. 10-128-8, there is no description of the characters or symbols attached to the plug caps, nor does it describe the detailed mounting method of the plug caps for a plurality of storage substrates, wafers Mounting methods for parts (electronic parts) and semiconductor small nines, and solder printing or solder bonding methods for a large number of storage substrates. In addition, Japanese Unexamined Patent Publication No. 6-302707 does not describe a method for installing a plug cap for a plurality of storage substrates. The purpose of the invention is to provide a method for manufacturing a semiconductor device that can reduce manufacturing processes and rationalize production and production lines. (Please read the precautions on the back before filling out this page j -Order--lr. This paper size applies to Chinese National Standard (CNS) A4 specifications (210X297 mm) -4- 550766 A7 _______ ^ __ 5. Description of the invention (2 ) Yet another object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce manufacturing costs. (Please read the precautions on the back before filling out this page) Another object of the present invention is to provide a material cost reduction The above-mentioned and other objects and novel features of the present invention can be understood from the description of the patent specification of the present invention and the attached drawings. (Disclosure of the Invention) The manufacturing method of the semiconductor device of the present invention The process includes: placing the passive element wafer and the active element wafer on the wiring substrate, and mounting the passive element wafer and the active element wafer on the wiring substrate; and inserting an identification mark on a surface. The contact cap is mounted on the wiring substrate, and the passive chip and the active chip are covered by the insertion cap. The method for manufacturing a semiconductor device printed by an employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the present invention includes: disposing the above-mentioned passive device wafer and the above-mentioned active device wafer on the wiring substrate and disposing the passive device. The process of mounting the component wafer and the active component wafer on the wiring board; and checking the recognition mark of the plug cap with a recognition mark attached to the surface. After the inspection, the good quality plug cap is installed on the wiring. The process of covering the wafer for the passive element and the wafer for the active element with the above-mentioned plug cap according to the present invention, since the inspection of the above-mentioned recognition mark of the plug cap with the recognition mark is performed after the inspection of the above-mentioned recognition mark with the recognition mark The connector cap is installed on the wiring substrate, so it can prevent defects such as no logo, bad logo, or plug caps with other logos. This paper applies the Chinese national standard (CNS) A4 specification (210X297 mm) -5- 550766 A7 B7 5. Description of the invention (3) The installation of the product plug cap (Please read the precautions on the back before filling in this purchase) Therefore, since a defective connector with a recognition mark is not installed, the manufacturing cost can be rationalized. The method for manufacturing a semiconductor device of the present invention belongs to the above-mentioned plurality of storage substrates in which a plurality of wiring substrates are formed. A wiring substrate, a manufacturing method for mounting a passive element wafer and an active element wafer and assembling a semiconductor device, characterized in that the wiring substrate includes the passive element and the passive element on the wiring substrate of the plurality of storage substrates inspected. The process of mounting the wafer for the active element and the wafer for the active element and mounting the wafer for the passive element and the wafer for the active element on a good-quality wiring substrate; and mounting a plug cap only on the good-quality wiring substrate through the above-mentioned plug The process of covering the wafer for passive components and the wafer for active components. According to the present invention, since only the wiring substrates of the plurality of storage substrates inspected, the wafers for the passive components and the wafers for the active components are mounted, the operation of the defective part can be omitted in the manufacturing process of the semiconductor device. As a result, rationalization of processes and manufacturing lines can be eliminated. As a result, the manufacturing cost of the semiconductor device can be reduced. The semiconductor device manufacturing method printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the present invention belongs to a manufacturing method of a semiconductor device in which a passive element wafer and an active element wafer are mounted on a wiring substrate and assembled. : A process of printing solder on the terminal of the passive element wafer for the wiring substrate; and a process of applying the solder to the recessed portion of the wiring substrate by bonding after the solder printing; and disposing the wafer for the passive element on the wiring The process of the substrate; and the wafer for the active device is arranged in the above-mentioned recess of the wiring substrate. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -6-550766 A7 B7. 5. Description of the invention (4) Process; and performing a solder melting heat treatment, and mounting the wafer for the passive element and the wafer for the active element on the wiring substrate by solder bonding. According to the present invention, since a solder is printed on a terminal for a passive element wafer of a wiring substrate, and then the solder is applied to the recessed portion of the wiring substrate by bonding, and then the solder is printed first, it is possible to prevent the flux hood during solder printing from passing through the solder. And dirty. The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a passive device wafer and an active device wafer are mounted on a wiring board and assembled, and the method includes: The process of the wiring substrate; and the process of disposing the active element wafer in the recess of the wiring substrate after the wafer for the passive element is arranged; and bonding and mounting the wafer for the passive element and the wafer for the active element by soldering In the process of the above wiring substrate. The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a passive device wafer and an active device wafer are mounted on a wiring board and assembled, and is characterized in that the passive device wafer is arranged in a plurality of numbers. A process of arranging the plurality of wiring substrates on which the wiring substrate is divided by the grooves for division; and a process of arranging the wafers for passive components in the recesses of the wiring substrate; and arranging the wafers for active components and the wafers. The process of mounting the active device wafer on the wiring board by solder bonding; and applying the sealing resin to the recessed portions of the plurality of wiring boards by bonding to avoid the above-mentioned division grooves. (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling out this page) '^ 衣. -Trfill too

、1T 經濟部智慧財產局員工消費合作社印製 -7- 550766 A 7 B7 五、發明説明（5 ) 脂封閉上述主動元件用晶片之過程。 (請先閱讀背面之注意事項再填寫本頁) 又本發明之半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有：將上述被動元件用 晶片及上述主動元件用晶片配置在複數之上述配線基板所 形成之多數個收納基板之上述配線基板並將上述被動元件 用晶片及上述主動元件用晶片實裝在上述配線基板之過程 ;及將支撑可卡合於上述配線基板之鈎的鈎支撑部對應地 設置之插接帽之其中一方的上述鈎支撑部斜向地插入在上 述多數個收納基板之鈎孔，俾將上述插接帽安裝於上述多 數個收納基板之過程； 藉由上述插接帽來覆蓋上述多數個收納基板之上述配 線基板上之上述被動元件用晶片及上述主動元件用晶片。 經濟部智慧財產局員工消費合作社印製 又本發明之半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有：將上述被動元件用 晶片配置經選別之上述配線基板之過程；及將經選別之上 述主動元件用晶片配置於上述配線基板之凹部之過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲劑接 合實裝在上述配線基板之過程；裝配分別經選別之上述配 線基板及上述主動元件用晶片並加以實裝成上述半導體裝 置之特性能進入容許範圍。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -8- 550766 經濟部智慧財產局員工消費合作社印製 A7 _ B7五、發明説明（6 ) (實施發明所用之最佳形態） 在以下之實施形態中，除了有特別情形以外，原則上 不重複同一或同樣部分之說明。 又，在以下之實施形態中，爲了方便，將複數發明說 明在兩個實施形態中，惟除了特別明示之情形之外，當然 各步驟係並不一定能說明所有說明。 又在以下之實施形態中，爲了方便，視需要，分別成 複數區段或是實施形態加以說明，惟除了特別明示之情形 之外，此等係並不是互相無關者，其中一方係具有與另一 方之一部分或全部之變形例，詳細補足說明等之關係。 又在以下之實施形態中，有關於要素之數等（包含個 數、數値、量、範圍等）之情形，除了特別明示之情形及 .原理上明白地限定於特定數之情形之外，並不被限定於該 特定數者，也可以爲特定數以上或以下者。 又在以下之實施形態中，其構成要素（包含要素步驟 等），係除了特別明示之情形及原理上認爲明白地必需之 情形等之外，當然並不一定爲必須者。 同樣地，在以下之實施形態中，有關於構成要素等之 形狀，位置關係等時，除了特別明示之情形及原理上認爲 不淸楚之情形等之外，實際上在其形狀等包含近似或類似 者等。此乃對於上述數値及範圍也同樣。 以下，依據圖式詳細說明本發明之實施形態。又，在 用以說明實施形態之全圖中，具有同一功能之構件賦與同 一記號，省略其重複說明。 1紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ 一~ -9- (請先閱讀背面之注意事項再填寫本頁) 550766 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（7 ) 將本發明之實施形態一，使用表示圖示於第1圖及第 2圖之半導體裝置（高頻模組1 )之構造的圖式，表示第 3圖之高頻模組1之裝配順序的圖式，表示於第4圖之每 --主要過程之配線基板的剖面圖，表示於第5圖之不良標 認配線基板之圖式加以說明。 藉由表示於第1圖及第2圖之本實施形態之一半導體 裝置之製造方法裝配之半導體裝置，係稱爲高頻模組1 ( 也稱爲高頻功率模組）之高頻電力放大裝置，插接帽4重 疊於板狀配線基板2之主面（上面），外觀上爲扁平之矩 形體構造者。 因此，主要組裝於行動電話等之小型攜帶用電子機器 等者，形成有場效電晶體同時爲裸晶片實裝之主動零件的 半導體小片2 1 (主動元件用晶片），及表面實裝型之晶 片電容器或晶片電阻等之電子零件（面實裝零件或具面之 零件同時爲被動零件的晶片零件2 2 (被動元件用晶片） 搭載（混載）於配線基板2上。 又，如第1 ( a )圖所示，高頻模組1係插接帽4之 外周緣與配線基板2之外周緣一致，或是成爲比其位於內 側，又，插接帽4係矩形箱狀地拉深金屬板，成爲具有沿 著下面周緣突出之周壁3之構造。 又如第1 ( b )圖所示，在插接帽4，相對應設有從 其兩側中央之周壁3朝下方突出的鈎支撑臂（鈎支撑部） 1 7，又在該鈎支撑臂1 7之前端側的內側，也設有藉成 形所形成之突出的鈎爪1 8。由該鈎爪1 8與鈎支撑臂 ---------^^衣-- (請先閲讀背面之注意事項再填寫本頁) 、?τ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -10- 550766 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（8 ) 1 7形成具彈力之擋止部的鈎1 9。 插接帽4之厚度係例如約0 . 1 m m，藉由無鍍之鎳 銅鋅合金，或施以鑛鎳之磷青銅等所形成，由此提高與銲 劑之濕潤性。 在配線基板2之兩側中央部，形成有鈎支撑臂1 7所 配置之凹陷部1 5，又在該凹陷部1 5之底，形成有更凹 下之鈎住部1 6，鈎1 9之鈎爪1 8卡合於該鈎住部1 6 〇 又，藉形成凹陷部1 5，在鈎爪1 8鈎在鈎住部1 6 之狀態下，鈎支撑臂1 7不會比凹陷部1 5更突出至外側 〇 利用鈎支撑臂1 7藉由金屬板所形成，可將彈力作用 於鈎1 9。因此，插接帽4之周壁3前端接觸於配線基板 2之主面，且利用鈎爪1 8具彈力鈎在配線基板2之背面 ，可將插接帽4確實地固定於配線基板2。 此時，鈎1 9係利用將彈力作用於配線基板2，也可 容易地拆下插接帽4。 又，對於配線基板2與插接帽4之插接帽4之卡止部 ，也可以爲其他之構造。 又如第2圖所示，在配線基板2之背面設有複數外部 端子5，此等之外部端子5係在配線基板2背面之長度方 向兩側分別以大約一定間隔配置，在一方之列（表示於第 2圖之上側之列），由左向右設有輸入端子（p 1 n 6 ) ，接地端子（G N D ) 7，接地端子（G N D ) 8及聞偏 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇><297公釐） -11 - 550766 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（9 ) 壓子（V g ) 9，且在另一方之列（表示於第2圖之下側 之列），由左向右設有輸出端子（P 〇 u t ) 1 0，接地 端子（G N D ) 1 1，接地端子（G N D ) 1 2及電源端 子（V d d ) 1 3。 在對應於輸入端子6，閘偏壓端子9，輸出端子1〇 及電源端子1 3之配線基板2之側面，如第1圖（a )圖 所示，端面通孔2 0設在從配線基板2之表面至背面之所 有部位。此乃將高頻模組1實裝在印刷配線基板等之實裝 基板時，成爲各外部端子5連接實裝配線基板2之背面之 電極部分與側面之端面通孔2 0部分，由此，可進行高頻 模組1之確實實裝。 在配線基板2之背面延伸成能區劃四個接地端子7、 .8、11、1 2之領域，設有藉由不會濕潤實裝高頻模組 1時所使用之實裝用接合材（例如銲劑）之材料所形成的 樹脂膜1 4。 在高頻模組1，如第1 ( b )圖所示，晶片零件2 2 搭載於配線基板2之表面，且半導體小片2 1經由銲劑接 合部2 6搭載於形成在配線基板2之表面的模穴部之凹部 2 a 〇 又，晶片零件2 2係形成銲劑接合輪廓2 5而與配線 基板2之表面於第5 ( b )圖之晶片零件用電極2 b (被 動元件用晶片用端子）進行銲劑接合，另一方面，半導體 小片2 1係其表面電極之襯墊藉由金線等之線2 4與配線 基板之基板側端子2 i相連接。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）~一 ' -12- (請先閱讀背面之注意事項再填寫本頁) 衣· 550766 A7 B7 五、發明説明（10) 半導體小片2 1與線2 4係藉由環氧樹脂等之封閉用 樹脂2 3被樹脂封閉。 (請先閱讀背面之注意事項再填寫本頁) 高頻模組1之大小係例如寬度8 m m，長度1 2 · 3 m m，高度 1 · 3 m m。 以下，使用第1圖至第5圖，說明本實施形態之一高 頻模組1 (半導體裝置）之製造方法之槪略，及賦於配線 基板2之不良標誌2 e。 經濟部智慧財產局員工消費合作社印製 高頻模組1係藉由表示於第3圖之裝配順序（製程） 進行裝配者，各該過程係成爲晶片零件搭載用之銲劑印刷 (步驟S 1，第4 ( a )圖），半導體小片搭載用之銲劑 接合（步驟S 2，第4 ( b )圖），晶片零件2 2之搭載 的零件搭載〔步驟S 3，第4 ( c )圖〕，半導體小片 2 1之搭載的小片搭載（步驟S 4，第4 ( d )圖），銲 劑之溶融熱處理（包含洗淨（步驟S 5 ))，溶融熱處理 後之自動外觀檢查（步驟S 6 )，連線銲接（步驟S 7， 第4 ( e )圖），連線銲接後之外觀檢查（步驟S 8 )， 封閉用樹脂2 3 (樹脂）之塗布的樹脂塗布（步驟S 9， 第4 ( f )圖），插接帽插入（包含具標誌（步驟S 1 〇 ，第4 ( g )圖），將多數個收納基板2 7分割成個片基 板之配線基板2的基板分割（步驟S 1 1 )，高頻模組1 之特性選別（步驟S 1 2，第4 ( h )圖）及高頻模組1 之用帶縛住（步驟S 1 3，第4 ( i )圖）。 上述各過程中，步驟S 1之銲劑印刷至步驟S 1 〇之 插接帽插入（包含具標誌），係在複數配線基板2所形成 本紙張尺度適用中國國家標準（CNS ) A4規格（X 297公慶） -13- 550766 A7 B7 五、發明説明（11) (請先閱讀背面之注意事項再填寫本頁) 之多數個收納基板2 7之狀態下進行各處理，之後，在步 驟S 1 1進行將多數個收納基板2 7分割成個片基板之配 線基板的基板分割，結果，步驟S 1 2之特性選別與步驟 S 1 3之用帶縛住，係成爲具有配線基板2之高頻模組1 之形態的處理。 因此，在高頻模組1之裝配過程之最終階段爲止，將 多數個收納基板2 7不分割地製造各各配線基板2，可減 低高頻模組1之製造成本及材料成本，可進行溶融之裝置 而可謀求製造生產線之合理化。 又，在實施形態二詳述各該過程之各處理內容。 又，在本實施形態一，作爲高頻模組1之製程之所有 整體之特徵，適用如下方法進行裝配。 首先，僅在表示於第5 ( a )圖之經檢查之多數個收 納基板2 7的配線基板2配置晶片零件2 2及半導體小片 2 1而將晶片零件2 2及半導體小片2 1實裝於良品之配 線基板2，由此，在步驟S 1 〇之插接帽插入過程，將插 接帽4僅安裝在良品之配線基板2。 經濟部智慧財產局員工消費合作社印製 亦即，在購入階段之多數個收納基板2 7之配線基板 2之檢查（又，該檢查係基板廠商事先進行，購入經檢查 之基板也可以，又購入後進行檢查也可以）被判定爲不良 之方塊，亦即在配線基板2，如第5 ( a )圖所示，賦於 不良標誌2 e，在以後之一連串之過程（從步驟S 3之零 件搭載至步驟S 1 0之插接帽插入），在各該過程認識不 良標誌2 e，省略對於形成有該不良標誌2 e之配線基板 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 -14 - 550766 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（12) 2之作業。 由此，可謀求高頻模組1之製程刪減與製造生產線之 合理化。 結果，可減低高頻模組1之製造成本。 所謂多數個收納基板購入階段之基板不良，係例如電 路短路或依斷線之電路開放等之電氣性不良，或基板彎曲 或外觀上短路等之外觀不良等。 又，不良標誌2 e係藉由焊接後之洗淨也不會溶解。 且爲了將圖案認識成爲容易，使用半導體用之標誌油墨等 ，塗布上述標誌油墨之後’進f了始烤處理。 又作成同樣，在處理各過程後，分別進行檢查認識在 過程內成爲不良品之過程不良品，而在成爲該過程不良品 之配線基板2賦與不良標誌2 e。由此，在晶片零件2 2 搭載以後之各過程之處理時’藉由認識不良標誌2 e，而 對於賦與不良標誌2 e之配線基板2 (過程不良品未進行 下一*過程之處理。 例如第5 ( b )圖所示，對於賦與不良標誌2 e之配 線基板2，在表示於第3圖之步驟S 3之零件搭載過程， 藉由圖案認識來檢出不良標誌2 e。而在成爲不良方塊之 配線基板2未進行晶片零件2 2之搭載。 同樣地，在步驟S 4之小片搭載過程，也藉由圖案認 識來檢出不良標誌2 e ’而在成爲不良方塊之配線基板2 未進行半導體小片2 1之搭載。 又在步驟S 6之零件與小片搭載後之自動外觀檢查’ 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0x297公釐） (請先閱讀背面之注意事項再填寫本頁) -15 - 550766 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（13) 藉由圖案認識來檢出不良標誌2 e ’未進行檢查而計數作 爲不良。此時’在該自動外觀檢查被判定爲不良之方塊（ 配線基板2 ) ’如第5 ( c ) B所示’即藉由塗布等賦與 依乾性油墨之不良標誌2 e。 又在步驟S 7之連線銲接過程中，也藉由圖案認識來 檢出購入時之不良標誌2 e及零件與小片搭載後外觀檢查 時之不良標誌2 e ’而在成爲不良方塊之配線基板2未實 行連線銲接。 又在步驟S 8之連接銲接膜後之外觀檢查，作爲連線 銲接外觀不良，如第5 ( d )圖所示，亦即藉由塗布等賦 與依乾性油墨之不良標誌2 e。 又在步驟S 9之樹脂塗布過程中，藉圖案認識檢出購 入時之不良標誌2 e，零件與小片搭載後外觀檢查時之不 良標誌2 e及連線銲接後外觀檢查時之不良標誌2 e ，而 在成爲不良配線基板2未進行樹脂塗布。 同樣地，在步驟S 1 〇之插接帽插入過程中，也藉圖 案認識檢出購入時之不良標誌2 e，零件與小片搭載後外 觀檢查時之不良標誌2 e及連線銲接後外觀檢查時之不良 標誌2 e，而在成爲不良方塊之配線基板2未進行插接帽 插入。 又在步驟S 1 1之基板分割過程中，藉感測器等檢出 有無插接帽4，將賦與插接帽4之配線基板2收納作爲良 品，另一方面，未賦與插接帽4之配線基板2係處理作爲 不良。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 -16 - (請先閱讀背面之注意事項再填寫本頁) 550766 A7 _ —___B7 五、發明説明（Μ) 由此，由於可省略對於下一過程之不良方塊（配線基 板2 )之作業，因此，可謀求高頻模組1之製程刪減與製 造生產線之合理化。 結果，可減少高頻模組1之製造成本。 多數個收納基板2 7係例如多層配線之陶瓷基板，作 爲例子，其大小係配線基板2形成4 0個時，爲 7 8 · 7 5 m m X 7 5 _ 0 0 m m。但是，多數個收納基 板2 7係陶瓷基板以外之玻璃環氧系基板等也可以。 以下，使用第1圖至第2 2圖說明本發明實施形態二 〇 又，實施形態二係依照表示於第3圖之高頻模組1之 裝配順序（製造處理流程），詳述各該過程之處理者。 又在多數個收納基板2 7之各配線基板2，隨者裸晶 片實裝之半導體小片2 1及晶片零件2 2之數量，如第5 (b )圖所示，一或複數半導體小片搭載用之凹部2 a或 晶片零件搭載用之晶片零件用電極2 b形成在其表面，如 第7 ( b )圖所示，藉由各種表面配線2 d連接有該晶片 零件用電極2 b。 首先，對於表示於第7 ( a )圖之多數個收納基板 2 7進行步驟S 1之銲劑印刷。 此時，在多數個收納基板2 7之表示於第7 ( b )圖 的配線基板2之表面2 7 a之晶片零件用電極2 b〔參照 第5 ( b )圖〕進行銲劑印刷，形成如第4 ( a )圖及第 7 ( c )圖之印刷銲劑圖案2 c ° 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇>< 297公釐） L.-------衣-- (請先閱讀背面之注意事項再填寫本頁) -訂 經濟部智慧財產局員工消費合作杜印製 l·—. -17- 550766 A7 B7 五、發明説明（15) 又上述銲劑印刷係例如使用銲劑遮光罩之絲網印刷等 〇 (請先閲讀背面之注意事項再填寫本頁) 上述銲劑印刷後，進行表示於步驟S 2之銲劑接合。 在此，將銲劑藉由接合塗布於多數個收納基板2 7之 各該配線基板2之凹部2 a，如第4 ( b )圖及第7 ( c )圖所不’形成接合鍵接2 f。 又如第6圖所示，作爲從銲劑接合用之噴嘴2 8吐出 銲劑時之噴嘴2 8之移動軌跡2 9，在一枚多數個收納基 板2 7上，將噴嘴2 8在鄰接配線基板2內之凹部2 a間 ，如第6 ( a )圖所示，以最短距離且連續動作地移動， 同時如第6 ( b )圖所示，對於多數個收納基板2 7之鄰 接的其他配線基板2，也以最短距離且連續動作地移動。 又控制該噴嘴2 8之移動軌跡2 9，係藉由搭載位置 座標程式加以設定。 經濟部智慧財產局員工消費合作社印製 如本實施形態二，首先，將銲劑（印刷銲劑圖案2 c )印刷在配線基板2之晶片零件用電極2 b ’然後’在配 線基板2之凹部2 a藉由接合塗布銲劑。由於先進行銲劑 印刷，因此，銲劑印刷時之上述銲劑遮光罩藉由接合之銲 劑而可防止弄髒。 又，在依噴嘴2 8之銲劑接合時，由於以最短距離來 移動噴嘴2 8，結果，可縮短接合時間’因此可提高銲劑 接合過程的生產量。 然後，進行表示於第3圖之步驟S 3之零件搭載’零 件搭載後，進行表示於步驟S 4之小片搭載。 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇><297公釐） -18- 550766 A7 B7__ 五、發明説明（16) 在此，說明在上述零件搭載所使用之表示於第8 ( a )圖之零件搭載裝置3 〇之構成。 (請先閲讀背面之注意事項再填寫本頁) 零件搭載裝置3 〇係將晶片零件2 2移載於多數個收 納基板2 7之配線基板2，並將晶片零件2 2搭載於配線 基板2上者，如第8 ( b )圖所示，由將收納之晶片零件 2 2〔參照第5 ( c )圖〕可依其每一種類（例如品種等 )所送出的第一零件供應部3 1 (零件供應部）與第二零 件供應部3 2 (零件供應部），及支撑多數個基板2 7之 X y台面3 4，及在xy台面3 4上進行晶片零件2 2之 搭載的搭載頭部3 3，及進行多數個收納基板2 7之運送 的基板運送部3 5所構成。 第一零件供應部3 1及第二零件供應部3 2係如帶進 給器或表體進給器，朝水平方向滑動自如地設於基板運送 部3 5之基板運送方向。 經濟部智慧財產局員工消費合作社印製 因此，在零件搭載裝置3 0欲進行晶片零件2 2之搭 載時，第一零件供應部3 1及第二零件供應部3 2中，將 分別收納之晶片零件2 2 (在此，爲零件A ’零件B ’零 件C，零件D，零件E，零件F )以零件供應單位供應配 置於配線基板2。 由此，如第4 (c)圖及第1〇(a)圖所示，在配 線基板2上搭載晶片零件2 2。 例如，首先，將第一零件供應部3 1之所有晶片零件 2 2搭載於整體被動元件用晶片2 7，之後，將第二零件 供應部3 2之所有晶片零件2 2搭載於整體被動元件用晶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -19- 550766 A7 B7 五、發明説明（17) 片2 7。 由此，可縮短第一零件供應部3 1及第二零件供應部 (請先閱讀背面之注意事項再填寫本頁) 3 2之移動距離，結果可提高零件搭載時間之生產量。 又在第一零件供應部3 1收納某一品種之晶片零件 2 2，另一面，在第二零件供應部3 2收納其他品種之晶 片零件2 2，也可成爲每一品種之零件搭載。 又在搭載晶片零件2 2時，認識形成於配線基板2之 晶片零件用電極2 b之印刷銲劑圖案2 c並在印刷銲劑圖 案2 c上配置晶片零件用電極2 b。 由此，銲劑溶融熱處理時，藉印刷銲劑圖案2 c之自 動對準效果，由於經由印刷銲劑圖案2 c確實連接晶片零 件2 2之端子與晶片零件用電極2 b，因此即使形成印刷 銲劑圖案2 c與晶片零件用電極2 b偏離之情形，也可防 止此時容易發生之零件站立或是零件浮起等之不良發生。 以下，說明步驟S 4之小片搭載所用之表示於第9 ( a )圖之小片搭載裝置3 6之構成。 經濟部智慧財產局員工消費合作社印製 小片搭載裝置3 6係係將半導體小片2 1移載至多數 個收納基板2 7之之配線基板2之凹部2 a，如此，，將 半導體小片2 1搭載於配線基板2之凹部2 a者，如第9 (b )圖所示，由將收納之半導體小片2 1依其每一種類 (例如品種等）可送出之小片供應系統3 7，及進行半導 體小片2 1之搭載的接合頭部3 8，及進行多數個收納基 板2 7之運送的基板運迭部3 9 ’及顯不接合位置的監測 4 0所構成。 本紙張尺度適用中國國家標準（CNS )八私見格（210X297公釐） " " 20- 550766 A7 B7 五、發明説明（1S) 又在小片供應系統3 7係例如設有四個零件供應部的 第一小片供應部3 7 a，第二小片供應部3 7 b，第三小 片供應部3 7 c，及第四小片供應部3 7 d ;上述零件供 應部係例如晶片托盤等；在小片供應系統3 7中分別安裝 於旋轉方塊3 7。又小片搭載裝置3 6之半導體小片2 1 之搭載方法，係例如來自晶片托盤等之小片供應部或半導 體晶圓之直接拾取方式。 因此，在小片搭載裝置3 6之小片供應系統3 7中欲 進行半導體小片2 1之搭載時，將第一小片供應部3 7 a ，第二小片供應部3 7 b，第三小片供應部3 7 c及第四 小片供應部3 7 d中，將收納於各該供應部的半導體小片 2 1 (在此爲小片A，小片B，小片C，小片D )以零件 供應部單位供應配置在配線基板2。 由此，如第4 (d)圖及第10(b)圖所示，將半 導體小片2 1搭載於配線基板2之凹部2 a。 例如，首先將第一小片供應部3 7 a之所有半導體小 片2 1搭載於整體多數個收納基板2 7，之後，將旋轉方 塊3 7施以旋轉，將第二小片供應部3 7 b之所有半導體 小片2 1搭載於整體多數個收納基板2 7。又，將旋轉方 塊3 7 e施以旋轉，依次分別將第三小片供應部3 7 c， 第四小片供應部3 7 d之半導體小片2 1搭載於整體多數 個收納基板2 7。 由此，可縮短第一小片供應部3 7 a，第二小片供應 部3 7 b，第三小片供應部3 7 c及第四小片供應部 本紙張尺度適用中國國家標準（cns ) a4規格（2 ι〇χ297公釐） L.--------衣— (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -21 - 550766 A7 經濟部智慧財產局員工消費合作社印製 _____B7_五、發明説明（19) 3 7 d之移動距離，結果可提高小片搭載時間之生產量。 由於在各該上述小片供應部收納不同品種或不同品位 之半導體小片2 1，也可成爲每一品種或每一品位之小片 搭載。 又在搭載半導體小片2 1時認識表示於第1 0 ( b ) 圖之配線基板2之凹部2 a之緣部2 g而將半導體小片 2 1配置於凹部2 a。 由此，可提高凹部2 a之位置認識精度，結果，可將 凹部2 a之大小成爲比半導體小片2 1之大小稍大之程度 〇 因此可減少凹部2 a內之半導體小片2 1之搖晃，結 果，可提高半導體小片2 1之水平方向之配置傾斜精度。 由此，可容易地進行連線接合時之半導體小片2 1之 襯墊（表面電極）之認識，結果，可減低連線接合不良。 又先進行晶片零件2 2之搭載，之後由於進行半導體 小片2 1之搭載，可減低半導體小片2 1之損傷要因。 亦即，由於半導體小片2 1係藉由來自外部之應力等 成爲不良之機率與晶片零件2 2相比較較高，因此搭載晶 片零件2 2之後搭載半導體小片2 1者較理想，由此可減 低損傷半導體小片2 1之可能性。 之後，進行表示於第3圖之步驟S 5之溶融熱處理。 在此，進行多數個收納基板2 7之銲劑溶融熱處理， 一起銲劑接合配線基板2上之晶片零件2 2及半導體小片 2 1。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁) -22- 550766 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（20) 然後，進行步驟S 6之自動外觀檢查。 在此，進行溶融熱處理後之多數個收納基板2 7之外 觀檢查，來檢查有無溶融熱處理。 此時，在搭載零件之位置檢出，使用雷射光等進行位 置檢出時，藉在配線基板2上認識段差部位，可精度優異 地認識搭載零件之位置。 例如藉認識形成在第1 1 ( a )圖之多數個收納基板 2 7之配線基板2的表示於第1 1 ( b )圖之通孔2 h或 表示於第7 ( b )圖之表面配線2 d等，可精度優異地認 識搭載零件之位置。 然後，進行表示於步驟S 7之連線接合。 在此，例如第4 ( e )圖所示，使用金線等之線2 4 進行連線接合，藉由線2 4來連接半導體小片2 Γ之表面 電極之襯墊與對應於該襯墊之多數個收納基板2 7之配線 基板2之基板側端子2 i 〔參照第5 ( b )圖〕。 之後，進行表示於步驟S 8之外觀檢查。 在此’進行連線接合後之多數個收納基板2 7之外觀 檢查，俾檢查有無連線接合不良。 然後’進行表示於步驟S 9之樹脂（封閉用樹脂2 3 )塗布。 在此’如第4 ( f )圖所示，藉由接合方法，將封閉 用樹脂2 3滴下在多數個收納基板2 7之配線基板2的凹 部2 a上’由此’利用封閉用樹脂2 3來樹脂封閉半導體 小片2 1及線2 4。 本^張尺度適用中國國家標準（CNS ) &格（21〇'χ 297公釐） ' -23- (請先閱讀背面之注意事項再填寫本頁) 550766 A7 B7 經濟部智慧財產局員工消費合作社印製 五、 發明説明 ( 21) 1 I 此 時 5 避 開 表 示於第 1 2 (a )圖之多數個收納 基板 1 1 1 2 7之分 割 用 槽 部 2 7b 藉 接合 將封閉用樹脂2 3 塗布 1 1 V 在 配線 基 板 2 之 凹 部2 a 5 俾 樹脂封閉多數個收納基 板 ^-V Γ 2 1 ° 清 先 閱 I 之樹脂塗布範圍4 讀 1 I 亦即 如 表 示 第1 2 ( b )圖 1所 背 1 I 示 ，在 每 一 個 片 方 塊，亦即 每 一多 數個收納基板2 7 上之 之 注 意 1 1 I 各 配線 基 板 2 進 行封閉用 樹 脂 2 3 之塗布，使封閉用 樹脂 事 項 再 1 1 2 3不 會 施 加 形 成在多數 個 收 納基 板2 7之個片基板分割 填 馬 用 縫隙 的分 割 用 樹 脂2 3 〇 頁 、«W✓ 1 1 因 此 由 於在多數個收 納 基板 2 7之分割用槽部 1 2 7 b 未 施 加 封 閉 用樹脂 2 3 ，由 此，從表示於第1 1 ( 1 1 I b )圖 之 通 孔 2 h 等使封 閉 用 樹脂 2 3進入而流進基 板背 1 訂 1 面 ，結 果 ， 可 防 止 對於基 板 分 割時 等之不良影響。 1 1 之 後 進 行 表 示於步 驟 S 10 之插接帽插入。 1 1 又 5 在本 實 施 形態二 之 插 接帽 插入過程中，對於 表不 1 於 第1 3 圖 之 插 接 帽4， 以 —^ 貫處 理連續進行認識標 誌之 9k I 標 誌4 2 之 U V ( Ultra Violet)乾 燥，依標誌4 2之 圖案 1 1 認 識之 標 誌 外 觀 檢 查及插 接 帽 插入 ，又在上述插接帽 插入 1 1 時 ，藉 由 標 誌 外 觀 檢查， 僅 將 判定 爲良品之插接帽4 進行 1 1 插 接帽 插 入 者 5 由 此可謀 求 縮 短插 接帽插入過程之裝 配時 1 I 間 ，同 時 5 可 將 賦 有其他 標 誌 4 2 之插接帽4混入防 範於 I 未 然。 1 1--I 首先 3 在 上 述 插接帽 插 入 過程 進行對於插接帽4 之標 1 1 誌 4 2 之 打 標 誌 〇 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -24 - 550766 A7 B7 五、發明説明（22) 又，如第1 3 ( a ) ，( b ) ，（ c )圖所示，插接 帽4係例如金屬板等所構成之箱型者，相對應設有支撑可 卡合於多數個收納基板2 7之配線基板2之表示於第1圖 之鈎1 9的鈎支撑臂1 7 (鈎支撑部）。 又，如第1 4圖所示，認識標誌之標誌4 2係例如爲 高頻模組1之製造號碼或模具號碼等，文字或記號所構成 者。 在此，將標誌4 2賦與插接帽4之表面4 a。 然後U V乾燥標誌4 2，乾燥後，藉由圖案認識進行 標誌之外觀檢查，由此，選別賦有良品標誌4 2之插接帽 4 。 之後’將成爲良品之插接帽4 一 一^地插進多數個收納 基板2 7之配線基板2。 又，由於進行賦有標記4 2之插接帽4之標記4 2之 檢查後僅將良品之插接帽4之安裝於配線基板2，可防止 無標誌，不良標誌或是其他標誌4 2之插接帽4等不良品 插接帽之安裝。 由此，由於不會安裝有關於標誌4 2之不良品插接帽 ，因此，可謀求製造生產線之合理化。 以下，說明插接帽4之插入（裝設）方法。 在此，說明在插接帽插入過程所使用之表示於第1 5 (a )圖及第1 6圖之插接帽裝設裝置44之構成。 插接帽裝設裝置4 4係由：支撑多數個收納基板2 7 之X y工作台4 5，及進行插接帽裝設之裝設單元4 6， 本紙張尺度適用中.國國家標準（CNS ) Α4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -7- 550766 A 7 B7 V. Description of the invention (5) The process of sealing the above-mentioned active device wafer with grease. (Please read the precautions on the back before filling in this page.) The manufacturing method of the semiconductor device of the present invention is a manufacturing method of a semiconductor device in which a passive element wafer and an active element wafer are mounted on a wiring substrate and assembled. It is characterized in that the wiring board for the passive device and the wafer for the active device are arranged on a plurality of the storage substrates formed by the plurality of wiring boards, and the wafer for the passive device and the wafer for the active device are mounted on the wiring board. The process of the above wiring substrate; and one of the above-mentioned hook support portions of one of the plug caps corresponding to the hook support portions that can be engaged with the hooks of the wiring substrate is inserted obliquely into the hook holes of the plurality of storage substrates. The process of installing the plug cap on the plurality of storage substrates; covering the wafers for the passive components and the wafers for the active components on the wiring substrates of the plurality of storage substrates by the plug caps. The semiconductor device manufacturing method printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the present invention belongs to a manufacturing method of a semiconductor device in which a passive element wafer and an active element wafer are mounted on a wiring substrate and assembled. : A process of disposing the above-mentioned passive device wafer with the selected wiring substrate; and a process of disposing the selected active device wafer with the recessed portion of the wiring substrate; and placing the passive device wafer with the active device wafer The process of mounting on the wiring substrate by solder bonding; assembling the selected wiring substrate and the chip for the active device separately, and implementing the characteristics of the semiconductor device into the allowable range. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -8- 550766 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 V. Description of the invention (6) (the best form for implementing the invention) In the following embodiments, the explanation of the same or the same part will not be repeated in principle except in special cases. In addition, in the following embodiments, for convenience, the plural inventions are described in two embodiments, except for the case where it is specifically stated, of course, each step may not necessarily explain all the explanations. In the following embodiments, for the sake of convenience, they are described in plural sections or embodiments separately, but except for the cases explicitly stated, these systems are not independent of each other. Part of or all of the modifications of one of the parties will fully explain the relationship between the description and the like. In the following embodiments, the number of elements (including the number, number, number, range, etc.), except for the case where it is specifically stated and the case where it is clearly limited to a specific number in principle, The number is not limited to the specific number, and may be one or more or less. Moreover, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily required unless they are explicitly stated or clearly considered necessary in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the constituent elements and the like are not explicitly stated or considered to be inconceivable in principle, the shapes and the like actually include approximate values Or similar. The same applies to the above-mentioned numbers and ranges. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiment, members having the same function are given the same reference numerals, and repeated descriptions thereof are omitted. 1Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ~ 1 ~ -9- (Please read the precautions on the back before filling out this page) 550766 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7. Description of the invention (7) The first embodiment of the present invention is shown using the diagram showing the structure of the semiconductor device (high-frequency module 1) shown in Figs. 1 and 2 to show the assembly of the high-frequency module 1 of Fig. 3. The sequential drawings are shown in the cross-section of each of the main processes of the wiring substrate in FIG. 4 and the diagrams of the defective identification wiring substrate in FIG. 5 are described. The semiconductor device assembled by the method for manufacturing a semiconductor device according to this embodiment shown in FIGS. 1 and 2 is a high-frequency power amplifier device called a high-frequency module 1 (also referred to as a high-frequency power module). The plug cap 4 is superimposed on the main surface (upper surface) of the plate-shaped wiring board 2 and has a flat rectangular structure in appearance. Therefore, small-sized portable electronic devices, such as mobile phones, are assembled into small semiconductor chips 2 1 (active element wafers) with field-effect transistors and active components mounted on bare wafers, and surface-mounted devices. Electronic components such as chip capacitors or chip resistors (surface-mounted components or surface-mounted components that are also passive components) 2 2 (passive component wafers) are mounted (mixed) on the wiring substrate 2. Also, as described in Section 1 ( a) As shown in the figure, the outer periphery of the high-frequency module 1 series of the plug cap 4 is consistent with the outer periphery of the wiring board 2 or is located on the inside, and the plug cap 4 is a rectangular box-shaped metal plate, It has a structure having a peripheral wall 3 protruding along the peripheral edge of the lower surface. As shown in FIG. 1 (b), the plug cap 4 is provided with a hook support arm correspondingly protruding downward from the peripheral wall 3 at the center of both sides ( Hook support part 1) 17, and on the inner side of the front end side of the hook support arm 17, there is also a protruding hook 18 formed by forming. The hook claw 18 and the hook support arm ---- ----- ^^ 衣-(Please read the notes on the back before filling this page ),? Τ This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -10- 550766 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) 1 7 The hook 19 of the stopper portion. The thickness of the plug cap 4 is, for example, about 0.1 mm, and is formed of an unplated nickel-copper-zinc alloy, or phosphor bronze applied with mineral nickel, thereby improving the flux with the solder. In the center of both sides of the wiring board 2, a recessed portion 15 in which the hook support arms 17 are arranged is formed, and a lower recessed hooking portion 16 is formed in the bottom of the recessed portion 15 The hook claw 18 of the hook 19 is engaged with the hooking portion 16 and the recessed portion 15 is formed. When the hook claw 18 is hooked to the hooking portion 16, the hook support arm 17 does not It will protrude to the outside than the recessed portion 15. The hook support arm 17 is formed by a metal plate, and the elastic force can be applied to the hook 19. Therefore, the front end of the peripheral wall 3 of the plug cap 4 contacts the main of the wiring substrate 2. Surface, and using the hook claw 18 with eight elastic hooks on the back of the wiring board 2, the plug cap 4 can be fixed to the wiring board 2. At this time, the hook 1 9 series It is also possible to easily remove the plug cap 4 by applying an elastic force to the wiring substrate 2. The locking portion of the plug cap 4 of the wiring substrate 2 and the plug cap 4 may have another structure. As shown in FIG. 2, a plurality of external terminals 5 are provided on the back surface of the wiring substrate 2. These external terminals 5 are arranged at regular intervals on both sides in the length direction of the back surface of the wiring substrate 2, and are arranged in one row (shown in FIG. The upper column in Figure 2), from left to right, there are input terminals (p 1 n 6), ground terminals (GND) 7, ground terminals (GND) 8 and smell (please read the precautions on the back before filling (This page) This paper is in accordance with Chinese National Standard (CNS) A4 specification (21〇 < 297 mm) -11-550766 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention (9) (V g) 9, and in the other side (shown in the lower column of Figure 2), from left to right are provided with output terminals (P 〇ut) 1 0, ground terminals (GND) 1 1, Ground terminal (GND) 1 2 and power terminal (V dd) 1 3. On the side of the wiring board 2 corresponding to the input terminal 6, the gate bias terminal 9, the output terminal 10, and the power terminal 13, as shown in FIG. 1 (a), the end surface through hole 20 is provided on the slave wiring board. 2 from the surface to all parts of the back. When the high-frequency module 1 is mounted on a printed circuit board or other mounting substrate, the external terminal 5 connects the electrode portion on the back surface of the assembly line substrate 2 and the end surface through-hole 20 portion on the side surface. Group 1 is indeed installed. The area on the back of the wiring board 2 is extended so that the four ground terminals 7, 8, 8, 11, and 12 can be divided, and a bonding material for mounting (such as a solder) used when mounting the high-frequency module 1 is not wetted. ) Of the resin film 1 4. In the high-frequency module 1, as shown in FIG. 1 (b), the chip component 2 2 is mounted on the surface of the wiring substrate 2, and the semiconductor chip 21 is mounted on a cavity formed on the surface of the wiring substrate 2 through the solder joint portion 26. The recessed part 2 a of the part is formed with a solder joint profile 25, and the surface of the wiring board 2 is soldered to the electrode 2 b (terminal for wafers for passive components) on the surface of the wiring board 2 as shown in FIG. 5 (b). Bonding, on the other hand, the semiconductor chip 21 is connected to the substrate-side terminal 2 i of the wiring substrate via a wire 24 of a gold wire or the like on the surface electrode pad. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ 1 '-12- (Please read the precautions on the back before filling this page) Clothing · 550766 A7 B7 V. Description of the invention (10) Semiconductor chip The 2 1 and the wire 2 4 are sealed with a resin 2 3 by an epoxy resin or the like. (Please read the precautions on the back before filling this page) The size of the high-frequency module 1 is, for example, 8 m m in width, 1 2 · 3 m m in length, and 1 · 3 m m in height. Hereinafter, using FIG. 1 to FIG. 5, a description will be given of a manufacturing method of the high-frequency module 1 (semiconductor device) according to this embodiment, and a defect mark 2 e assigned to the wiring substrate 2. The high-frequency module 1 printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economics is assembled by the assembly sequence (process) shown in FIG. 3, and each of these processes is a solder printing for mounting chip parts (step S1, step 4 (a)), solder bonding for semiconductor chip mounting (step S2, FIG. 4 (b)), component mounting for wafer part 22 [step S3, FIG. 4 (c)], semiconductor chip 21 1 chip mounting (step S 4, Figure 4 (d)), melt heat treatment of the flux (including cleaning (step S 5)), automatic appearance inspection after the melt heat treatment (step S 6), wiring Welding (step S 7, FIG. 4 (e)), visual inspection after wire welding (step S8), sealing resin coating with resin 2 3 (resin) coating (step S9, 4 (f)) (Figure), the plug cap is inserted (including the marked (step S 1 0, figure 4 (g)), the substrate of the wiring substrate 2 is divided into a plurality of storage substrates 2 7 into a single substrate (step S 1 1) , Selection of characteristics of high-frequency module 1 (step S 1 2, Figure 4 (h)) and high-frequency module 1 Tie with a strap (step S 1 3, figure 4 (i)). In each of the above processes, the solder of step S 1 is printed to the plug cap of step S 1 〇 (including the mark), which is attached to a plurality of wiring substrates. 2 The paper size formed by this paper is applicable to Chinese National Standard (CNS) A4 specification (X 297 public holiday) -13- 550766 A7 B7 V. Description of the invention (11) (Please read the precautions on the back before filling this page) Each process is performed in the state of the storage substrate 27, and then, in step S11, the substrate division of the wiring substrate that divides the plurality of storage substrates 27 into individual substrates is performed. As a result, the characteristic selection of step S1 and step S2 The binding with 1 3 is a process that becomes the form of the high-frequency module 1 with the wiring substrate 2. Therefore, until the final stage of the assembly process of the high-frequency module 1, a plurality of storage substrates 2 7 are manufactured without division. The wiring substrate 2 can reduce the manufacturing cost and the material cost of the high-frequency module 1. The melting device can be used to rationalize the manufacturing production line. Also, the processing content of each of these processes will be described in detail in the second embodiment. In this implementation, Form one, as an overall feature of the manufacturing process of the high-frequency module 1, the following method is applicable for assembly. First, the wafer components are arranged only on the wiring substrate 2 of the plurality of storage substrates 27 shown in FIG. 5 (a) that have been inspected. 2 2 and the semiconductor chip 21 and the wafer part 22 and the semiconductor chip 21 are mounted on the good-quality wiring substrate 2. Therefore, in the plug cap insertion process of step S 1 〇, the plug cap 4 is only mounted on Good quality wiring board 2. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, that is, the inspection of wiring board 2 containing a large number of substrates 2 7 in the purchase stage (also, this inspection is performed in advance by the substrate manufacturer The substrate can also be used, and it can also be inspected after purchase.) The block judged to be defective, that is, the wiring substrate 2, as shown in Figure 5 (a), is assigned a defective mark 2e, which will be a series of processes in the future ( From mounting the part in step S 3 to inserting the plug cap in step S 10), recognize the defective mark 2 e in each process, and omit the paper size applicable to the wiring board on which the defective mark 2 e is formed. Standard (CNS) A4 size (210X297 mm) a -14 - 550766 A7 B7 Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed V. invention is described in (12) 2 of the job. Therefore, it is possible to reduce the manufacturing process of the high-frequency module 1 and rationalize the manufacturing production line. As a result, the manufacturing cost of the high-frequency module 1 can be reduced. Defective substrates at the stage of purchase of a plurality of storage substrates include, for example, electrical failures such as short circuits or open circuits due to disconnection, or appearance failures such as a bent substrate or an external short circuit. In addition, the defective mark 2 e is not dissolved by washing after welding. In order to make it easier to recognize the pattern, a marking ink for semiconductors is used, and the marking ink is applied to the baking process. In the same manner, after each process is processed, inspection is performed to recognize a process defective product that has become a defective product during the process, and the wiring board 2 that has become a defective product is assigned a defective mark 2e. Therefore, at the time of processing of each process after the wafer component 2 2 is mounted, by recognizing the defective mark 2 e, the wiring board 2 to which the defective mark 2 e is given (the defective product of the process is not processed in the next * process). For example, as shown in FIG. 5 (b), for the wiring board 2 to which the defective mark 2e is given, during the component mounting process shown in step S3 of FIG. 3, the defective mark 2e is detected by pattern recognition. The wafer component 22 is not mounted on the wiring substrate 2 that becomes a defective block. Similarly, in the chip mounting process of step S4, the defective mark 2 e 'is detected by pattern recognition, and the wiring substrate that is a defective block is detected. 2 The mounting of the semiconductor chip 2 1 is not performed. The automatic appearance inspection of the parts and chips after mounting in step S 6 'This paper size applies to the Chinese National Standard (CNS) A4 specification (2 丨 0x297 mm) (Please read the back first Please note this page before filling in this page) -15-550766 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (13) Detecting bad marks 2 through the recognition of the pattern 2 e 'Count without counting At this time, 'the block judged to be defective in this automatic visual inspection (wiring board 2)' as shown in Section 5 (c) B ', that is, the defective mark 2e of the dry ink is applied by coating or the like. In the wire bonding process of step S7, the defective mark 2 e at the time of purchase and the defective mark 2 e 'at the time of appearance inspection after the parts and chips are mounted are also detected by pattern recognition, and the wiring board 2 which is a defective block is not detected. Perform wire welding. Also check the appearance of the welding film after step S8, as the appearance of the wire welding is not good, as shown in Figure 5 (d), that is, the poor mark of the dry ink is given by coating, etc. 2 e. In the resin coating process of step S 9, the defective mark 2 e at the time of purchase is recognized by the pattern, the defective mark 2 e at the appearance inspection after the parts and small pieces are mounted, and the defective at the appearance inspection after the wire welding. The mark 2 e is not coated with resin when it becomes a defective wiring board 2. Similarly, during the insertion of the plug cap in step S 1 0, the defective mark 2 e at the time of purchase is also recognized by the pattern, and parts and chips are mounted. Post visual inspection The defective mark 2 e at the time and the defective mark 2 e at the time of the appearance inspection after the soldering of the wire, but the wiring board 2 which has become a defective block has not been inserted with a plug cap. Also in the process of dividing the substrate in step S 1 1 The tester detects the presence or absence of the plug cap 4 and stores the wiring board 2 provided with the plug cap 4 as a good product. On the other hand, the wiring board 2 not provided with the plug cap 4 is treated as a defective product. This paper applies China National Standard (CNS) A4 specification (210X297 mm) I-16-(Please read the precautions on the back before filling out this page) 550766 A7 _ —___ B7 V. Explanation of the invention (Μ) The operation of the defective block (wiring substrate 2) of a process, therefore, it is possible to seek for the reduction of the manufacturing process of the high-frequency module 1 and the rationalization of the manufacturing production line. As a result, the manufacturing cost of the high-frequency module 1 can be reduced. The plurality of storage substrates 27 are, for example, ceramic substrates of multilayer wiring. As an example, when the number of the wiring substrates 2 is 40, it is 7 8 · 7 5 m x 7 5 _ 0 0 m m. However, a plurality of accommodating substrates, such as glass epoxy-based substrates other than 27-based ceramic substrates, may be used. Hereinafter, Embodiment 2 of the present invention will be described using FIGS. 1 to 22. Embodiment 2 is a detailed description of the processing of each process according to the assembly sequence (manufacturing process flow) of the high-frequency module 1 shown in FIG. 3. By. In each of the plurality of wiring substrates 2 accommodating the substrates 27, the number of the semiconductor chips 21 and the wafer components 22 mounted on the bare wafer is as follows, as shown in FIG. 5 (b), for mounting one or more semiconductor chips. The concave part 2 a or the wafer part electrode 2 b for mounting the wafer part is formed on the surface thereof, and as shown in FIG. 7 (b), the wafer part electrode 2 b is connected by various surface wirings 2 d. First, the plurality of storage substrates 27 shown in FIG. 7 (a) are subjected to solder printing in step S1. At this time, flux printing is performed on the plurality of storage substrates 2 7 on the surface 2 7 a of the wiring substrate 2 shown in FIG. 7 (b) (see FIG. 5 (b)). Figure 4 (a) and Figure 7 (c) of the printed solder pattern 2 c ° This paper size applies the Chinese National Standard (CNS) A4 specification (21〇 > < 297 mm) L .----- -衣-(Please read the notes on the back before filling out this page)-Order the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs to print l · —. -17- 550766 A7 B7 V. Description of the invention (15) and the above The flux printing is, for example, screen printing using a flux hood. (Please read the precautions on the back before filling in this page.) After the above flux printing, perform the flux bonding shown in step S2. Here, the flux is applied to the recessed portions 2 a of each of the plurality of storage substrates 2 7 by bonding, as shown in FIGS. 4 (b) and 7 (c), so as to form a bonding key 2 f. . As shown in FIG. 6, as the movement trajectory 2 9 of the nozzle 2 8 when the solder is discharged from the nozzle 2 8 for solder bonding, the nozzles 2 8 are adjacent to the wiring substrate 2 on a plurality of storage substrates 2 7. As shown in Fig. 6 (a), the inner recess 2a moves continuously with the shortest distance, and as shown in Fig. 6 (b), for the other wiring boards adjacent to the plurality of storage substrates 27 2. It also moves continuously with the shortest distance. In addition, the movement trajectory 29 of the nozzle 28 is controlled, and it is set by the coordinate program of the mounting position. The employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the same as in the second embodiment. First, a solder (printing solder pattern 2 c) is printed on the electrode 2 for wafer parts of the wiring substrate 2 b 'then' on the recess 2 a of the wiring substrate 2 a Flux is applied by bonding. Since the flux printing is performed first, the above-mentioned flux hood during the flux printing can be prevented from being soiled by the bonded solder. In addition, since the nozzle 28 is moved by the shortest distance when the solder is bonded according to the nozzle 28, as a result, the bonding time can be shortened and the throughput of the solder bonding process can be increased. Then, after mounting the parts shown in step S3 of Fig. 3, the parts are mounted, and then the chip mounting shown in step S4 is performed. This paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 〇 < 297 mm) -18- 550766 A7 B7__ V. Description of the invention (16) Here, the description of the use of the above-mentioned parts is shown in FIG. 8 (a) shows the structure of the component mounting device 30. (Please read the precautions on the back before filling in this page.) The component mounting device 3 〇 transfers the wafer component 2 2 to the wiring substrate 2 which contains a large number of storage substrates 2 7 and mounts the wafer component 2 2 on the wiring substrate 2. Alternatively, as shown in Fig. 8 (b), the first part supply unit 3 which can be sent by each of the wafer components 22 to be stored [refer to Fig. 5 (c)] according to each type (for example, variety) 1 (part supply part) and second part supply part 3 2 (part supply part), and the X y table 3 4 supporting a plurality of substrates 2 7, and the wafer parts 2 2 are mounted on the xy table 3 4 The mounting head 3 3 is configured by a substrate transfer unit 35 that transfers a plurality of storage substrates 27. The first parts supply section 31 and the second parts supply section 32 are, for example, a belt feeder or a surface body feeder, and are slidably provided in the substrate conveyance direction of the substrate conveyance section 35 in the horizontal direction. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, when the component mounting device 30 wants to mount the chip component 22, the first component supply section 31 and the second component supply section 32 will be stored separately. The wafer part 2 2 (here, part A 'part B' part C, part D, part E, part F) is supplied and arranged on the wiring board 2 in a parts supply unit. Thereby, as shown in Figs. 4 (c) and 10 (a), the wafer component 22 is mounted on the wiring substrate 2. For example, first, all the wafer parts 22 of the first parts supply unit 31 are mounted on the entire passive component wafer 27, and then all the wafer parts 22 of the second parts supply unit 32 are mounted on the entire passive part. The size of the crystal paper used for components is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -19- 550766 A7 B7 V. Description of the invention (17) Sheet 2 7 As a result, the moving distance between the first parts supply section 31 and the second parts supply section (please read the precautions on the back before filling this page) 3 2 can be shortened, and as a result, the throughput of the part loading time can be improved. In addition, the first component supply unit 31 stores wafer components 2 of a certain variety, and on the other side, the second component supply unit 32 stores wafer components of other varieties 2 2. It can also be a component of each variety. . When mounting the wafer component 22, the printed solder pattern 2c of the wafer component electrode 2b formed on the wiring board 2 was recognized, and the wafer component electrode 2b was arranged on the printed solder pattern 2c. Therefore, during the solder melt heat treatment, the automatic alignment effect of the printed solder pattern 2 c is used to reliably connect the terminals of the wafer component 2 2 and the wafer component electrode 2 b via the printed solder pattern 2 c. Therefore, even if the printed solder pattern 2 is formed, The deviation of c from the wafer component electrode 2 b can also prevent defects such as component standing or component floating that easily occur at this time. Hereinafter, the configuration of the chip mounting device 36 shown in FIG. 9 (a) for the chip mounting in step S4 will be described. The mini-chip mounting device 3, which is a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, transfers the semiconductor chip 21 to the recess 2a of the wiring substrate 2 of the plurality of storage substrates 27. Thus, the semiconductor chip 21 is mounted In the recess 2a of the wiring board 2, as shown in FIG. 9 (b), a semiconductor chip supply system 37 capable of sending the semiconductor chip 21 accommodated according to each type (such as a variety, etc.), and performing semiconductors The bonding head 3 8 mounted on the small piece 21 is composed of a substrate transfer portion 3 9 ′ for carrying a plurality of storage substrates 27 and a monitoring of the bonding position 40. This paper size is in accordance with Chinese National Standard (CNS) Eight Private Dimensions (210X297 mm) " " 20- 550766 A7 B7 V. Description of Invention (1S) In the small film supply system 3 7 series, for example, there are four parts supply departments The first chip supply part 3 7 a, the second chip supply part 3 7 b, the third chip supply part 3 7 c, and the fourth chip supply part 3 7 d; the above-mentioned part supply part is, for example, a wafer tray, etc .; Each of the supply systems 37 is mounted on a rotating block 37. The mounting method of the semiconductor die 21 of the die mounting device 36 is, for example, a direct pick-up method from a die supply section of a wafer tray or the like or a semiconductor wafer. Therefore, when mounting the semiconductor die 21 in the die supply system 37 of the die mounting device 36, the first die supply section 37a, the second die supply section 37b, and the third die supply section 3 In 7 c and the fourth chip supply section 3 7 d, the semiconductor chips 2 1 (here, chip A, chip B, chip C, and chip D) stored in each of the supply sections are supplied and arranged in the unit of the component supply section. Substrate 2. Thereby, as shown in Figs. 4 (d) and 10 (b), the semiconductor chip 21 is mounted on the recess 2a of the wiring substrate 2. For example, first, all the semiconductor chips 21 of the first chip supply section 3 7 a are mounted on the plurality of storage substrates 2 7 as a whole, and then, the rotating block 37 is rotated to rotate all the second chip supply sections 3 7 b. The semiconductor chip 21 is mounted on a plurality of storage substrates 27 as a whole. The rotating block 3 7e is rotated, and the semiconductor chips 21 of the third chip supply section 3 7 c and the fourth chip supply section 3 7 d are mounted on the plurality of storage substrates 27 as a whole, respectively. As a result, the first chip supply unit 37a, the second chip supply unit 37b, the third chip supply unit 37c, and the fourth chip supply unit can be shortened. The paper size applies the Chinese National Standard (cns) a4 specifications ( 2 ι〇χ297 mm) L .-------- Cloth — (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs-21-550766 A7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau _____B7_ V. Description of the invention (19) 3 7 d Moving distance, as a result, the production capacity of the small chip loading time can be improved. Since the semiconductor chips 21 of different varieties or different grades are stored in each of the above-mentioned chip supply units, it can also be mounted as small chips of each variety or grade. When mounting the semiconductor chip 21, the edge portion 2g of the recess 2a of the wiring board 2 shown in Fig. 10 (b) is recognized, and the semiconductor chip 21 is arranged on the recess 2a. As a result, the accuracy of the position recognition of the recessed portion 2 a can be improved. As a result, the size of the recessed portion 2 a can be slightly larger than the size of the semiconductor chip 21 1. Therefore, the shaking of the semiconductor chip 21 in the recessed portion 2 a can be reduced. As a result, it is possible to improve the accuracy of arrangement of the semiconductor chips 21 in the horizontal direction. This makes it easy to recognize the pad (surface electrode) of the semiconductor die 21 at the time of wire bonding, and as a result, poor wire bonding can be reduced. The mounting of the wafer component 22 is performed first, and then the mounting of the semiconductor chip 21 can reduce the damage factor of the semiconductor chip 21. That is, since the semiconductor chip 21 has a higher probability of becoming defective due to stress from the outside and the like than the wafer component 2 2, it is preferable to mount the semiconductor chip 21 after mounting the chip component 2 2, thereby reducing the risk. Possibility of damaging the semiconductor die 21. Thereafter, the melting heat treatment shown in step S5 in FIG. 3 is performed. Here, a plurality of solder melting heat treatments of the storage substrates 27 are performed, and the wafer parts 22 and the semiconductor dice 21 on the wiring substrate 2 are soldered together with the flux. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the notes on the back before filling out this page) -22- 550766 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs Explanation (20) Then, the automatic visual inspection of step S6 is performed. Here, the plurality of storage substrates 27 after the heat treatment are subjected to external inspection to check the presence or absence of the heat treatment. At this time, when the position of the mounted component is detected and the position detection is performed using laser light or the like, the position of the mounted component can be recognized with high accuracy by recognizing the stepped portion on the wiring board 2. For example, by understanding the wiring board 2 of the plurality of storage substrates 2 7 formed in FIG. 1 (a), the through holes 2 h shown in FIG. 1 (b) or the surface wiring shown in FIG. 7 (b) 2 d, etc., the position of the mounted component can be recognized with high accuracy. Then, the wire bonding shown in step S7 is performed. Here, for example, as shown in FIG. 4 (e), a wire 2 4 such as a gold wire is used for wire bonding, and the pad of the surface electrode of the semiconductor chip 2 Γ and the pad corresponding to the pad are connected by the wire 2 4. The substrate-side terminals 2 i of the plurality of wiring substrates 2 accommodating the substrates 2 7 [see FIG. 5 (b)]. After that, the visual inspection shown in step S8 is performed. Here, the external appearance inspection of the plurality of storage substrates 27 after the wire bonding is performed, and the presence or absence of the wire bonding is checked. Then, the resin (sealing resin 2 3) shown in step S 9 is applied. Here, as shown in FIG. 4 (f), the sealing resin 2 3 is dropped onto the recessed portions 2 a of the wiring substrate 2 of the plurality of storage substrates 2 7 by the bonding method, and thus the sealing resin 2 is used. 3 to resin seal the semiconductor chip 21 and the wire 24. This standard is applicable to the Chinese National Standard (CNS) & Standard (21〇'χ 297 mm) '-23- (Please read the precautions on the back before filling this page) 550766 A7 B7 Employees ’Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Printed by the cooperative V. Description of the invention (21) 1 I At this time 5 Avoid the plurality of storage substrates 1 1 1 2 7 shown in FIG. 12 (a) Dividing grooves 2 7b Sealing resin 2 by bonding 3 Coating 1 1 V on the recess 2 of the wiring board 2 a 5 俾 Resin seals the majority of the storage substrates ^ -V Γ 2 1 ° Clearly read the resin coating range of I 4 Read 1 I It means the first 2 (b) 1 I on the back of FIG. 1 shows that on each piece of the block, that is, on each of the plurality of storage substrates 2 7 Note 1 1 I Each wiring substrate 2 is coated with a sealing resin 2 3 to make the sealing resin matters Further, 1 1 2 3 does not apply a resin for division formed on a plurality of storage substrates 2 7 and a substrate for dividing a gap for filling horses 2 3 〇 page, «W ✓ 1 1 The division groove portion 1 2 7 b of the substrate 2 7 is not provided with the sealing resin 2 3, and thus the sealing resin 2 3 is entered from the through hole 2 h shown in FIG. 1 (1 1 I b), etc. It flows into the substrate back 1 side 1 side, and as a result, adverse effects on the substrate division and the like can be prevented. Performing after 1 1 is indicated by the plug cap insertion in step S 10. 1 1 and 5 In the process of inserting the plug cap of the second embodiment, for the plug cap 4 shown in FIG. 1 and FIG. 13, the 9k I mark 4 2 UV of the recognition mark is continuously processed by — ^ Ultra Violet) Dry, according to the pattern of the logo 4 2 1 1 Appearance inspection of the logo and insertion of the plug cap, and when the plug cap is inserted 1 1 above, only the logo cap is judged as a good product by the logo appearance inspection 4 Perform 1 1 plug cap inserter 5 This can shorten the assembly time of the plug cap during the assembly process. At the same time, 5 can mix the plug cap 4 with other marks 4 2 to prevent it from happening. 1 1--I First 3 In the above process of inserting the plug cap, the mark of plug cap 4 is marked 1 1 The mark of 4 2 is marked 0 1 1 1 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ) -24-550766 A7 B7 V. Description of the invention (22) In addition, as shown in Figures 1 (a), (b), (c), the plug cap 4 is a box type made of, for example, a metal plate. Correspondingly, a hook support arm 17 (hook support portion) supporting a wiring substrate 2 which can be engaged with a plurality of storage substrates 2 7 is shown in the hook 19 of FIG. 1. In addition, as shown in Fig. 14, the identification mark 4 2 of the recognition mark is constituted by, for example, a manufacturing number or a mold number of the high-frequency module 1, and is formed by a character or a symbol. Here, the mark 4 2 is assigned to the surface 4 a of the plug cap 4. Then U V dries the mark 4 2. After drying, the appearance of the mark is checked by pattern recognition. Therefore, a plug cap 4 with a good mark 4 2 is selected. After that, the plug caps 4 which are good products are inserted into the wiring boards 2 of the plurality of storage boards 2 7 one by one. In addition, since the inspection of the mark 4 2 of the plug cap 4 with the mark 4 2 is performed, only the good quality of the plug cap 4 is installed on the wiring substrate 2, which can prevent the insertion of no mark, bad mark or other marks 4 2. Installation of bad connectors such as cap 4. As a result, the defective product plug cap with respect to the mark 4 2 will not be installed, so that the production line can be rationalized. The method of inserting (installing) the plug cap 4 will be described below. Here, the structure of the plug cap installation device 44 shown in FIG. 15 (a) and FIG. 16 used in the plug cap insertion process will be described. The plug cap installation device 4 4 is composed of: an X y table 4 5 supporting a plurality of storage substrates 2 7, and an installation unit 4 6 for plug cap installation. This paper is applicable in China. National Standard ( CNS) Α4 size (210 X 297 mm) (Please read the precautions on the back before filling this page)

，1T 經濟部智慧財產局員工消費合作杜印製 -25- 550766 A 7 B7 五、發明説明（23) (請先閲讀背面之注意事項再填寫本頁) 搭載於X y工作台4 5上之多數個收納基板2 7之認識咅5 位之複數鈎孔2 7 c〔參照第1 5 ( b )圖〕，及攝影鈎 孔2 7 c之認識攝影機4 7，及傾斜插接帽4加以配置之 對準站4 8所構成。 又，在裝設單元4 6設有··可吸附保持插接帽4之吸 附彈簧筒夾4 6 a，及將吸附彈簧筒夾4 6 a加以上下移 動之第一圓筒4 6 b與第一彈簧4 6 c，及引導吸附彈簧 筒夾4 6 a之上下移動之第一滑件4 6 d，及插接帽插入 時推壓插接帽4之推件4 6 i ，將推件4 6 i加以上下移 動之第二圓筒4 6 e與第二彈簧4 6 f ，及引導推件 4 6 i之上下移動之第二滑件4 6 g。 又，在對準站4 8設有將插接帽4傾斜成所定角度並 加以支撑的傾斜主工模4 8 a，及藉傾斜主工模4 8 a傾 斜插接帽4並加以支撑時，在其周圍引導插接帽4之傾斜 輔助工模4 8 b。 經濟部智慧財產局員工消費合作社印製 又，藉由吸附彈簧筒夾4 6 a從傾斜主工模4 8 a吸 附保持插接帽4時，與傾斜主工模4 8 a之插接帽4之傾 斜角度同樣之角度藉由吸附彈簧筒夾4 6 a可傾斜保持， 吸附彈簧筒夾4 6 a之吸附面4 6 j係與傾斜主工模 4 8 a-之支撑面之角度同樣之角度所形成。 在插入插接帽4時，首先，如第1 5 ( a )圖所示， 將多數個收納基板2 7配置在X y工作台4 5，之後，藉 認識攝影機4 7攝影表示於第1 5 ( b )圖之多數個收納 基板2 7之鈎孔2 7 c並檢出該孔之位置。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -26 - 550766 A7 _B7_ 五、發明説明（24) 另一方面，如第1 6圖所示，將判定爲良品之插接帽 4 ，藉由插接帽裝設裝置4 4之對準站4 8之傾斜主工模 4 8 a傾斜成所定角度並加以支撑，之後，維持插接帽4 傾斜之狀態下藉由裝設單元4 6之吸附彈簧筒夾4 6 a來 吸附保持插接帽4。 又，在該狀態，每一裝設單元4 6移動插接帽4成爲 插接帽4相對應之兩支鈎支撑臂1 7中，使藉由傾斜配置 於下側之其中一方之鈎支撑臂1 7配置於搭載X y工作台 4 5上之多數個收納基板2 7之所期望之鈎孔2 7 c上。 此時，對於多數個收納基板2 7之複數配線基板2， 將插接帽4之相對應之兩支鈎支撑臂1 7中藉傾斜配置於 下側之鈎支撑臂1 7，如第1 7 ( b )圖所示，插入在未 安裝有須插入之兩個钩孔2 7 c中之鄰接之插接帽4之一* 側的鈎孔2 7 c。 又，插接帽4之相對應之兩個鈎支撑臂1 7中，如第 17(a) ， （ b )圖所示，對應於未安裝有鄰接之插接 帽4之一側之鈎孔2 7 c，藉先插入與此對應之鈎支撑臂 1 7 (在此爲A側之鈎支撑臂1 7 )，可防止與經裝設之 插接帽4之干擾。 結果，可防止依上述干擾所發生之麻煩。 在此，如第1 7 ( a )圖所示，藉由插接帽裝設裝置 4 4之裝設單元4 6之A側的第一圓筒4 6 b下降吸著彈 簧筒夾4 6 a ，又藉由插接帽4之傾斜，將鈎支撑臂1 7 之鈎1 9傾斜地插入對應於該鈎之鈎孔2 7 c。 i紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ' — -27 - (請先閲讀背面之注意事項再填寫本頁) 衣·, 1T Consumption Cooperation by Employees of Intellectual Property Bureau, Ministry of Economic Affairs -25- 550766 A 7 B7 V. Description of Invention (23) (Please read the precautions on the back before filling this page) Installed on X 5 y workbench 4 5 The recognition of a plurality of storage substrates 2 7 咅 5 positions of plural hook holes 2 7 c [refer to FIG. 15 (b)], and the camera hooks 2 7 c of the camera 4 7 and the inclined plug cap 4 are arranged. The alignment station is composed of 4 8. In addition, the installation unit 4 6 is provided with a suction spring collet 4 6 a capable of sucking and holding the plug cap 4, and a first cylinder 4 6 b and a first cylinder for moving the suction spring collet 4 6 a up and down. A spring 4 6 c, and a first sliding member 4 6 d that guides the up and down movement of the suction spring collet 4 6 a, and pushes the pushing member 4 6 i of the plug cap 4 when the plug cap is inserted, and pushes the push member 4 6 i adds a second cylinder 4 6 e and a second spring 4 6 f that move up and down, and a second slider 4 6 g that guides the pusher 4 6 i to move up and down. In addition, the alignment station 48 is provided with a tilted main mold 4 8 a that tilts the plug cap 4 at a predetermined angle and supports it, and when the tilted main mold 4 8 a tilts the plug cap 4 and supports it, The tilt auxiliary tool 4 8 b of the plug cap 4 is guided around it. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and by holding the spring collet 4 6 a from the tilting main mold 4 8 a, the plugging cap 4 is held with the tilting main mold 4 8 a. The same angle of inclination can be tilted and held by the adsorption spring collet 4 6 a. The adsorption surface 4 6 j of the adsorption spring collet 4 6 a is the same angle as the angle of the supporting surface of the inclined main mold 4 8 a-. Formed. When inserting the plug cap 4, firstly, as shown in FIG. 15 (a), a plurality of storage substrates 2 7 are arranged on the X y table 4 5. Then, the camera 4 7 is photographed and displayed on the 1st 5 (b) The hook holes 2 7 c of the plurality of receiving substrates 27 in the figure and the positions of the holes are detected. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -26-550766 A7 _B7_ V. Description of the invention (24) On the other hand, as shown in Figure 16, the plug cap will be judged as a good product 4 ， The aligning station 4 8 of the aligning station 4 8 by the plug cap installation device 4 8 a tilts the main mold 4 8 a to a predetermined angle and supports it, and then maintains the inclined state of the plug cap 4 by installing the unit The suction spring collet 4 6 a of 4 6 is used to suck and hold the plug cap 4. In this state, each mounting unit 4 6 moves the plug cap 4 to become the two hook support arms 17 corresponding to the plug cap 4 so that one of the hook support arms is arranged at an oblique position on the lower side. 1 7 is arranged on the desired hook holes 2 7 c of the plurality of storage substrates 2 7 on which the X y table 45 is mounted. At this time, for the plurality of wiring substrates 2 of the plurality of storage substrates 2 7, the two hook support arms 17 corresponding to the plug cap 4 are inclinedly arranged on the lower side of the hook support arms 17, as in the first 7 (b) As shown in the figure, the hook hole 2 7 c on the side of one of the * plugs 4 adjacent to the plug cap 4 which is not installed with two hook holes to be inserted is inserted. In addition, as shown in Figs. 17 (a) and (b), the two hook support arms 17 corresponding to the plug cap 4 correspond to the hook holes on one side where the adjacent plug cap 4 is not installed. 2 7 c. By inserting the corresponding hook support arm 17 (here, the A-side hook support arm 17), interference with the installed plug cap 4 can be prevented. As a result, troubles caused by the interference can be prevented. Here, as shown in FIG. 17 (a), the first cylinder 4 6 b on the A side of the mounting unit 4 6 of the cap mounting device 4 4 is lowered to attract the spring collet 4 6 a. Then, by the inclination of the plug cap 4, the hook 19 of the hook support arm 17 is inserted obliquely into the hook hole 2c corresponding to the hook. i Paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) '— -27-(Please read the precautions on the back before filling this page)

、1T 經濟部智慧財產局員工消費合作社印製 550766 A7 B7 五、發明説明（25) 此時’在插接帽裝設裝置4 4之A側，藉傾斜地插入 插接帽4之鈎支撑臂1 7，可將鈎支撑臂1 7之鈎1 9插 入成未接觸於鈎孔2 7 c。 由此，插入鈎支撑臂1 7時，由於鈎1 9之鈎爪1 8 與鈎孔2 7 c未接觸，因此，可防止多數個收納基板2 7 之鈎孔2 7 c附近之損壞，結果，可謀求提高多數個收納 基板2 7之良品率及提高品質。 之後，如第18 (a)圖所示，對於插入在未安裝鄰 接之插接帽4之一側之鈎孔2 7 c之其中一方（A側）之 鈎支撑臂1 7，將配線基板2藉由寬度靠件4 6 k (將 X y工作台4 5從B側移動設定値至a側俾移動多數個收 納基板2 7之配線基板2 )，俾將載重賦與A側之鈎支撑 臂1 7。 此時，由於表示於第1 8 ( a )圖之插接帽4之表面 4 a之A側端部踫到吸附彈簧筒夾4 6 a之表示於第1 8 (b )圖之臂止動件4 6 h，因此藉配線基板2之寬度靠 件4 6 k之載重賦與A側之鈎支撑臂1 7，結果，朝從B 側（另一方）之鈎支撑臂1 7離開之方向在其彈性領域內 撓曲A側（其中一方）之鈎支撑臂1 7〔參照第1 8 ( c )圖〕。 又，藉將移動X y工作台4 5之寬度靠件4 6 k時之 上述設定値成爲鈎支撑臂1 7之彈性未失效之範圍，可成 爲在其彈性領域內撓曲。 藉撓曲A側之鈎支撑臂1 7，擴展插接帽4之兩個鈎 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公餐） (請先閱讀背面之注意事項再填寫本頁) •^^衣· 訂 經濟部智慧財產局員工消費合作社印製 -28- 550766 A7 _____B7 五、發明説明（26) (請先閲讀背面之注意事項再填寫本頁) 支撑臂1 7間之距離，結果，A側之鈎支撑臂1 7之鈎 1 9之鈎爪1 8 (參照第1圖）卡合於配線基板2之鈎住 部1 6 ’同時如第1 8 (b)圖所示，B側（另一方）之 韵支撑臂1 7之鈎1 9配置在多數個收納基板2 7之其他 鈎孔2 7 c上。 在該狀態，如第1 9 ( a )圖所示，藉b側之第二圓 筒46e及第二彈簧46f降下推具46i ，俾推壓插接 帽4之表面4 a之B側端部，由此，在與插入a側之鈎支 撑臂1 7之表示於第1 7 ( a )圖之鈎孔2 7 c相對應所 配置之其他鈎孔2 7 c插入B側（另一方）之鈎支撑臂 17。 此時，由於藉多數個收納基板2 7之表示於第1 8圖 之寬度靠件4 6 k，另一鈎孔2 7 c配置於靠近A側之鈎 支撑臂1 7，因此，插入B側之鈎支撑臂1 7時，與A側 之情形同樣地，鈎1 9之鈎爪1 8與鈎孔2 7 c未接觸， 可防止多數個收納基板2 7之其他鈎孔2 7 c附近之損壞 〇 經濟部智慧財產局員工消費合作社印製 結果，可謀求提高多數個收納基板2 7之良品率與提 高品質。 然後，開放依多數個收納基板2 7之配線基板2之寬 度靠件4 6 k之對於A側鈎支撑臂1 7之載重賦與，由此 ’將A側鈎支撑臂1 7之鈎1 9及B側鈎支撑臂1 7之鈎 1 9分別卡合於配線基板2兩側之鈎住部1 6。 結果，如第1 9 ( b )圖所示，可完成插接帽4對於 本紙張尺度適用中國國家標準（CNS ) Μ規格（210χ297公釐） -29- 550766 A7 ___ B7_ 五、發明説明（27) 多數個收納基板2 7之配線基板2之裝設（安裝），因此 ，可容易地進行插接帽4自動裝設至多數個收納基板2 7 〇 (請先閱讀背面之注意事項再填寫本頁) 由此，如第4 ( g )圖所示，藉由插接帽4可覆蓋搭 載有晶片零件2 2與半導體小片2 1之配線基板2。 依照本實施形態二之插接帽4之裝設方法，可避免插 接帽4之脫落，或插接帽4之搖幌的缺點。 又，由於在使用多數個收納基板2 7之一貫裝配生產 上進行依插接帽4之封閉，因此可提高量產效率。 又，與依插接帽銲接之封閉方法等相比較之情形，可 顯著減低工數，又也可省略對於助溶劑等污垢之洗淨過程 〇 之後，如第2 0圖所示，將第一滑件4 6 d及第二滑 件4 6 g作爲導件俾上昇吸附彈簧筒夾4 6 a與推具 4 6 i而回到原來位置，又將裝設單元4 6移動至對準站 4 8上即完成插接帽插入過程。 經濟部智慧財產局員工消費合作社印製 然後，進行表示於第3圖之步驟S 1 1之基板分割， 將多數個收納基板2 7分割成個片基板之各各配線基板2 ，由此成爲如第4 ( h )圖所示之各各高頻模組1之形態 〇 然後，進行表示於步驟1 2之特性選別，能取得各該 高頻1之電氣特性，同時藉其結果未選別高頻模組1。 又在高頻模組1係藉由陶瓷基板亦即配線基板2之配 線圖案導體電阻，配線圖案間電容之批量偏差及半導體小 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -30- 550766 A7 B7 五、發明説明（28) 片2 1之特性偏差使模組特性變動。因此，在特性選別之 過程，監測高頻模組1之配線基板2的電氣特性。 (請先閲讀背面之注意事項再填寫本頁) 在裝配高頻模組1，事先品位分類半導體小片2 1之 特性，選擇使用之配線基板2與半導體小片2 1之組合上 最適合之晶片電容器或晶片電阻等之晶片零件2 2之常數 ，俾進行裝配。 亦即，準備經特性選別之配線基板2及半導體小片 2 1，藉將半導體小片2 1與晶片零件2 2實裝於該經選 別之配線基板2，可將高頻模組1之特性放進容許範圍， 結果，可裝配特性之高品質且安定之高頻模組1。 在此，第2 1圖係表示高頻模組1之配線基板2之特 性的頻率與輸出（P 〇 u t )之關係的一例。 例如，在第2 1圖中，將輸出Q ( W )作爲高·頻模組 1之輸出合否之臨界値，高頻模組1之第一樣品5 0時， 則使用頻帶4 9成爲充分地輸出合格，作爲高頻模組1成 爲良品。 經濟部智慧財產局員工消費合作社印製 但是，第二樣品5 1時，在使用頻帶4 9中，只有約 一半領域（使用頻帶4 9之低頻側領域）成爲輸出合格 5 2，而剩下之約一半領域（使用頻帶4 9之高頻側領域 )成爲輸出不合格5 3，結果成爲不良品之高頻模組1。 又第2 2圖係表示半導體小片2 1之品級分類之一例 子；在此’表示以事先過程晶圓檢查之資料爲基礎，藉由 自動分類工模裝塞機，對於每一半導體小片進行品級分類 者0 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -31 - 550766 A7 B7 五、發明説明（29) 又，第22圖中，Ciss係表示電容，Idss係 表示洩漏電流，V t h係表示臨界電壓，例如第2 2圖中 組合品級N〇· 3、4、8之三個半導體小片2 1後使用 ，可設定最適合之電路常數。 然後，進行表示於第3圖之步驟1 3之用帶縛住。 亦即，用帶縛住經選別之複數高頻模組1，並捲繞在 表示於第4 ( i )圖之捲軸4 3並加以收納。 依照本實施形態2之半導體裝置（高頻模組1 )之製 造方法，可將以往以1 2個過程裝配者減少至9個過程， 結果，可實現製造生產線之合理化。 又，可謀求使用多數個收納基板2 7之高頻模組1之 裝配的提高生產量或減低基板材料費，結果，可實現將生 產性提高至以往裝配方法之約之三倍，又可減低約 5 0 % 之價格。 以上，依據發明之實施形態一、二具體地說明藉由本 ’發明人所實行之發明，惟本發明並不被限定於上述發明之 實施形態一、二者，當然在不超越其要旨之範圍內可做各 種變更。 例如在實施形態二之特性選別過程中，說明監測配線 基板2之電氣特性，事先品級分類半導體小片2 1之特性 ，以最適合之組合來裝配使用之配線基板2與半導體小片 2 1之情形，惟即使選別配線基板2與半導體小片2 1並 加以組合也無法得到高頻模組1之特性時，則更換晶片零 件2 2等能得到高頻模組1之特性也可以。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 衣· 訂 經濟部智慧財產局員工消費合作社印製 550766 A7 B7 五、發明説明（3〇) (請先閲讀背面之注意事項再填寫本頁) 又在上述實施形態所說明之半導體小片2 1係由矽之 半導體晶圓所得到者也可以，或由鎵、砷之半導體晶圓所 得到者也可以，或是使用S〇I、GeSi、TFT( Thin Film Transistor)等也可以。 〔產業上之利用可能性〕 如上所述，本發明之半導體裝置之製造方法，係適用 於實裝晶片電容器或晶片電阻等之晶片零件，及依裸晶片 實裝之半導體小片，且使用多數個收納基板加以裝配之所 有模組製品之製造方法，同時，適用於組裝於行動電話等 之小型攜帶用電子機器，特別是適用於搭載薄型之攜帶用 電子機器之高頻模組（高頻電力放大裝置）。 (圖式之簡單說明） 第1圖係表示藉由本發明之半導體裝置之製造方法所 裝配的高頻模組之構造之實施形態之一例的圖式；（a ) 係表不斜視圖；而（b )係表75剖面圖。 經濟部智慧財產局員工消費合作社印製 第2圖係表示圖示於高頻模組之構造的底面圖。 第3圖係表示圖示於高頻模組之製造方法之裝配順序 之一例子的製造處理流程圖。 第 4(a) ，（b) ，（c) ，( d ) ，（e)，（ f) ’ （g) ， （h) ， （i)圖係表示圖示於第8圖之 主要製程之配線基板及高頻模組之構造之一例子的剖面圖 ，側面圖及斜視圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -33 - 550766 經濟部智慧財產局員工消費合作社印製 A7 B7_五、發明説明（31) 第5圖係表示使用於製造圖示在第1圖之高頻模組時 之基板與其不良標誌配線基板之構造之一例子的圖式；（ a )係表示多數個收納基板之斜視圖；（b )係表示零件 搭載檢查時之不良標誌基板的平面圖；（c )係表示溶融 熱處理後之不良標誌配線基板的平面圖；（d )係表示連 線接合後之不良標誌配線基板的平面圖。 第6圖係表示本發明之半導體裝置之製造方法之銲劑 接合過程之噴嘴移動軌跡之實施形態之一例子的圖式；（ a )係表示配線基板之移動軌跡的平面圖；（b )係表示 多數個收納基板之移動軌跡的斜視圖。 第7圖係表示本發明之半導體裝置之製造方法之銲劑 印刷過程與鲜劑接合過程之基板構造之實施形態之一^例的 圖式；（a )係表不銲劑形成前之多數個收納基板‘的平面 圖；（b )係表示銲劑形成前之配線基板的平面圖；（c )係表示銲劑印刷與銲劑接合後之配線基板的平面圖。 第8圖係表示在本發明之半導體裝置之製造方法的零 件搭載過程所使用之零件搭載裝置之構造之實施形態之一 例子的圖式；（a )係表示外觀斜視圖；（b )係表示構 成方塊圖。 第9圖係表示本發明之半導體裝置之製造方法的小片 搭載過程所使用之小片搭載裝置之構造之實施形態之一例 的圖式；（a )係表示外觀斜視圖；（b )係構成方塊圖 〇 第10圖係表示本發明之半導體裝置之製造方法的零 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) •^^衣· 訂 __ -34 - 550766 A7 B7 五、發明説明（32) (請先閱讀背面之注意事項再填寫本頁) 件搭載與小片搭載過程之配線基板之構造之實施形態之一 例子的圖式；（a )係表示零件搭載後的基板平面圖；（ b )係表示小片搭載後的基板平面圖。 第11圖係表示本發明之半導體裝置之製造方法的自 動外觀檢查過程之零件位置檢出時之基板構造之實施形態 之一例子的圖式（a )係表示多數個收納基板之平面圖； (b )係表示配線基板之平面圖。 第12圖係表示本發明之半導體裝置之製造方法的樹 脂塗布過程之基板構造之實施形態之一例子的圖式；（a )係多數個收納基板之平面圖；（b )係表示配線基板之 平面圖。 第13圖係表示本發明之半導體裝置之製造方法的插 接帽插入過程所使用之插接帽之構造之實施形態之一例的 圖式；（a )係表示平面圖；（b )被動元件用晶片係表 示側面圖。 第1 4圖係表示標誌賦與圖示於第1 3圖之插接帽之 狀態之實施形態之一例子的斜視圖。 經濟部智慧財產局員工消費合作社印製 第15圖係表示本發明之半導體裝置之製造方法之插 接帽插入過程的多數個收納基板之鈎孔之認識方法之一例 子的圖式；（a )係表示認識狀態的正面圖；（b )係表 示多數個收納基板之鈎孔的平面圖。 第16圖係表示本發明之半導體裝置之製造方法之插 接帽插入過程之插接帽移載方法之實施形態之一例子的移 載原理圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X：297公釐） -35- 550766 Μ Β7 五、發明説明（33) (請先閱讀背面之注意事項再填寫本頁) 第17圖係表示本發明之半導體裝置之製造方法的插 接帽插入過程之插接帽插入方法之實施形態之一例子的圖 式；（a )係表示插入原理圖；（b )係表示（a )之插 接帽插入狀態圖。 第18圖係表示本發明之半導體裝置之製造方法的插 接帽插入過程之插接帽裝設方法之實施形態之一例子的圖 式；（a )係表示裝設原理圖；（b )係表示（a )之插 接帽放大剖面圖；（c )係表示（b )之c部之放大部分 剖面圖。 第19圖係表示本發明之半導體裝置之製造方法的插 接帽插入過程之插接帽插入後之狀態之一'例子的圖式；（ a )係表示正面圖；（b )係表示配線基板之放大部分剖 面圖。 第2 0圖係表示本發明之半導體裝置之製造方法的插 接帽插入過程之插接帽插入後之插接帽裝設裝置之動作之 一例子的動作原理圖。 經濟部智慧財產局員工消費合作社印製 第21圖係表示本發明之半導體裝置之製造方法的特 性選別過程之特性檢查結果之一例子的輸出特性圖。 第2 2圖係表示本發明之半導體裝置之製造方法的小 片特性檢查結果之一例子之小片品級分類的圖式。 (記號之說明） 1 高頻模組 2 配線基板 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -36- 550766 A7 B7 五、發明説明（34) 4 5 7 經濟部智慧財產局員工消費合作社印製 2 2 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 4 2 4 4 4 5 4 6 4 7 4 8 插接帽 外部端子 凹部 鈎住部 鈎支撑臂 鈎爪 鈎 半導體小片 晶片零件 多數個收納基板 噴嘴 移動軌跡 零件搭載裝置 第一零件供應部 第二零件供應部 搭載頭部 X y台面 基板運送部 標誌 插接帽裝設裝置 X y工作台 裝設單元 認識攝影機 對準站 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -37 -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 550766 A7 B7 V. Description of the invention (25) At this time, 'On the A side of the plug cap installation device 4 4, insert the hook support arm 1 of the plug cap 4 at an angle 7. The hook 19 of the hook support arm 17 can be inserted so as not to contact the hook hole 2 7 c. Therefore, when the hook support arm 17 is inserted, since the hook claws 18 of the hooks 19 and the hook holes 2 7 c are not in contact, damage to the vicinity of the hook holes 2 7 c of the plurality of storage substrates 2 7 can be prevented. It is possible to improve the yield and quality of the plurality of storage substrates 27. Thereafter, as shown in FIG. 18 (a), the wiring board 2 is connected to the hook support arm 17 inserted into one of the hook holes 2 7c on one side of the unattached plug cap 4 (A side). With the width support member 4 6 k (moving the X y table 4 5 from the B side to the a side, and moving the wiring board 2 of the plurality of storage boards 2 7), the load is given to the hook support arm on the A side 1 7. At this time, since the A-side end of the surface 4 a of the plug cap 4 shown in FIG. 18 (a) is pushed to the suction spring collet 4 6 a, the arm is shown in FIG. 18 (b). 4 h, so the width of the wiring board 2 is given to the hook support arm 17 on the A side by the load of the component 4 6 k. As a result, the hook support arm 17 on the B side (the other side) moves away from In the elastic area, the hook support arm 17 (refer to FIG. 18 (c)) is flexed on the A side (one of the sides). In addition, by setting the above-mentioned setting when moving the width rest member 4 6 k of the X y table 45 to the range in which the elasticity of the hook support arm 17 is not invalidated, it can be flexed in its elasticity range. By flexing the hook support arm 17 on the A side and extending the two hooks of the plug cap 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 meals) (Please read the precautions on the back before filling this page ) • ^^ Clothes · Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -28- 550766 A7 _____B7 V. Description of the invention (26) (Please read the precautions on the back before filling this page) The distance between the support arms 17 As a result, the hook support arm 17 on the A side, the hook 19 on the hook 19, and the hook 1 8 (refer to FIG. 1) are engaged with the hooking portion 16 on the wiring board 2 as shown in FIG. 18 (b). The hooks 19 of the rhyme supporting arms 17 on the B side (the other side) are arranged on the other hook holes 2 7 c of the plurality of storage substrates 27. In this state, as shown in FIG. 19 (a), the pusher 46i is lowered by the second cylinder 46e and the second spring 46f on the b side, and the end portion B on the surface 4a of the plug cap 4 is pushed. Therefore, other hook holes 2 7 c arranged corresponding to the hook holes 2 7 c shown in FIG. 17 (a) of the hook support arm 17 inserted on the a side are inserted into the B side (the other side). Hoop support arm 17. At this time, since a plurality of width-receiving pieces 4 6 k shown in FIG. 18 are borrowed from a plurality of storage substrates 2 7, and another hook hole 2 7 c is disposed on the hook support arm 17 near the A side, therefore, it is inserted into the B side. When the hook support arm 17 is the same as the case of the A side, the hook claw 18 of the hook 19 is not in contact with the hook hole 2 7 c, which can prevent a large number of other hook holes 2 7 c near the storage substrate 2 7. Damage 〇 The printed results of employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs can improve the yield and quality of most storage substrates 27. Then, the load on the A-side hook support arm 17 according to the width of the wiring board 2 of the plurality of storage substrates 2 7 is released, thereby 'hook the A-side hook support arm 17 7 9 And the hooks 19 of the B-side hook supporting arms 17 are respectively engaged with the hooking portions 16 on both sides of the wiring board 2. As a result, as shown in Fig. 19 (b), the pluggable cap 4 can be applied to the Chinese standard (CNS) M specification (210x297 mm) for this paper size. -29- 550766 A7 ___ B7_ V. Description of the invention (27 ) The mounting (installation) of the wiring board 2 of the plurality of storage substrates 2 7 can be easily installed automatically to the plurality of storage substrates 2 7 〇 (Please read the precautions on the back before filling in this Page) As a result, as shown in FIG. 4 (g), the wiring board 2 on which the chip parts 22 and the semiconductor chips 21 are mounted can be covered by the plug cap 4. According to the installation method of the plug cap 4 according to the second embodiment, it is possible to avoid the shortcomings of the plug cap 4 from falling off or the wobble of the plug cap 4. In addition, since the plug-in cap 4 is closed in a one-piece assembly production using a plurality of storage substrates 27, mass production efficiency can be improved. In addition, compared with the method of sealing by plug-in cap welding, the number of work can be significantly reduced, and the cleaning process for dirt such as co-solvents can be omitted. After the first, as shown in FIG. 20, the first The slide 4 6 d and the second slide 4 6 g are used as guides. The suction spring collet 4 6 a and the pusher 4 6 i are returned to their original positions, and the installation unit 4 6 is moved to the alignment station 4. The plug cap insertion process is completed on 8. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, the substrate division shown in step S 1 1 in FIG. 3 is performed, and the plurality of storage substrates 27 are divided into individual wiring substrates 2 of a single substrate, thereby becoming as follows. The form of each high-frequency module 1 shown in FIG. 4 (h). Then, the characteristic selection shown in step 12 is performed, and the electrical characteristics of each high-frequency 1 can be obtained. At the same time, the high-frequency module 1 is not selected based on the results. In the high-frequency module 1, the ceramic substrate, that is, the wiring pattern conductor resistance of the wiring substrate 2, the bulk deviation of the capacitance between the wiring patterns, and the semiconductor paper size are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -30 -550766 A7 B7 V. Description of the invention (28) The characteristic deviation of the chip 2 1 changes the module characteristics. Therefore, during the characteristic selection process, the electrical characteristics of the wiring board 2 of the high-frequency module 1 are monitored. (Please read the precautions on the back before filling this page.) When assembling the high-frequency module 1, classify the characteristics of the semiconductor chip 21 in advance, and choose the most suitable chip capacitor or chip for the combination of the wiring substrate 2 and the semiconductor chip 21. The constants of the chip parts 22 such as resistors are assembled. That is, the wiring board 2 and the semiconductor chip 21 are selected according to the characteristics. By mounting the semiconductor chip 21 and the wafer component 22 on the selected wiring substrate 2, the characteristics of the high-frequency module 1 can be put into the allowable range. As a result, a high-quality and stable high-frequency module 1 with characteristics can be assembled. Here, Fig. 21 is an example showing the relationship between the characteristic frequency and the output (Pout) of the wiring board 2 of the high-frequency module 1. For example, in Fig. 21, the output Q (W) is regarded as the critical value of the output of the high-frequency module 1. When the first sample 50 of the high-frequency module 1 is 50, the frequency band 4 9 is used to obtain a sufficient output. Passed, and became a good product as the high-frequency module 1. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, in the second sample of 51, only about half of the bands used in the band 4 9 (the low-frequency side bands in the band 4 9) became output qualified 5 2 and the rest were Approximately half of the areas (high-frequency side areas using frequency bands 4 to 9) became output failures 5 3, and as a result the defective high-frequency module 1. Figure 22 shows an example of the grade classification of semiconductor die 21. Here, 'represents that each semiconductor die is automatically sorted by a die plugging machine based on the information of the wafer inspection process in advance. Grade classifier 0 This paper size is in accordance with China National Standard (CNS) A4 (210X 297 mm) -31-550766 A7 B7 V. Description of the invention (29) Also, in Figure 22, Ciss means capacitors, Idss means Represents the leakage current, and V th is the threshold voltage. For example, in Figure 22, the three semiconductor chips No. 3, 4, and 8 are combined and used after use. The most suitable circuit constant can be set. Then, bind with a band shown in steps 13 of FIG. 3. That is, the selected plurality of high-frequency modules 1 are tied with a band, and wound around a reel 43 shown in Fig. 4 (i) and stored. According to the manufacturing method of the semiconductor device (high-frequency module 1) according to the second embodiment, it is possible to reduce the number of assemblers from 12 to 9 processes in the past, and as a result, the manufacturing line can be rationalized. In addition, it is possible to increase the throughput of the assembly of the high-frequency module 1 using a plurality of storage substrates 2 7 or to reduce the substrate material cost. As a result, the productivity can be increased to about three times that of the conventional assembly method, and it can be reduced by about 5 times. 0% price. In the above, the inventions implemented by the present inventor have been specifically described based on the first and second embodiments of the invention, but the invention is not limited to the first or two embodiments of the invention described above, and of course, it is within the scope of not exceeding the gist Various changes can be made. For example, in the characteristic selection process of the second embodiment, the electrical characteristics of the wiring board 2 are monitored, the characteristics of the semiconductor chip 21 are classified in advance, and the wiring board 2 and the semiconductor chip 21 are assembled and used in the most suitable combination. However, if the characteristics of the high-frequency module 1 cannot be obtained even if the wiring substrate 2 and the semiconductor chip 21 are selected and combined, the characteristics of the high-frequency module 1 can be obtained by replacing the chip parts 2 2 and the like. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page). · Ordering printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative 550766 A7 B7 V. Description of the invention (30) (Please read the precautions on the back before filling in this page) The semiconductor chip 21 described in the above embodiment may be obtained from a semiconductor wafer of silicon, or a semiconductor crystal of gallium or arsenic. It is also possible to obtain a circle, or it is also possible to use S0I, GeSi, TFT (Thin Film Transistor), or the like. [Industrial Applicability] As described above, the method for manufacturing a semiconductor device of the present invention is suitable for mounting chip components such as chip capacitors or chip resistors, and semiconductor chips mounted on bare chips, and uses a large number of A manufacturing method for all module products assembled by accommodating substrates. It is also suitable for small portable electronic devices assembled in mobile phones, especially high-frequency modules (high-frequency power amplifiers) equipped with thin portable electronic devices. . (Brief description of the drawings) FIG. 1 is a diagram showing an example of an embodiment of the structure of a high-frequency module assembled by the method for manufacturing a semiconductor device of the present invention; (a) is a perspective view of a table; and (b) Table 75 is a sectional view. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 2 is a bottom view showing the structure of the high-frequency module. Fig. 3 is a manufacturing process flowchart showing an example of an assembling procedure of a manufacturing method of a high-frequency module. Figures 4 (a), (b), (c), (d), (e), (f) '(g), (h), (i) are the main processes shown in Figure 8 A cross-sectional view, a side view, and a perspective view of an example of a structure of a wiring substrate and a high-frequency module. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) -33-550766 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_5. Description of the invention (31) Figure 5 shows that it is used in manufacturing A diagram showing an example of the structure of the substrate and its defective mark wiring substrate in the high-frequency module of FIG. 1; (a) is a perspective view showing a plurality of storage substrates; and (b) is a failure when the parts are mounted and inspected. (C) is a plan view showing a defective mark wiring board after a melt heat treatment; (d) is a plan view showing a defective mark wiring board after wire bonding. FIG. 6 is a diagram showing an example of an embodiment of the nozzle movement trajectory of the solder bonding process of the semiconductor device manufacturing method of the present invention; (a) is a plan view showing the movement trajectory of the wiring board; (b) is a plan view showing a majority An oblique view of the movement track of each storage substrate. FIG. 7 is a diagram showing one example of the embodiment of the substrate structure of the solder printing process and the solder joining process of the manufacturing method of the semiconductor device of the present invention; (a) shows a plurality of storage substrates before the formation of the solder (B) is a plan view showing the wiring substrate before the formation of the flux; (c) is a plan view showing the wiring substrate after the printing of the flux and the bonding of the flux. FIG. 8 is a diagram showing an example of an embodiment of a structure of a component mounting device used in a component mounting process of a method for manufacturing a semiconductor device according to the present invention; (a) is an external perspective view; (b) is a perspective view Make up a block diagram. FIG. 9 is a diagram showing an example of an embodiment of a structure of a chip mounting device used in a chip mounting process of a method for manufacturing a semiconductor device according to the present invention; (a) is a perspective view showing the appearance; (b) is a block diagram 〇 Figure 10 shows the zero paper size of the manufacturing method of the semiconductor device of the present invention, which is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling in this page). ^^ Clothes · Order __ -34-550766 A7 B7 V. Description of the Invention (32) (Please read the precautions on the back before filling this page) One example of the implementation form of the structure of the wiring board during the process of mounting and small pieces (A) is a plan view of the substrate after the component is mounted; (b) is a plan view of the substrate after the chip is mounted. FIG. 11 is a diagram (a) showing an example of an embodiment of a substrate structure when a component position is detected in an automatic visual inspection process of a method of manufacturing a semiconductor device according to the present invention; (b) is a plan view showing a plurality of storage substrates; ) Is a plan view showing a wiring substrate. FIG. 12 is a diagram showing an example of an embodiment of a substrate structure in a resin coating process of a method for manufacturing a semiconductor device according to the present invention; (a) is a plan view of a plurality of storage substrates; (b) is a plan view of a wiring substrate . FIG. 13 is a diagram showing an example of an embodiment of a structure of a plug cap used in a plug cap insertion process of a method for manufacturing a semiconductor device of the present invention; (a) is a plan view; (b) a wafer for a passive device Department shows a side view. Fig. 14 is a perspective view showing an example of the embodiment of the state where the logo is assigned to the plug cap shown in Fig. 13; Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. FIG. 15 is a diagram showing an example of a method for recognizing hook holes of a plurality of receiving substrates in a process of inserting a plug cap of a semiconductor device manufacturing method of the present invention; It is a front view showing a recognition state; (b) is a plan view showing hook holes of a plurality of storage substrates. Fig. 16 is a schematic diagram of an example of a transfer method of an embodiment of a method for transferring a plug cap in a plug cap insertion process of a method for manufacturing a semiconductor device according to the present invention. This paper size applies Chinese National Standard (CNS) A4 specification (21〇X: 297 mm) -35- 550766 Μ B7 V. Description of invention (33) (Please read the precautions on the back before filling this page) Figure 17 It is a diagram showing an example of an embodiment of a method for inserting a plug cap in the process of inserting a plug cap in the method of manufacturing a semiconductor device of the present invention; (a) is a schematic diagram of insertion; (b) is a diagram of (a) The state diagram of the plug cap. FIG. 18 is a diagram showing an example of an embodiment of a method for installing a plug cap in a plug cap insertion process of a method for manufacturing a semiconductor device according to the present invention; (a) is a schematic diagram showing an installation principle; (b) is An enlarged sectional view of the plug cap showing (a); (c) is an enlarged partial sectional view showing part c of (b). FIG. 19 is a diagram showing an example of an example of a state after the plug cap is inserted in the plug cap insertion process of the method for manufacturing a semiconductor device of the present invention; (a) is a front view; (b) is a wiring substrate Zoomed in section view. Fig. 20 is an operation principle diagram showing an example of the operation of the plug cap mounting device after the plug cap is inserted in the plug cap insertion process of the semiconductor device manufacturing method of the present invention. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Fig. 21 is an output characteristic diagram showing an example of a characteristic inspection result of a characteristic selection process of a method for manufacturing a semiconductor device according to the present invention. Fig. 22 is a diagram showing chip grade classification as an example of a chip characteristic inspection result of the method for manufacturing a semiconductor device of the present invention. (Explanation of symbols) 1 High-frequency module 2 Wiring board This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) -36- 550766 A7 B7 V. Description of invention (34) 4 5 7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by employee consumer cooperative 2 2 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 4 2 4 4 4 5 4 6 4 7 4 8 Plug cap external terminal recessed hook hook support arm hook Claw hook semiconductor chip wafer parts Most storage substrate Nozzle movement trajectory component mounting device First component supply section Second component supply section mounted head X y Mesa substrate conveying section mark plug cap mounting device X y table mounting Unit recognition camera alignment station (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) -37-

Claims (1)

550766 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 q 1 · 一種半導體裝置之製造方法，係屬於具有： 在配線基板的主面搭載被動元件用晶片及主動元件用 晶片之過程；及 以能夠覆蓋上述被動元件用晶片及主動元件用晶片之 方式來將插接帽安裝於上述配線基板之過程；及 在上述插接帽形成認識標誌之過程之半導體裝置的製 造方法，其特徵爲： 上述認識標誌是在上述配線基板安裝上述插接帽的過 程之前，形成於上述插接帽的表面； 將形成有上述認識標誌的上述插接帽安裝於上述配線 基板。 2 .如申請專利範圍第1項所述之半導體裝置之製造 方法，其中更具有檢查上述認識標誌之過程； 只將合格於上述認識標誌的檢查之上述插接帽安裝於 上述配線基板。 3·—種半導體裝置之製造方法，係屬於具有： 準備一具有複數個封裝形成領域的配線基板之過程； 及 在上述配線基板的複數個封裝形成領域的各個主面搭 載被動元件用晶片及主動元件用晶片之過程；及 以能夠覆蓋上述被動元件用晶片及主動元件用晶片之 方式，在上述配線基板的複數個封裝形成領域中安裝複數 個插接帽之過程；及 分別在上述複數個插接帽形成認識標誌之過程之半導 (請先閲讀背面之注意事項再填寫本頁) 、1T 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） -38- 經濟部智慧財產局員工消費合作社印製 550766 A8 B8 C8 ____ D8 六、申請專利範圍 2 體裝置的製造方法，其特徵爲： 上述認識標誌是在上述配線基板安裝上述複數個插接 帽的過程之前，分別形成於上述插接帽的表面； 將形成有上述認識標誌的上述複數個插接帽安裝於上 述配線基板的複數個封裝形成領域。 4 .如申請專利範圍第3項所述之半導體裝置之製造 方法’其中搭載上述被動元件用晶片及上述主動元件用晶 片之過程’及在上述複數個插接帽形成上述認識標誌之過 程，以及安裝上述複數個插接帽之過程，是藉由一貫的製 造裝置來進行。 5 ·如申請專利範圍第3項所述之半導體裝置之製造 方法，其中更具有檢查形成於上述複數個插接帽的認識標 誌之過程； 只將合格於上述認識標誌的檢查之上述插接帽安裝於 上述配線基板。 6 · —種半導體裝置之製造方法，係屬於具有： 準備一具有複數個封裝形成領域的配線基板之過程； 及 在上述配線基板的複數個封裝形成領域的各個主面， 藉由焊劑溶融熱處理來搭載被動元件用晶片及主動元件用 晶片之過程；及 以能夠覆蓋上述被動元件用晶片及主動元件用晶片之 方式，在上述配線基板的複數個封裝形成領域中安裝複數 個插接帽之過程；及 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ (請先閲讀背面之注意事項再填寫本頁)550766 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Patent application scope q 1 · A method for manufacturing a semiconductor device, which includes: mounting a passive element wafer and an active element wafer on the main surface of a wiring substrate A process of mounting a plug cap on the wiring substrate in such a manner as to cover the passive component wafer and the active component wafer; and a method of manufacturing a semiconductor device in the process of forming an identification mark on the plug cap, It is characterized in that: the recognition mark is formed on the surface of the plug cap before the wiring board is mounted with the plug cap; and the plug cap with the recognition mark is mounted on the wiring board. 2. The method of manufacturing a semiconductor device according to item 1 of the scope of patent application, which further includes a process of checking the above-mentioned recognition mark; only the above-mentioned plug caps that pass the inspection of the above-mentioned recognition mark are mounted on the above wiring substrate. 3. A method for manufacturing a semiconductor device, which belongs to the process of: preparing a wiring substrate having a plurality of package formation fields; and mounting a passive element wafer and an active device on each main surface of the plurality of package formation fields of the wiring substrate. A process for mounting a chip for a component; and a process for mounting a plurality of plug caps in a plurality of package forming fields of the wiring substrate in a manner capable of covering the passive component wafer and the active component wafer; The semi-conductor of the process of forming the recognition mark by the cap (please read the precautions on the back before filling this page), 1T This paper size applies the Chinese National Standard (CNS) Α4 specification (210 X 297 mm) -38- Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau 550766 A8 B8 C8 ____ D8 VI. Method of manufacturing a patent application 2 body device, characterized by: The above recognition marks are formed before the wiring board is installed with the plurality of plug caps, respectively. On the surface of the above-mentioned plug cap; and the above-mentioned multiple plugs on which the recognition mark is formed The cap is mounted on a plurality of package formation areas of the wiring board. 4. The method for manufacturing a semiconductor device according to item 3 of the scope of the patent application, wherein the process of mounting the above-mentioned passive element wafer and the above-mentioned active element wafer and the process of forming the above-mentioned recognition mark on the plurality of plug caps, and The process of installing the plurality of plug caps is performed by a conventional manufacturing apparatus. 5. The method for manufacturing a semiconductor device as described in item 3 of the scope of patent application, which further includes a process of inspecting the recognition marks formed on the plurality of plug caps; only the plug caps that pass the inspection of the recognition marks Mounted on the wiring board. 6-A method for manufacturing a semiconductor device, which belongs to the process of: preparing a wiring substrate having a plurality of package formation areas; and each main surface of the plurality of package formation areas of the wiring substrate described above, by means of a solder melt heat treatment. A process of mounting a passive element wafer and an active element wafer; and a process of installing a plurality of plug caps in a plurality of package formation fields of the wiring substrate in a manner capable of covering the passive element wafer and the active element wafer; And this paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) _ (Please read the precautions on the back before filling this page) -39- 550766 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 3 沿著上述複數個封裝形成領域來分割上述配線基板， 藉此來形成複數個封裝體之過程之半導體裝置的製造方法 ，其特徵爲： 準備上述配線基板之過程具有：分別檢查上述複數個 封裝形成領域，在不良的領域中形成不良標誌之過程； 在形成有上述不良標誌的上述封裝形成領域中不搭載 上述被動元件用晶片，上述主動元件用晶片，及上述插接 帽。 7·—種半導體裝置之製造方法，係屬於具有： 準備一具有複數個封裝形成領域的配線基板之過程； 及 在上述配線基板的複數個封裝形成領域的各個主面， 搭載被動元件用晶片及主動元件用晶片之過程；及 以能夠覆蓋上述被動元件用晶片及主動元件用晶片之 方式，在上述配線基板的複數個封裝形成領域中安裝複數 個插接帽之過程；及 沿著上述複數個封裝形成領域來分割上述配線基板， 藉此來形成複數個封裝體之過程之半導體裝置的製造方法 ，其特徵爲具有： 在上述各個過程中進行檢查，藉此來認識過程不良品 ，且附上不良標誌之過程； 在附有上述不良標誌的上述複數個封裝形成領域中不 進行往後的過程。 8 · —種半導體裝置之製造方法，係屬於在配線基板 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -40- 550766 A8 B8 C8 D8 六、申請專利範圍 4 實裝被動元件用晶片及主動元件用晶片並加以裝配之半導 體裝置之製造方法，其特徵爲具有： (請先閲讀背面之注意事項再填寫本頁) 在上述配線基板之被動元件用晶片用端子印刷銲劑之 過程；及 上述銲劑印刷後，將銲劑藉由接合塗布於上述配線基 板之凹部之過程；及 將上述被動動元件用晶片配置在上述配線基板之過程 ;及 將上述主動元件用晶片配置在上述配線基板之上述凹 部之過程；及 進行銲劑溶融熱處理並將上述被動元件用晶片及上述 主動元件用晶片藉由銲劑接合實裝於上述配線基板之過程 Ο 9 .如申請專利範圍第8項所述之半導體裝置之製造 方法，其中，從接合用之噴嘴吐出上述銲劑時，將上述噴 嘴以最短距離移動至上述配線基板內及鄰接之其他之配線 基板，並在複數之上述配線基板之上述凹部吐出上述銲劑 經濟部智慧財產局員工消費合作社印製 〇 1 〇 . —種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 在上述配線基板之被動元件用晶片用端子印刷銲劑之 過程；及 在上述配線基板之凹部藉接合來塗布銲劑之過程；及 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -41 - 550766 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 ___ D8六、申請專利範圍 5 上述銲劑印刷後，將銲劑藉由接合塗布於上述配線基 板之凹部之過程；及 將上述被動元件用晶片配置在上述配線基板之過程； 及 將上述主動元件用晶片配置在上述配線基板之上述凹 部之過程；及 進行銲劑溶融熱處理並將上述被動元件用晶片及上述 主動元件用晶片藉由銲劑接合實裝於上述配線基板之過程 〇 1 1 . 一種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 將上述被動元件用晶片配置在上述配線基板之過程； 及 配置上述被動元件用晶片後，將上述主動元件用晶片 配置在上述配線基板之上述凹部之過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲 劑接合實裝於上述配線基板過程。 1 2 . —種半導體裝置之製造方法，係屬於在配線基 板貫裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 設於上述被動元件用晶片對於上述配線基板進行搭載 之零件搭載裝置之複數零件供應部中，將收納於各該零件 供應部之上述被動元件用晶片以零件供應部單位供應於上 本紙張又度適用中國國家標準（CNS ) A视^ ( 210X297公董)" " -42- (請先聞讀背面之注意事項再填寫本頁) 550766 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 6 述配線基板並加以配置之過程；及 將上述被動元件用晶片配置在上述配線基板之凹部之 過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲 劑接合實裝於上述配線基板之過程。 1 3 · —種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 認識形成在上述配線基板之被動元件用晶片用端子之 印刷銲劑圖案並在上述印刷銲劑圖案上配置上述被動元件 用晶片之過程；及 設於上述被動元件用晶片對於上述配線基板進行搭載 之零件搭載裝置之複數零件供應部中，將收納於各該零件 供應部之上述被動元件用晶片以零件供應部單位供應於上 述配線基板並加以配置之過程；及 將上述主動元件用晶片配置在上述配線基板之凹部之 過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲 劑接合實裝於上述配線基板之過程。 1 4 · 一種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 將上述被動元件用晶片配置在上述配線基板之過程； 及 I紙張尺度適用巾國國家標準（CNS )八视# ( 21〇X297公釐) " -43- (請先閱讀背面之注意事項再填寫本頁) 550766 A8 B8 C8 D8 5、申請專利範圍 7 設於上述主動元件用晶片對於上述配線基板進行搭載 之小片搭載裝置之複數小片供應部中，將收納於各該小片 供應部之上述主動兀件用晶片以小片供應部單位供應於上 述配線基板之凹部並加以配置之過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲 劑接合實裝於上述配線基板之過程。 15· ~^種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 將上述被動元件用晶片配置在上述配線基板之過程； 及 認識上述配線基板之凹部緣部，在上述凹部配置上述 主動元件用晶片之過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲 劑接合實裝於上述配線基板之過程。 1 6 · —種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 將上述被動元件用晶片配置在複數上述配線基板藉由 分割用槽部被區劃形成之多數個收納基板之上述配線基板 之過程；及 將上述主動元件用晶片配置在上述配線基板之凹部之 過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） (請先聞讀背面之注意事項再填寫本頁) 、τ.- 經濟部智慧財產局員工消費合作社印製 -44- 550766 A8 B8 C8 D8 六、申請專利範圍 8 劑接合實裝在上述配線基板之過程；及 利用接合避開上述分割用槽部將上述封閉用樹脂塗布 在複數上述配線基板之凹部，俾樹脂封閉上述主動元件用 晶片之過程。 1 7 · —種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 將上述被動元件用晶片及上述主動元件用晶片配置在 複數之上述配線基板所形成之多數個收納基板之上述配線 基板並將上述被動元件用晶片及上述主動元件用晶片實裝 在上述配線基板之過程；及 將支撐可卡合於上述配線基板之鈎的鈎支撐部對應地 設置之掘接帽之其中一方的上述鈎支撐部斜向地插入在上 述多數個收納基板之鈎孔，俾將上述插接帽安裝於上述多 數個收納基板之過程； 藉由上述插接帽來覆蓋上述多數個收納基板之上述配 線基板上之上述被動元件用晶片及上述主動元件用晶片。 1 8 ·如申請專利範圍第1 7項所述之半導體裝置之 製造方法，其中，在上述多數個收納基板安裝複數上述插 接帽時，相對應於上述插接帽之上述鈎支撑部中，從配置 於未安裝有鄰接之插接帽之一側的上述鈎支撑部插入在上 述多數個收納基板之上述鈎孔而將上述插接帽安裝於上述 多數個收納基板。 1 9 · 一種半導體裝置之製造方法，係屬於在配線基 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 、一Sr 經濟部智慧財產局員工消費合作社印製 -45- 550766 8 88 8 ABCD 六、申請專利範圍 。 y 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： (請先閱讀背面之注意事項再填寫本頁) 將上述被動元件用晶片及上述主動元件用晶片配置在 複數之上述配線基板所形成之多數個收納基板之上述配線 基板並將上述被動元件用晶片及上述主動元件用晶片實裝 在上述配線基板之過程；及 將支撑可卡合於上述配線基板之鈎的鈎支撑部對應地 設置之插接帽之其中一方的上述鈎支撑部斜向地插入在上 述多數個收納基板之鈎孔之過程；及 對於插入在上述鈎孔之上述其中一方的鈎支撑部，藉 由上述配線基板賦與載重，將上述其中一方之鈎支撑部朝 從另一方之支撑部離開之方向撓曲在其彈性領域內，並將 另一方之鈎支撑部之鈎配置在上述多數個收納基板之其他 钩：fL之過程；及 在上述其他之鈎孔插入上述另一方之鈎支撑部之過程 ;及 經濟部智慧財產局員工消費合作社印製 開放依上述配線基板之載重之賦與，將上述鈎及上述 其他鈎卡合於上述配線基板，並將上述插接帽安裝於上述 多數個收納基板之過程。 2 〇 · —種半導體裝置之製造方法，係屬於在配線基 板實裝被動元件用晶片及主動元件用晶片並加以裝配之半 導體裝置之製造方法，其特徵爲具有： 將上述被動元件用晶片配置經選別之上述配線基板之 過程；及 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） -46- 550766 A8 B8 C8 _ D8 夂、申請專利範圍 ％ 將經選別之上述被動元件用晶片配置於上述配線基板 之凹部之過程；及 將上述被動元件用晶片及上述主動元件用晶片藉由銲 劑接合實裝在上述配線基板之過程； 裝配分別經選別之上述配線基板及上述主動元件用晶 片並加以實裝成上述半導體裝置之特性能進入容許範圍。 2 1 .如申請專利範圍第1項所述之半導體裝置之製 造方法，其中上述被動元件用晶片爲電阻元件用晶片，或 電容元件用晶片，上述主動元件用晶片爲電晶體晶片。 2 2 ·如申請專利範圍第2 1項所述之半導體裝置之 製造方法，其中上述電晶體晶片爲構成高頻放大電路。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -47--39- 550766 Printed by A8, B8, C8, D8, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application 3 Dividing the above wiring substrate along the above-mentioned multiple package formation fields, thereby forming semiconductors in the process of forming multiple packages The manufacturing method of the device is characterized in that the process of preparing the wiring substrate includes a process of inspecting each of the plurality of package forming areas and forming a defective mark in a defective area; and in the package forming area in which the defective mark is formed, The passive device wafer, the active device wafer, and the plug cap are mounted. 7 · A method for manufacturing a semiconductor device belongs to the process of: preparing a wiring substrate having a plurality of package formation areas; and mounting a passive element wafer on each main surface of the plurality of package formation areas of the wiring substrate, and A process for a wafer for an active element; and a process for installing a plurality of plug caps in a plurality of package formation fields of the wiring substrate in a manner capable of covering the wafer for the passive element and the wafer for the active element; and along the plurality of The method of manufacturing a semiconductor device in the process of forming a plurality of packages by dividing the above-mentioned wiring substrate in the field of package formation is characterized by: inspecting each of the above processes to recognize defective products, and attaching Defective mark process; the subsequent processes are not performed in the plurality of package forming fields with the above-mentioned bad mark. 8 · —A method for manufacturing semiconductor devices, which belongs to the Chinese National Standard (CNS) A4 specification (210X297 mm) for the paper size of the wiring substrate (Please read the precautions on the back before filling this page) -40- 550766 A8 B8 C8 D8 VI. Patent application scope 4 The manufacturing method of a semiconductor device for mounting and assembling wafers for passive components and wafers for active components is characterized by: (Please read the precautions on the back before filling this page) The process of printing solder on the terminal for the passive element wafer of the wiring substrate; and the process of applying the solder to the concave portion of the wiring substrate by bonding after the solder printing; and the process of disposing the wafer for the passive component on the wiring substrate. And the process of disposing the active element wafer in the recessed portion of the wiring substrate; and performing a solder melting heat treatment and mounting the passive element wafer and the active element wafer on the wiring substrate by solder bonding. 9. Manufacture of semiconductor device as described in item 8 of the scope of patent application A method in which, when the flux is discharged from a nozzle for bonding, the nozzle is moved to the wiring substrate and other adjacent wiring substrates by the shortest distance, and the flux is discharged from the recesses of the plurality of wiring substrates. Printed by the employee's consumer cooperative of the Property Bureau 〇 〇. A semiconductor device manufacturing method, which belongs to a semiconductor device manufacturing method in which passive chip and active element wafer are mounted on a wiring substrate and assembled, is characterized by: The process of printing solder on the terminals of the above-mentioned wiring substrate for passive component wafers; and the process of applying solder by bonding on the recessed portions of the above wiring substrate; and this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)- 41-550766 Printed by A8, B8, C8, _D8, Consumer Cooperatives of the Ministry of Economic Affairs and Intellectual Property. VI. Patent application scope 5 After the above solder is printed, the solder is applied to the recessed portion of the wiring substrate by bonding; and the passive components are used The process of disposing a chip on the above wiring substrate; and A process in which the active element wafer is disposed in the concave portion of the wiring substrate; and a process in which a solder melting heat treatment is performed and the passive element wafer and the active element wafer are mounted on the wiring substrate by solder bonding. A manufacturing method of a semiconductor device belongs to a manufacturing method of a semiconductor device in which a passive element wafer and an active element wafer are mounted on a wiring substrate and assembled, and is characterized in that: the passive element wafer is arranged on the wiring substrate; Process; and the process of arranging the active element wafer in the recess of the wiring substrate after disposing the passive element wafer; and mounting the passive element wafer and the active element wafer on the wiring by solder bonding Substrate process. 1 2. A method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which a wafer for a passive device and a wafer for an active device are mounted on a wiring board, and the method is characterized in that: In the plurality of component supply units of the component mounting device on which the wiring board is mounted, the passive component wafers stored in each of the component supply units are supplied to the upper paper in units of the component supply unit, and the Chinese National Standard (CNS) A is also applied. Video ^ (210X297 public director) " " -42- (Please read the precautions on the back before filling out this page) 550766 A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application 6 A process of disposing the wiring substrate; and a process of disposing the passive element wafer in the recess of the wiring substrate; and a process of mounting the passive element wafer and the active element wafer on the wiring substrate by solder bonding. . 1 3-A method for manufacturing a semiconductor device belongs to a method for manufacturing a semiconductor device in which a passive element wafer and an active element wafer are mounted on a wiring substrate and assembled, and is characterized by: recognition of the passive components formed on the wiring substrate; A process of printing a solder pattern on a terminal for a wafer for an element and disposing the wafer for a passive element on the printed solder pattern; and a plurality of parts supply sections provided in a component mounting device for mounting the wiring board on the wafer for the passive element, A process of supplying the passive component wafers stored in each of the component supply units to the wiring substrate and arranging them in units of a supply unit; and a process of arranging the active element wafers in the recesses of the wiring substrate; and The process of mounting the passive element wafer and the active element wafer on the wiring substrate by solder bonding. 1 4 · A method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which a passive device wafer and an active device wafer are mounted on a wiring board and assembled, and the method includes: The process of the wiring substrate; and the national paper standard (CNS) Ba Shi # (21〇X297mm) for paper size application-"-43- (Please read the precautions on the back before filling this page) 550766 A8 B8 C8 D8 5. Scope of patent application 7 In the plurality of small chip supply units of the small chip mounting device for mounting the wiring board on the active component wafer, the active component wafers stored in each small chip supply unit are divided into small chip supply units. A process of supplying and disposing the recessed portion of the wiring substrate; and a process of mounting the wafer for the passive element and the wafer for the active element on the wiring substrate by solder bonding. 15 · ~ ^ A method for manufacturing a semiconductor device belongs to a method for manufacturing a semiconductor device in which a passive device wafer and an active device wafer are mounted on a wiring substrate and assembled, and is characterized in that: The process of the wiring substrate; and the process of recognizing the edge of the recessed portion of the wiring substrate and disposing the wafer for the active element in the recess; and mounting the wafer for the passive element and the wafer for the active element on the wiring by solder bonding Substrate process. 16 A manufacturing method of a semiconductor device belongs to a manufacturing method of a semiconductor device in which a passive device wafer and an active device wafer are mounted on a wiring board and assembled, and is characterized in that: A process of arranging the plurality of wiring substrates in which the plurality of wiring substrates are divided into grooves for dividing the substrate; and a process of disposing the active device wafer in the recessed portion of the wiring substrate; and disposing the passive device wafer and The above-mentioned chip for active components is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) by soldering the paper size (please read the precautions on the back before filling this page), τ.- Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employee consumer cooperatives-44- 550766 A8 B8 C8 D8 VI. Patent application process of 8-component bonding and mounting on the above wiring substrate; and using bonding to avoid the above-mentioned dividing grooves and coating the above-mentioned sealing resin on the above-mentioned wiring The recessed part of the substrate is filled with a resin to seal the wafer for the active device. 1 ·· A method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which a passive device wafer and an active device wafer are mounted on a wiring board, and the semiconductor device is characterized in that: A process in which the active device wafer is disposed on the above-mentioned wiring substrate that houses a plurality of storage substrates formed by the plurality of the above-mentioned wiring substrates, and the passive device wafer and the active device wafer are mounted on the wiring substrate; One of the hook support portions provided correspondingly to the hook support portion of the hook of the wiring board is inserted obliquely into the hook holes of the plurality of storage substrates, and the plug cap is mounted to the plurality of The process of accommodating the substrate; covering the plurality of accommodating substrates on the wiring substrate by the plug cap to cover the passive component wafer and the active component wafer. 1 8 · The method for manufacturing a semiconductor device according to item 17 of the scope of patent application, wherein, when the plurality of the above-mentioned plug caps are mounted on the plurality of storage substrates, the hook support portions corresponding to the plug caps, The hook support portion disposed on one side where the adjacent plug caps are not attached is inserted into the hook holes of the plurality of storage substrates, and the plug caps are mounted on the plurality of storage substrates. 1 9 · A method for manufacturing semiconductor devices, which belongs to the national paper (CNS) A4 specification (210X297 mm) applicable to the basic paper size of the wiring (please read the precautions on the back before filling this page), a Sr Ministry of Economy wisdom Printed by the Consumer Cooperative of the Property Bureau-45- 550766 8 88 8 ABCD 6. Scope of patent application. y A method for manufacturing a semiconductor device in which a passive element wafer and an active element wafer are mounted on a board, and the method is as follows: (Please read the precautions on the back before filling this page) The process of disposing the component wafer on the wiring substrate including a plurality of the storage substrates formed by the plurality of the wiring substrates, and mounting the passive component wafer and the active component wafer on the wiring substrate; and mounting the support on the wiring substrate; A process in which one of the above-mentioned hook support portions of the plug caps corresponding to the hook support portions of the hooks of the wiring substrate is inserted obliquely into the hook holes of the plurality of storage substrates; and One of the hook support portions is subjected to a load by the wiring board, and the one of the hook support portions is flexed in a direction away from the other support portion in its elastic area, and the other hook support portion is bent. The other hooks arranged on the above-mentioned plurality of storage substrates: the process of fL; and the above-mentioned other hook holes are inserted The process of the hook support part of one party; and the printing and opening of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs according to the load of the wiring board, the hook and the other hooks are engaged with the wiring board, and the plug cap The process of mounting on the plurality of storage substrates described above. 2 〇—A method for manufacturing a semiconductor device belongs to a method for manufacturing a semiconductor device in which a passive element wafer and an active element wafer are mounted on a wiring board and assembled, and is characterized by: The process of selecting the above-mentioned wiring substrates; and this paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) -46- 550766 A8 B8 C8 _ D8 夂, the scope of patent application% of the above-mentioned passive components will be selected The process of using a wafer to arrange in the recess of the wiring substrate; and the process of mounting the passive component wafer and the active component wafer on the wiring substrate by solder bonding; assembling the selected wiring substrate and the active component respectively The characteristics of using the wafer and mounting it into the above-mentioned semiconductor device are within the allowable range. 2 1. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the passive element wafer is a resistor element wafer or a capacitor element wafer, and the active element wafer is a transistor wafer. 2 2 · The method for manufacturing a semiconductor device according to item 21 of the scope of patent application, wherein the transistor wafer constitutes a high-frequency amplifier circuit. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 (210 X 297 mm) -47-
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