WO2001061744A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
WO2001061744A1
WO2001061744A1 PCT/JP2000/000828 JP0000828W WO0161744A1 WO 2001061744 A1 WO2001061744 A1 WO 2001061744A1 JP 0000828 W JP0000828 W JP 0000828W WO 0161744 A1 WO0161744 A1 WO 0161744A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
chip
mounting
element chip
passive element
Prior art date
Application number
PCT/JP2000/000828
Other languages
French (fr)
Japanese (ja)
Inventor
Akio Ishizu
Kazutoshi Takashima
Shiro Oba
Yoshihiko Kobayashi
Tsutomu Ida
Shigeru Haga
Susumu Takada
Iwamichi Koujiro
Original Assignee
Hitachi, Ltd.
Hitachi Tohbu Semiconductor, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP2000/000828 priority Critical patent/WO2001061744A1/en
Priority to AU2000224628A priority patent/AU2000224628A1/en
Priority to TW089106119A priority patent/TW550766B/en
Priority to CNB018033148A priority patent/CN1222036C/en
Priority to US10/129,305 priority patent/US6852553B2/en
Priority to KR1020027010498A priority patent/KR100689129B1/en
Priority to AU32308/01A priority patent/AU3230801A/en
Priority to PCT/JP2001/001091 priority patent/WO2001061754A1/en
Publication of WO2001061744A1 publication Critical patent/WO2001061744A1/en
Priority to US10/983,689 priority patent/US6946306B2/en
Priority to US11/178,423 priority patent/US20050250254A1/en

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Classifications

    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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    • H01L2224/481—Disposition
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Definitions

  • the present invention relates to a semiconductor manufacturing technique, and more particularly to a technique that is effective when applied to a method for manufacturing a high-frequency module (high-frequency power amplifier).
  • a high-frequency power amplifying device called a high-frequency module (also referred to as an RF module or an RF power module) in which surface-mounted chip components such as a chip capacitor and a chip resistor and a semiconductor pellet for bare chip mounting are mounted
  • a high-frequency module also referred to as an RF module or an RF power module
  • surface-mounted chip components such as a chip capacitor and a chip resistor and a semiconductor pellet for bare chip mounting are mounted
  • Japanese Patent Application Laid-Open No. H10-128808 (Numanami) describes the structure and electrical characteristics of a high-frequency module and a large number of individual units for assembling a plurality of high-frequency modules collectively. It describes the structure of the substrate and the like.
  • a method of mounting a cap on a hybrid IC is described in, for example, Japanese Patent Application Laid-Open No. Hei 6-307207 (Morizumi). It describes how to attach caps to singulated substrates.
  • Japanese Patent Application Laid-Open No. H10-12808 does not describe marks such as letters and symbols attached to the cap, and further describes a method of attaching the cap to the multi-piece board in detail, a chip component ( There is no description of mounting techniques such as electronic components) and semiconductor pellets, and solder printing and solder potting methods on multi-cavity boards.
  • Japanese Patent Application Laid-Open No. Hei 6-320707 does not describe a method of mounting a cap on a multi-cavity substrate.
  • An object of the present invention is to provide a method for manufacturing a semiconductor device which reduces the number of manufacturing steps and rationalizes a manufacturing line.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device which aims to reduce manufacturing costs. To provide.
  • Still another object of the present invention is to provide a method for manufacturing a semiconductor device which reduces material costs.
  • a method for manufacturing a semiconductor device includes the steps of: disposing a passive element chip and an active element chip on a wiring board and mounting the passive element chip and the active element chip on the wiring board; Attaching a cap with a mark to the wiring board, and covering the passive element chip and the active element chip with the cap.
  • the method of manufacturing a semiconductor device includes the steps of: disposing a passive element chip and an active element chip on a wiring board and mounting the passive element chip and the active element chip on the wiring board;
  • the above-mentioned recognition mark of the cap having the recognition mark on the surface is inspected, and after the inspection, a non-defective product cap is attached to the wiring board, and the passive element chip and the active element chip are covered by the cap. And a process.
  • a non-defective mark, a defective mark, or a cap of a defective mark such as a cap of another mark is attached because a non-defective cap is attached to the wiring board after inspecting the recognition mark of the cap having the recognition mark. Can be prevented.
  • the defective cap for the recognition mark is not attached, so that the production line can be streamlined.
  • the method of manufacturing a semiconductor device of the present invention is a method of mounting a passive element chip and an active element chip on a wiring board of a multi-piece board on which a plurality of wiring boards are formed. Arranging the passive element chip and the active element chip on the wiring board of the multi-piece substrate and mounting the passive element chip and the active element chip on a non-defective wiring board; The cap Covering the passive element chip and the active element chip with the cap by attaching only to a non-defective wiring board.
  • a passive element chip and an active element chip are mounted only on a wiring board of a multi-cavity board that has been inspected, thereby omitting work on this defective portion in a semiconductor device manufacturing process. be able to.
  • a passive element chip and an active element chip are mounted on a wiring board and assembled, and solder is printed on the passive element chip terminals of the wiring board.
  • solder printing After the solder printing, a step of applying solder to the concave portion of the wiring board by potting, a step of disposing the passive element chip on the wiring board, and a step of attaching the active element chip to the wiring board. Arranging the passive element chip and the active element chip on the wiring board by solder connection by performing solder reflow.
  • solder is printed on the passive element chip terminals of the wiring board, and then the solder is applied to the recesses of the wiring board by potting, so that the solder printing is performed first. It is possible to prevent the solder mask from being stained by the solder.
  • the method of manufacturing a semiconductor device includes a step of mounting a passive element chip and an active element chip on a wiring board, and assembling the passive element chip on the wiring board. After disposing the passive element chip, the method includes a step of disposing the active element chip in the recess of the wiring board, and a step of mounting the passive element chip and the active element chip on the wiring board by soldering. Things.
  • the passive element chip and the active element chip are mounted on a wiring board and assembled, and the plurality of wiring boards are defined by dividing grooves. Disposing the passive element chip on the wiring board of the multi-cavity board; and placing the active element chip in a recess of the wiring board. Disposing; mounting the passive element chip and the active element chip on the wiring board by soldering; and avoiding the dividing groove by potting a plurality of recesses of the wiring board. Applying the sealing resin and sealing the active element chip with resin.
  • the method of manufacturing a semiconductor device is characterized in that a passive element chip and an active element chip are mounted on a wiring board and assembled, and the wiring of the multi-piece board on which a plurality of the wiring boards are formed is provided. Disposing the passive element chip and the active element chip on a substrate and mounting the passive element chip and the active element chip on the wiring board; and supporting a hook engageable with the wiring board. Attaching the cap to the multi-piece substrate by obliquely inserting one of the hook supports of the cap provided with the hook support portions facing each other into a hook hole of the multi-piece board. The cap for covering the chip for the passive element and the chip for the active element on the wiring board of the multi-piece substrate.
  • the passive element chip and the active element chip are mounted on a wiring board and assembled, and the passive element chip is arranged on the selected wiring board.
  • the above-mentioned wiring board and the active element chip are mounted in combination so that the characteristics of the semiconductor device fall within an allowable range.
  • FIGS. 1A and 1B are views showing an example of an embodiment of the structure of a high-frequency module assembled by the method for manufacturing a semiconductor device according to the present invention, wherein FIG. 1A is a perspective view, FIG. 1B is a cross-sectional view, and FIG. Fig. 3 is a bottom view showing the structure of the high-frequency module shown in Fig. 3, and Fig. 3 is a manufacturing process diagram showing an example of the assembly procedure in the method for manufacturing the high-frequency module shown in Fig. 1-Fig.
  • FIGS. 3A and 3B are diagrams showing an example of the structure of a substrate to be inserted and a defective mark wiring substrate, (a) is a perspective view of a multi-piece substrate, (b) is a plan view of the defective mark wiring substrate during component mounting inspection, and (c).
  • FIG. 7A is a plan view illustrating a movement trajectory on a wiring board
  • FIG. 7B is a perspective view illustrating a movement trajectory on a multi-cavity board
  • FIG. FIG. 7A is a plan view illustrating a movement trajectory on a wiring board
  • FIG. 7B is a perspective view illustrating a movement trajectory on a multi-cavity board
  • FIG. FIG. 7A is a plan view illustrating a movement trajectory on a wiring board
  • FIG. 7B is a perspective view illustrating a movement trajectory on a multi-cavity board
  • FIG. 3 is a view showing an example of an embodiment of a substrate structure in a solder printing step and a solder potting step of the method of manufacturing a semiconductor device according to the present invention, wherein (a) is a plan view of a multi-piece substrate before solder formation; (B) is the wiring board before solder formation FIG. 8C is a plan view of the wiring board after solder printing and solder potting.
  • FIG. 8 is an embodiment of the structure of the component mounting apparatus used in the component mounting step of the semiconductor device manufacturing method according to the present invention.
  • FIGS. 9A and 9B are views showing an example of the structure, wherein FIG. 9A is an external perspective view, FIG. 9B is a block diagram of the configuration, and FIG.
  • FIG. 1 is a view showing an example of an embodiment, in which (a) is an external perspective view, (b) is a configuration block diagram, and FIG. 10 is a diagram showing a method of manufacturing a semiconductor device according to the present invention.
  • FIG. 1 is a view showing an example of an embodiment of a structure of a substrate.
  • (A) is a plan view of a substrate after mounting components
  • (b) is a plan view of a substrate after mounting a pellet
  • FIG. Of the board structure at the time of component position detection in the automatic appearance inspection process of 1A is a plan view of a multi-piece substrate, FIG.
  • FIGS. 3A and 3B are diagrams illustrating an example of an embodiment of a substrate structure, in which FIG. 3A is a plan view of a multi-piece substrate, FIG. 3B is a plan view of a wiring substrate, and FIG. FIGS. 3A and 3B are diagrams illustrating an example of an embodiment of a structure of a cap used in a cap insertion step, in which FIG. 1A is a plan view, FIGS. 1B and 1C are side views, and FIG. FIG.
  • FIG. 15 shows an example of a method of recognizing hook holes of a multi-piece substrate in a cap insertion step of a method of manufacturing a semiconductor device according to the present invention.
  • (A) is a front view showing a recognition state
  • (b) is a hook hole of a multi-piece board. Plan view, the implementation of cap transferring method in cap ⁇ process of the manufacturing method of FIG. 1 6
  • FIG. 17 is a diagram showing an example of an embodiment of a cap insertion method in a cap insertion step of a method of manufacturing a semiconductor device according to the present invention
  • FIG. FIG. 18B is a principle diagram
  • FIG. 18B is a diagram showing the state of the cap inserted in FIG. 17A
  • FIG. 19 is a method of manufacturing a semiconductor device of the present invention.
  • FIGS. 3A and 3B are views showing an example of a state after a cap is inserted in a cap insertion step of FIG. 1A, wherein FIG. 2A is a front view, FIG. 2B is an enlarged partial cross-sectional view of a wiring board, and FIG. An example of the operation of the cap mounting device after cap insertion in the cap insertion process of the manufacturing method is shown. Operation principle diagram, FIG.
  • FIG. 21 is an output characteristic diagram showing an example of a characteristic inspection result in a characteristic selection step of the semiconductor device manufacturing method of the present invention
  • FIG. 22 is a pellet characteristic inspection of the semiconductor device manufacturing method of the present invention
  • FIG. 14 is a diagram showing a pellet grade showing an example of an inspection result.
  • FIGS. 1 and 2 show the structure of a semiconductor device (high-frequency module 1)
  • FIG. 3 shows a procedure for assembling the high-frequency module 1
  • FIG. This will be described with reference to the cross-sectional view of the wiring board and the drawing of the defective mark wiring board shown in FIG.
  • the semiconductor device assembled by the method for manufacturing a semiconductor device according to the first embodiment shown in FIGS. 1 and 2 is a high-frequency power amplifier, which is called a high-frequency module 1 (also referred to as a high-frequency power module).
  • the cap 4 is superimposed on the main surface (upper surface) of the substrate 2, and has a flat rectangular structure in appearance.
  • semiconductor pellets 21 active element chips
  • chip components 22 passive element chips
  • surface-mounted or surface-mounted components such as surface-mount type chip capacitors and chip resistors and passive components.
  • the outer edge of the cap 4 coincides with or is located inside the outer edge of the wiring board 2.
  • the cap 4 has a structure in which a metal plate is drawn into a rectangular box shape and has a peripheral wall 3 protruding along the lower surface periphery.
  • the cap 4 is provided with hook support arms (hook support portions) 17 protruding downward from the peripheral wall 3 at the center on both sides thereof. Further, inside the tip side of the hook support arm 17, a protruding hook claw 18 also formed by molding is provided. The hook 19 and the hook support arm 17 form a hook 19 which is a locking portion having elasticity.
  • the thickness of the cap 4 is, for example, about 0.1 mm, and is formed of a nickelless nickel silver (an alloy of nickel, copper, and zinc), a nickel-plated phosphor bronze, or the like. This enhances the wettability with the solder.
  • a recess 15 In the center of both sides of the wiring board 2, there is formed a recess 15 in which the hook support arm 17 is disposed. At the bottom of the recess 15 is a further recessed hook 16. The hook claw 18 of the hook 19 is formed and is engaged with the hook portion 16.
  • the hook support arm 17 does not protrude outside the recess 15 when the hook claw 18 is hooked on the hook portion 16.
  • the hook support arm 17 is formed of a metal plate, an elastic force can be applied to the hook 19. Accordingly, the tip of the peripheral wall 3 of the cap 4 comes into contact with the main surface of the wiring board 2, and the hook 4 is elastically hooked on the back surface of the wiring board 2, so that the cap 4 is attached to the wiring board 2. It can be fixed securely.
  • the cap 4 can be easily removed.
  • the locking portion between the wiring board 2 and the cap 4 may have another structure.
  • a plurality of external terminals 5 are provided on the back surface of the wiring board 2, and these external terminals 5 are provided on both sides in the longitudinal direction of the back surface of the wiring board 2. They are arranged at almost constant intervals, and one row (upper row shown in Fig. 2) has, from left to right, an input terminal (P in) 6, a ground terminal (GND) 7, and a ground terminal ( GND) 8 and gate bias terminal (Vg) 9 are provided, and the other column (lower column shown in FIG. 2) has output terminals (P out) 10 from left to right. , A ground terminal (GND) 11, a ground terminal (GND) 12, and a power supply terminal (Vdd) 13 are provided.
  • the side of the wiring board 2 corresponding to the input terminal 6, the gate bias terminal 9, the output terminal 10 and the power supply terminal 13 is arranged from the front side to the back side as shown in FIG.
  • An end face through hole 20 is provided at every position. This is because when mounting the high-frequency module 1 on a mounting board such as a printed wiring board, each external terminal 5 is connected to the electrode portion on the back surface of the wiring board 2 and the through hole 20 on the side face of the side face. As a result, the high-frequency module 1 can be reliably mounted.
  • a region extending so as to partition the four ground terminals 7, 8, 11 and 12 is provided with a mounting bonding material used when mounting the high-frequency module 1 (for example, , Solder) is provided with a resist film 14 made of a material that does not wet.
  • the chip component 22 is mounted on the surface of the wiring board 2, and the recess 2a which is a cavity formed on the surface of the wiring board 2 is provided in the recess 2a.
  • the pellet 21 is mounted via the solder connection part 26.
  • the chip part 22 is formed with a solder fillet 25 to form an electrode for the chip part of the wiring board 2 shown in FIG. 5 (b).
  • 2 b terminal for a chip for passive element
  • the pad which is the surface electrode is connected to the board side terminal of the wiring board 2 by a wire 24 such as a gold wire. 2 Connected to i.
  • the semiconductor pellet 21 and the wires 24 are resin-sealed with a sealing resin 23 such as an epoxy resin.
  • the size of the high-frequency module 1 is, for example, 8 mm in width, 12.3 mm in length, and 1.8 mm in height.
  • the high-frequency module 1 is assembled by the assembly procedure (manufacturing process) shown in Fig. 3.
  • Each process consists of solder printing for mounting chip components (Step S1, Figure 4 (a)) and solder potting for mounting semiconductor pellets (Step S2, Figure 4 ( b)), component mounting for mounting chip components 22 (Step S3, FIG. 4 (c)), mounting of pellets for mounting semiconductor pellet 21 (Step S4, FIG. 4 (d)), Solder reflow (including cleaning (Step S5)), automatic appearance inspection after reflow (Step S6), wire bonding (Step S7, Fig. 4 (e)), appearance inspection after wire bonding (Step S5) Step S 8), resin application (step S 9, FIG.
  • Multi-cavity board 27 is divided into wiring board 2 which is a single board Substrate division (Step SI 1) that the high-frequency module - a characteristic evaluation of the Le 1 (Step S 1 2, Fig. 4 (h)) and the high frequency module 1 of the taping (Step S 1 3, FIG. 4 (i)).
  • step S10 from the solder printing in step S1 to the insertion of the cap (including the marking) in step S10, the multi-piece board 27 on which the plurality of wiring boards 2 are formed is formed.
  • step S11 the multi-piece board 27 is divided into wiring boards 2 which are individual boards, and as a result, the characteristic selection and the steps in step S12 are performed.
  • the taping of S 13 is performed in the form of the high-frequency module 1 having the wiring board 2.
  • the manufacturing cost and material cost of the high-frequency module 1 can be reduced by manufacturing the multi-cavity substrate 27 without dividing it into the individual wiring boards 2 until the final stage of the assembly process of the high-frequency module 1 In addition, a smooth assembly can be achieved, and the production line can be streamlined.
  • assembly is performed by applying the following method.
  • the chip component 22 and the semiconductor pellet 21 are placed only on the wiring board 2 of the inspected multi-cavity board 27 shown in FIG. Is mounted on a non-defective wiring board 2, thereby In the cap insertion process of S 1 ⁇ , the cap 4 is attached only to the non-defective wiring board 2.
  • the inspection of the wiring board 2 of the multi-piece board 27 at the delivery (purchase) stage (this inspection may be performed in advance by the board maker, and the inspected board may be delivered, or Blocks that are determined to be defective in either case (whichever may be performed later), that is, wiring board 2, are marked with a defect mark 2e as shown in FIG. 5 (a), and a series of subsequent steps (step S3 In the process from mounting of the component to insertion of the cap in step S10), the defective mark 2e is recognized in each process, and the work on the wiring board 2 on which the defective mark 2e is formed is omitted.
  • the manufacturing cost of the high-frequency module 1 can be reduced.
  • the board failure at the stage of delivering a multi-cavity board is, for example, an electrical failure such as a circuit open due to a short circuit or disconnection of the circuit, or a poor appearance such as a warp or short circuit in the appearance.
  • the defective mark 2e is not melted by washing after soldering, and in order to facilitate pattern recognition, a mark ink for a semiconductor or the like is used. Do.
  • each process is inspected to recognize a process defective product which has become a defective product in the process, and a defective mark 2 e is attached to the wiring board 2 which has become a process defective product.
  • a defective mark 2 e is attached to the wiring board 2 which has become a process defective product.
  • the defect mark 2e is recognized by pattern recognition in the component mounting process in step S3 shown in FIG.
  • the chip component 22 is not mounted on the wiring board 2 which is detected and becomes a defective block.
  • step S4 the defective mark 2e is detected by pattern recognition and the wiring board 2 which becomes a defective block is provided with the semiconductor pellet 21. Do not mount.
  • the defective mark 2e is detected by pattern recognition and counted as defective without performing the inspection.
  • the block (wiring board 2) determined to be defective in the automatic appearance inspection is provided with a defective mark 2e made of quick-drying ink by coating or the like as shown in FIG. 5 (c).
  • step S7 the defective mark 2e at the time of delivery and the defective mark 2e at the time of appearance inspection after mounting the component pellet are detected by pattern recognition, and the wiring board 2 which becomes a defective block is detected. Do not perform wire bonding. Further, in the appearance inspection after the wire bonding in step S8, as shown in FIG. 5 (d), a defective mark 2e made of quick-drying ink is applied as wire bonding appearance defects as shown in FIG. 5 (d).
  • the defective mark 2e at the time of delivery, the defective mark 2e at the time of appearance inspection after mounting the part pellet, and the defective mark 2e at the time of appearance inspection after wire bonding are pattern-recognized.
  • the resin is not applied to the wiring board 2 which is detected as a defective block and becomes a bad block.
  • step S10 the defective mark 2e at the time of delivery, the defective mark 2e at the time of appearance inspection after mounting the component 'pellet', and the defective mark 2e at the time of appearance inspection after wire bonding are patterned.
  • a cap is not inserted into the wiring board 2 that is detected by recognition and becomes a defective block.
  • step S11 the presence or absence of the cap 4 is detected by a sensor or the like, and the wiring board 2 with the cap 4 is stored as a good product, while the cap 4 is not attached. Wiring board 2 is treated as defective.
  • the manufacturing cost of the high-frequency module 1 can be reduced.
  • the multi-cavity substrate 27 is, for example, a ceramic substrate of multilayer wiring, and its size is, for example, 78.75 when 40 wiring substrates 2 are formed. m mx 75.0 mm.
  • the multi-piece substrate 27 may be a glass epoxy substrate other than the ceramic substrate.
  • each wiring board 2 of the multi-cavity board 27 has a surface as shown in FIG. 5 (b) according to the number of semiconductor pellets 21 and chip parts 22 mounted on the bare chip.
  • One or a plurality of recesses 2a for mounting a semiconductor pellet and chip component electrodes 2b for mounting chip components are formed, and as shown in FIG.
  • step S1 solder printing in step S1 is performed on the multi-piece substrate 27 shown in FIG. 7 (a).
  • solder printing is performed on the chip component electrode 2b (see FIG. 5 (b)) on the surface 27a of the wiring board 2 shown in FIG. 7 (b) in the multi-piece board 27, and FIG. a) and a printed solder pattern 2c as shown in FIG. 7 (c) is formed.
  • the solder printing is, for example, screen printing using a solder mask.
  • step S2 After the solder printing, the solder potting shown in step S2 is performed.
  • solder is applied to the concave portion 2a of each wiring board 2 of the multi-piece board 27 by potting, and the potting is applied as shown in FIGS. 4 (b) and 7 (c). Form solder 2 f.
  • the nozzle 2 8 As shown in FIG. 6, as a movement trajectory 29 of the nozzle 28 when the solder is ejected from the solder potting nozzle 28, the nozzle 2 8 is moved between adjacent recesses 2a in the wiring board 2 in the shortest distance and in a continuous operation (single-stroke operation) as shown in FIG. 6 (a), and as shown in FIG. 6 (). However, it is moved in a shortest distance and also in a continuous operation (single-stroke operation) with respect to another adjacent wiring substrate 2 in the multi-cavity substrate 27.
  • the movement trajectory 29 of the nozzle 28 is controlled by a mounting position coordinate program. To set.
  • solder printed solder pattern 2c
  • solder is printed on the chip component electrodes 2b of the wiring board 2
  • solder is potted on the recesses 2a of the wiring board 2.
  • the potting time can be shortened as a result, and thus the throughput of the solder potting process can be reduced. Can be improved.
  • step S3 of FIG. 3 After that, the components are mounted in step S3 of FIG. 3, and after the components are mounted, the pellet is mounted in step S4.
  • the component mounting device 30 transfers a large number of chip components 22 to the wiring board 2 of the circuit board 27, and mounts the chip components 22 on the wiring board 2, as shown in FIG. 8 (b).
  • the first component supply unit 31 component supply unit
  • the first component supply unit 31 that can send out the stored chip parts 22 (see Fig. 5 (c)) for each type (for example, product type)
  • Component supply section 3 2 component supply section
  • XY stage 34 supporting multi-cavity board 27, and mounting head section 33 mounting chip component 22 on XY stage 34
  • a board transfer section 35 for transferring the multi-piece board 27.
  • the first component supply unit 31 and the second component supply unit 32 are, for example, a tape feeder or a bulk feeder, and can be freely slid in the direction parallel to the board transfer direction of the board transfer unit 35. Have been.
  • the components A, B, C, D, E, and F) are supplied to the wiring board 2 for each component supply unit and are arranged.
  • the chip component 22 is mounted on the wiring board 2 as shown in FIG. 4 (c) and FIG. 10 (a).
  • the chip component 22 in the first component supply section 31 are mounted on the entire multi-piece board 27, and then all the chip components 22 in the second component supply section 32 are multi-piece boards 2. 7 Installed on the whole.
  • the moving distance of the first component supply unit 31 and the second component supply unit 32 can be reduced, and as a result, the throughput of the component mounting time can be improved.
  • Each component can be mounted.
  • the printed solder pattern 2 c formed on the chip component electrode 2 b of the wiring board 2 is recognized and the chip component electrode 2 b is formed on the printed solder pattern 2 c. Place.
  • the terminals of the chip component 22 and the electrode 2b for the chip component are securely soldered via the printed solder pattern 2c due to the self-alignment effect of the printed solder pattern 2c. Therefore, even when the printed solder pattern 2c is formed to be displaced from the chip component electrode 2b, it is possible to prevent the occurrence of defects such as component standing and component floating, which are likely to occur at that time.
  • the pellet mounting device 36 transfers a large number of semiconductor pellets 21 to the recess 2 a of the wiring board 2 of the substrate 27, and places the semiconductor pellet 21 in the recess 2 a of the wiring board 2.
  • a pellet supply system 37 that can send out the stored semiconductor pellets 21 by type (for example, product type), and a semiconductor pellet It comprises a bonding head section 38 for mounting 21, a board transfer section 39 for transferring a multi-piece board 27, and a monitor 40 for displaying the bonding position and the like.
  • the pellet supply system 37 includes, for example, a first pellet supply section 37a, a second pellet supply section 37b, and a third pellet supply section 37, which are four component supply sections. c and a fourth pellet supply unit 37 d are provided, and the component supply unit is, for example, a chip tray, and a rotating block 37 in the pellet supply system 37. attached to e.
  • the method of mounting the semiconductor pellet 21 in the pellet mounting device 36 is, for example, a direct pickup method from a pellet supply unit such as a chip tray or a semiconductor wafer.
  • the semiconductor pellets 21 accommodated therein (here, pellet A, pellet B, pellet). And Pellet D) are supplied to the wiring board 2 for each component supply unit and are arranged.
  • the semiconductor pellet 21 is mounted in the concave portion 2a of the wiring board 2.
  • the rotating block 37e is rotated to rotate the second pellet supply section 3.
  • All of the semiconductor pellets 21 in 7b are mounted on the entire multi-piece substrate 27.
  • the rotary block 37 e is rotated, and the semiconductor pellets 21 of the third pellet supply section 37 c and the fourth pellet supply section 37 d are sequentially taken into a large number, and the whole board 27 is taken. To be mounted on.
  • the edge 2 g of the recess 2 a of the wiring board 2 shown in FIG. 10 (b) is recognized and the semiconductor pellet 21 is placed in the recess 2 a. .
  • the position recognition accuracy of the concave portion 2a can be improved, and as a result, the size of the concave portion 2a can be made slightly larger than the size of the semiconductor pellet 21. Therefore, the rattling of the semiconductor pellet 21 in the concave portion 2a can be reduced, and as a result, the accuracy of the horizontal arrangement and inclination of the semiconductor pellet 21 can be improved. Wear.
  • the pads (surface electrodes) of the semiconductor pellet 21 can be easily recognized at the time of wire bonding, and as a result, defective wire bonding can be reduced.
  • the semiconductor pellet 21 has a higher probability of failure due to stress from the outside than the chip component 22, it is better to mount the semiconductor pellet 21 after mounting the chip component 22. Therefore, the possibility that the semiconductor pellet 21 is damaged can be reduced.
  • step S5 shown in FIG. 3 is performed.
  • solder reflow opening of the multi-piece board 27 is performed, and the chip component 22 and the semiconductor pellet 21 on the wiring board 2 are both connected by soldering.
  • step S6 an automatic appearance inspection in step S6 is performed.
  • the appearance inspection of the multi-cavity substrate 27 just after the riff opening is performed to check whether there is any defect in the riff opening.
  • the position of the mounted component when the position of the mounted component is detected using a laser beam or the like, the position of the mounted component can be accurately recognized by recognizing the stepped portion on the wiring board 2.
  • a through hole 2h shown in FIG. 11 (b) and a surface wiring 2d shown in FIG. 7 (b) formed on the wiring board 2 of the multi-piece board 27 shown in FIG. 11 (a) are recognized.
  • the position of the mounted component can be recognized with high accuracy.
  • step S7 wire bonding shown in step S7 is performed.
  • wire bonding is performed using a wire 24 such as a gold wire, and a pad serving as a surface electrode of the semiconductor pellet 21 and a plurality of corresponding pads are formed.
  • the board side terminal 2 i (see FIG. 5 (b)) of the wiring board 2 of the wiring board 27 is connected with the wire 24.
  • step S8 After that, the appearance inspection shown in step S8 is performed.
  • step S 9 the resin (encapsulating resin 23) shown in step S 9 is applied.
  • the sealing resin 23 is dropped on the concave portion 2 a of the wiring board 2 of the multi-piece board 27 by the potting method, thereby forming the semiconductor.
  • the pellet 21 and the wire 24 are sealed with a sealing resin 23.
  • the sealing resin 23 is applied by potting to the recess 2 a of the wiring board 2, avoiding the dividing groove 27 b of the multi-piece board 27 shown in FIG. 12 (a).
  • the semiconductor pellet 21 is sealed with resin.
  • the sealing resin 23 is not applied to the dividing groove portion 27 b which is a slit for dividing the individual substrate formed on the multi-cavity substrate 27.
  • the encapsulating resin 23 is applied to each individual block, that is, to each wiring board 2 on the multi-cavity board 27.
  • the sealing resin 23 is not applied to the dividing groove portion 27 b of the multi-piece substrate 27, so that the sealing resin 23 is removed from the through hole 2 h shown in FIG. 11B. 23 can be prevented from entering and sneaking into the back surface of the substrate, thereby adversely affecting when the substrate is divided.
  • cap insertion shown in step S10 is performed.
  • the cap 4 shown in FIG. 13 is marked with a mark as shown in FIG. 14 and the UV (Ultra Viol et) Drying, mark 4 Inspection of the mark appearance by pattern recognition of mark 2 and cap insertion are performed by continuous integrated processing, and when inserting the cap, only caps 4 judged as good by the mark appearance inspection are capped. In this way, it is possible to shorten the assembling time in the step of inserting the cap and to prevent the cap 4 with the other mark 42 from being mixed.
  • the UV Ultra Viol et
  • the mark 42 is marked on the cap 4 in the cap introduction step.
  • the cap 4 is made of, for example, a metal.
  • the hook support arm 17 (hook support portion) that supports the hook 19 shown in FIG. 1 and that can be engaged with the wiring board 2 of the multi-piece board 27 It is provided.
  • the mark 42 which is a recognition mark, is, for example, a serial number or a model number of the high-frequency module 1, and is composed of characters and symbols.
  • the mark 4 2 is attached to the surface 4 a of the cap 4.
  • the mark 42 is dried by UV. After drying, the appearance of the mark 42 is inspected by pattern recognition, and the caps 4 having the non-defective marks 42 are selected.
  • the cap mounting device 44 includes an XY table 45 supporting the multi-piece substrate 27, a mounting unit 46 for mounting the cap, and a multi-piece substrate 27 mounted on the XY table 45.
  • a plurality of hook holes 27c (see Fig. 15 (b)), which are recognition points, a recognition camera 47 for imaging the hook holes 27c, and an alignment station 48 for disposing the cap 4 at an angle. Consists of
  • the mounting unit 46 includes a suction collet 46a capable of holding the cap 4 by suction, a first cylinder 46b and a first panel 46c for vertically moving the suction collet 46a, A first slider 46 d to guide the vertical movement of the suction collet 46 a, and a key
  • the pusher 46 i that presses the cap 4 when inserting the cap, the second cylinder 46 e and the second panel 46 f that moves the pusher 46 i up and down, and the vertical movement of the pusher 46 i
  • a second slider 46 g for guiding is provided.
  • the alignment station 48 includes an inclined main jig 48 a for supporting the cap 4 at a predetermined angle and a cap 4 when the cap 4 is inclined and supported by the inclined main jig 48 a.
  • An auxiliary tilting jig 48 b is provided to guide around.
  • the suction collet 46 a When the cap 4 is suction-held from the inclined main jig 48 a by the suction collet 46 a, the suction collet is inclined at the same angle as the inclination angle of the cap 4 at the inclined main jig 48 a.
  • the suction surface 46 j of the suction collet 46 a is formed at the same angle as the angle of the support surface of the main tilting jig 48 a so that the suction collet 46 a can be tilted and held.
  • the multi-cavity substrate 27 is placed on the XY table 45, and thereafter, the recognition An image of the hook hole 27 c of the multi-piece substrate 27 shown in) is detected and its position is detected.
  • the cap 4 determined to be non-defective is supported by being inclined at a predetermined angle by the inclination main jig 48 a of the alignment station 48 of the cap mounting device 44. After that, the cap 4 is held by the suction collet 46 a of the mounting unit 46 while the cap 4 is kept inclined.
  • one of the two hook support arms 17 opposed to each other on the cap 4 and one of the hook support arms 1 ⁇ ⁇ ⁇ ⁇ arranged on the lower side due to the inclination is mounted on the XY table 45 with a large number of pieces.
  • the cap 4 is moved together with the mounting unit 46 so as to be placed on a desired hook hole 27 c of the substrate 27.
  • the hook supporting arm 17 arranged at the lower side due to the inclination of the two hook supporting arms 17 facing the cap 4 is shown in FIG.
  • FIG. 7 (b) of the two hook holes 27c to be inserted, insert into the hook hole 27c on the side where the adjacent cap 4 is not attached.
  • the corresponding hook support arm 17 (here the hook support arm 1 on the A side) is inserted into the hook hole 27 c on the side where the cap 4 is not attached.
  • the suction collet 46a is lowered by the first cylinder 46b on the A side of 46, and the hook 19 of the hook support arm 17 is hooked up by the inclination of the cap 4. Insert at an angle to c.
  • the hook support arm 17 when the hook support arm 17 is inserted, the hook claw 18 of the hook 19 does not come into contact with the hook hole 27 c, thereby preventing damage to the vicinity of the hook hole 27 c in the multi-piece board 27. As a result, the yield and quality of the multi-piece substrate 27 can be improved.
  • the wiring board 2 is inserted into the hook support arm 17 on one side (A side) inserted into the hook hole 27c on the side where the adjacent cap 4 is not attached.
  • the hook support arm 17 on the A side by moving the width 46 k (moving the wiring board 2 of the multi-piece board 27 by moving the XY table 45 from the B side to the A side and moving the set value) Load.
  • the radius is set within the elastic range. It is possible to make it.
  • the radius of the hook support arm 17 on the A side increases the distance between the two hook support arms 17 on the cap 4, and as a result, the hook claw on the hook 19 on the hook support arm 17 on the A side 18 (see FIG. 1) engages with the hooked portion 16 of the wiring board 2 and, as shown in FIG. 18 (b), the hook support arm 17 on the B side (the other side) 17 Are arranged on the other hook holes 27 c of the multi-piece substrate 27.
  • the yield and quality of the multi-piece substrate 27 can be improved.
  • the load applied to the A-side hook support arm 17 by the width adjustment 46 k of the wiring board 2 of the multi-piece board 27 is released, whereby the A-side hook support arm 1 is released.
  • the hook 19 of 7 and the hook 19 of the hook support arm 17 on the B side are engaged with the hooks 16 on both sides of the wiring board 2, respectively.
  • the mounting (attachment) of the multi-piece board 27 of the cap 4 to the wiring board 2 can be completed, and therefore, the multi-piece board of the cap 4 can be completed.
  • Automatic mounting on 27 can be performed easily.
  • the wiring board 2 on which the chip component 22 and the semiconductor pellet 21 are mounted can be covered with the cap 4.
  • the cap 4 is The problem of rattling of step 4 can be eliminated.
  • sealing with the cap 4 can be performed on an integrated assembly line using the multi-cavity substrate 27, mass production efficiency can be improved.
  • the number of steps can be significantly reduced, and a washing step for dirt such as flux can be omitted.
  • the suction collet 46a and the pusher 46i are raised to the original position by using the first slider 46d and the second slider 46g as guides, and returned to their original positions. Further, the mounting unit 46 is moved to the alignment station 48 to complete the cap insertion process.
  • step S11 the board division of step S11 shown in FIG. 3 is performed, and the multi-piece board 27 is divided into individual wiring boards 2 which are individual boards, thereby obtaining a structure as shown in FIG. 4 (h).
  • Each high-frequency module is in the form of 1.
  • step S12 the characteristic selection shown in step S12 is performed to obtain the electrical characteristics of each high-frequency module 1, and the high-frequency module 1 is selected based on the result.
  • module characteristics fluctuate due to variations in the wiring pattern conductor resistance of the ceramic substrate, that is, the wiring substrate 2, variations in the capacitance between the wiring patterns, and variations in the characteristics of the semiconductor pellet 21. Therefore, in the characteristic selection process, the electrical characteristics of the wiring board 2 in the high-frequency module 1 are monitored. Therefore, in assembling the high-frequency module 1, the characteristics of the semiconductor pellet 21 are classified and used in advance. Assembling is performed by selecting the constants of chip components 22 such as a chip capacitor and a chip resistor that are optimal for the combination of the wiring board 2 and the semiconductor pellet 21.
  • the high-frequency module 1 is manufactured.
  • the characteristics can be within an acceptable range, and as a result, a high-quality and stable high-frequency module 1 can be assembled. You.
  • FIG. 21 shows an example of the relationship between the frequency and the output (Pout) in the characteristics of the wiring board 2 of the high-frequency module 1.
  • the output Q (W) in Fig. 21 is the threshold for the pass / fail of the output of the high-frequency module 1
  • the output in the case of the first sample 50 of the high-frequency module 1, the output is sufficiently acceptable in the used frequency band 49. It becomes a good product as the high-frequency module 1.
  • the output in the case of the second sample 51, in the used frequency band 49, the output passes only in about half the area (the lower frequency side area in the used frequency band 49), and the output passes 52, and the remaining about half area In the (higher frequency range in the used frequency band 49), the output failed 53, resulting in a defective high-frequency module 1.
  • Fig. 22 shows an example of the grade classification of the semiconductor pellet 21.
  • the automatic sorting jig-packing machine is used for each semiconductor pellet. Shows the result of grade classification.
  • C iss represents capacitance
  • I dss represents leakage current
  • V th represents threshold voltage.
  • three semiconductors of grades ⁇ ⁇ ⁇ 3, 4 and 8 are shown.
  • the optimal circuit constants can be set by using a combination of pellets 21.
  • step S13 shown in FIG. 3 is performed.
  • a plurality of the selected high-frequency modules 1 are taped, wound and stored on a reel 43 shown in FIG. 4 (i).
  • the productivity is approximately three times that of the conventional assembling method. Further, a price reduction of 50% can be realized.
  • the present invention is not limited to the first and second embodiments of the invention, and the gist thereof is described. It is needless to say that various changes can be made without departing from the scope.
  • the characteristic selection step of the second embodiment the electrical characteristics of the wiring board 2 are monitored, the characteristics of the semiconductor pellet 21 are classified in advance, and the wiring substrate 2 and the semiconductor pellet used are classified.
  • the chip component may be obtained by exchanging 22 or the like.
  • the semiconductor pellet 21 described in the above embodiment may be obtained from a silicon semiconductor wafer, or may be obtained from a gallium or arsenic semiconductor wafer. Further, SOI, GeSi, TFT (Thin Film Transistor) and the like may be used.
  • the method of manufacturing a semiconductor device according to the present invention is applied to a general module product in which chip components such as chip capacitors and chip resistors and a semiconductor pellet formed by bare chip mounting are mounted and assembled using a multi-cavity substrate. It is suitable for the manufacturing method of small-sized portable electronic devices such as mobile phones, and especially suitable for high-frequency modules (high-frequency power amplifiers) mounted on thin portable electronic devices. is there.

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Abstract

A method for manufacturing a semiconductor device, the number of steps of which is reduced and which contributes to rationalization of the production line. A high-frequency module is produced by mounting chip components (22) and semiconductor pellets (21) on a wiring board (2) of an inspected multiple-block board (27). A wiring board (2) of a block which is judged to be defective at the inspection of the multiple-block board (27) is marked with a defect mark (2e). In the assembling steps after the marking, the defect mark (2e) is recognized and the work on the wiring board (2) marked with the defect mark (2e) is omitted, thereby rationalizing the production line.

Description

明 細 書 半導体装置の製造方法 技術分野  Description Semiconductor device manufacturing method Technical field
本発明は、 半導体製造技術に関し、 特に、 高周波モジュール （高周波電力増幅 装置） の製造方法に適用して有効な技術に関する。 背景技術  The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique that is effective when applied to a method for manufacturing a high-frequency module (high-frequency power amplifier). Background art
チップコンデンサやチップ抵抗などの表面実装形のチップ部品と、 ベアチップ 実装用の半導体ペレヅ トとを実装した高周波モジュール （R Fモジュールまたは R Fパワーモジュールともいう） と呼ばれる高周波電力増幅装置については、 例 えば、 特開平 1 0— 1 2 8 0 8号公報 （沼波） にその記載があり、 そこには、 高 周波モジユールの構造と電気的特性および複数個の高周波モジュールを一括して 組み立てるための多数個取り基板の構造などが記載されている。  For example, a high-frequency power amplifying device called a high-frequency module (also referred to as an RF module or an RF power module) in which surface-mounted chip components such as a chip capacitor and a chip resistor and a semiconductor pellet for bare chip mounting are mounted, for example, Japanese Patent Application Laid-Open No. H10-128808 (Numanami) describes the structure and electrical characteristics of a high-frequency module and a large number of individual units for assembling a plurality of high-frequency modules collectively. It describes the structure of the substrate and the like.
また、 ハイブリ ッ ド I C ( Integrated C i rcui t) におけるキャップの装着方法 については、 例えば、 特開平 6— 3 0 2 7 0 7号公報 （森住など） にその記載が あり、 そこには、 個片化された基板に対してのキャ ップの装着方法が記載されて いる。  A method of mounting a cap on a hybrid IC (Integrated Circuit) is described in, for example, Japanese Patent Application Laid-Open No. Hei 6-307207 (Morizumi). It describes how to attach caps to singulated substrates.
なお、 特開平 1 0— 1 2 8 0 8号公報には、 キャップに付す文字や記号などの マークについての記載はなく、 さらに、 多数個取り基板へのキャップの詳細取り 付け方法、 チップ部品 （電子部品） および半導体ペレッ トの搭載方法および多数 個取り基板への半田印刷や半田ポッティ ング方法などの組み立て技術についての 記載もない。  Note that Japanese Patent Application Laid-Open No. H10-12808 does not describe marks such as letters and symbols attached to the cap, and further describes a method of attaching the cap to the multi-piece board in detail, a chip component ( There is no description of mounting techniques such as electronic components) and semiconductor pellets, and solder printing and solder potting methods on multi-cavity boards.
また、 特開平 6— 3 0 2 7 0 7号公報 （森住など） には、 多数個取り基板に対 してのキヤップの装着方法は記載されていない。  In addition, Japanese Patent Application Laid-Open No. Hei 6-320707 (Morizumi, etc.) does not describe a method of mounting a cap on a multi-cavity substrate.
本発明の目的は、 製造工程の削減と製造ラインの合理化を図る半導体装置の製 造方法を提供することにある。  An object of the present invention is to provide a method for manufacturing a semiconductor device which reduces the number of manufacturing steps and rationalizes a manufacturing line.
また、 本発明の他の目的は、 製造コス トの低減を図る半導体装置の製造方法を 提供することにある。 Another object of the present invention is to provide a method of manufacturing a semiconductor device which aims to reduce manufacturing costs. To provide.
さらに、 本発明の他の目的は、 材料コス トの低減を図る半導体装置の製造方法 を提供することにある。  Still another object of the present invention is to provide a method for manufacturing a semiconductor device which reduces material costs.
本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述および添 付図面から明らかになるであろう。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention
本発明の半導体装置の製造方法は、 受動素子用チップおよび能動素子用チップ を配線基板に配置して前記受動素子用チップおよび前記能動素子用チップを前記 配線基板に実装する工程と、 表面に認識マークが付されたキャップを前記配線基 板に取り付けて前記キヤップによって前記受動素子用チップおよび前記能動素子 用チップを覆う工程とを有するものである。  A method for manufacturing a semiconductor device according to the present invention includes the steps of: disposing a passive element chip and an active element chip on a wiring board and mounting the passive element chip and the active element chip on the wiring board; Attaching a cap with a mark to the wiring board, and covering the passive element chip and the active element chip with the cap.
さらに、 本発明の半導体装置の製造方法は、 受動素子用チップおよび能動素子 用チップを配線基板に配置して前記受動素子用チッブおよび前記能動素子用チッ プを前記配線基板に実装する工程と、 表面に認識マークが付されたキャップの前 記認識マークの検査を行い、 前記検査後、 良品のキャップを前記配線基板に取り 付けて前記キヤップによって前記受動素子用チップおよび前記能動素子用チップ を覆う工程とを有するものである。  Further, the method of manufacturing a semiconductor device according to the present invention includes the steps of: disposing a passive element chip and an active element chip on a wiring board and mounting the passive element chip and the active element chip on the wiring board; The above-mentioned recognition mark of the cap having the recognition mark on the surface is inspected, and after the inspection, a non-defective product cap is attached to the wiring board, and the passive element chip and the active element chip are covered by the cap. And a process.
本発明によれば、 認識マークが付されたキヤップの前記認識マークの検査を行 つた後に良品のキャップを配線基板に取り付けるため、 マーク無し、 マーク不良 もしくは他のマークのキャップなど不良品キャップの取り付けを防ぐことができ る。  According to the present invention, a non-defective mark, a defective mark, or a cap of a defective mark such as a cap of another mark is attached because a non-defective cap is attached to the wiring board after inspecting the recognition mark of the cap having the recognition mark. Can be prevented.
これにより、 認識マークに関する不良品キャップが取り付けられることはない ため、 製造ライ ンの合理化を図ることができる。  As a result, the defective cap for the recognition mark is not attached, so that the production line can be streamlined.
また、 本発明の半導体装置の製造方法は、 複数の配線基板が形成された多数個 取り基板の配線基板に受動素子用チップおよび能動素子用チップを実装して組み 立てられるものであり、 検査済みの前記多数個取り基板の前記配線基板に前記受 動素子用チップおよび前記能動素子用チップを配置して前記受動素子用チップぉ よび前記能動素子用チップを良品の配線基板に実装する工程と、 キヤップを前記 良品の配線基板のみに取り付けて前記キヤップによって前記受動素子用チップぉ よび前記能動素子用チップを覆う工程とを有するものである。 Further, the method of manufacturing a semiconductor device of the present invention is a method of mounting a passive element chip and an active element chip on a wiring board of a multi-piece board on which a plurality of wiring boards are formed. Arranging the passive element chip and the active element chip on the wiring board of the multi-piece substrate and mounting the passive element chip and the active element chip on a non-defective wiring board; The cap Covering the passive element chip and the active element chip with the cap by attaching only to a non-defective wiring board.
本発明によれば、 検査済みの多数個取り基板の配線基板のみに受動素子用チッ プおよび能動素子用チップを実装することにより、 半導体装置の製造工程におい てこの不良箇所への作業を省略することができる。  According to the present invention, a passive element chip and an active element chip are mounted only on a wiring board of a multi-cavity board that has been inspected, thereby omitting work on this defective portion in a semiconductor device manufacturing process. be able to.
これにより、 製造工程の削減と製造ライ ンの合理化を図ることができる。 その結果、 半導体装置の製造コス トを低減できる。  This can reduce the number of manufacturing processes and streamline manufacturing lines. As a result, the manufacturing cost of the semiconductor device can be reduced.
なお、 本発明の半導体装置の製造方法は、 配線基板に受動素子用チップおよび 能動素子用チップを実装して組み立てられるものであり、 前記配線基板の受動素 子用チップ用端子に半田を印刷する工程と、 前記半田印刷後、 前記配線基板の凹 部に半田をポッティ ングによって塗布する工程と、 前記受動素子用チップを前記 配線基板に配置する工程と、 前記能動素子用チップを前記配線基板の前記凹部に 配置する工程と、 半田リフローを行って前記受動素子用チップおよび前記能動素 子用チップを前記配線基板に半田接続によって実装する工程とを有するものであ る。  In the method of manufacturing a semiconductor device according to the present invention, a passive element chip and an active element chip are mounted on a wiring board and assembled, and solder is printed on the passive element chip terminals of the wiring board. After the solder printing, a step of applying solder to the concave portion of the wiring board by potting, a step of disposing the passive element chip on the wiring board, and a step of attaching the active element chip to the wiring board. Arranging the passive element chip and the active element chip on the wiring board by solder connection by performing solder reflow.
本発明によれば、 配線基板の受動素子用チップ用端子に半田を印刷し、 その後 、 配線基板の凹部に半田をポッティ ングによって塗布することにより、 半田印刷 を先に行うため、 半田印刷時の半田マスクが半田によって汚れることを防止でき る。  According to the present invention, solder is printed on the passive element chip terminals of the wiring board, and then the solder is applied to the recesses of the wiring board by potting, so that the solder printing is performed first. It is possible to prevent the solder mask from being stained by the solder.
また、 本発明の半導体装置の製造方法は、 配線基板に受動素子用チップおよび 能動素子用チップを実装して組み立てられるものであり、 前記受動素子用チップ を前記配線基板に配置する工程と、 前記受動素子用チップ配置後、 前記能動素子 用チップを前記配線基板の凹部に配置する工程と、 前記受動素子用チップおよび 前記能動素子用チップを前記配線基板に半田接続によって実装する工程とを有す るものである。  Further, the method of manufacturing a semiconductor device according to the present invention includes a step of mounting a passive element chip and an active element chip on a wiring board, and assembling the passive element chip on the wiring board. After disposing the passive element chip, the method includes a step of disposing the active element chip in the recess of the wiring board, and a step of mounting the passive element chip and the active element chip on the wiring board by soldering. Things.
さらに、 本発明の半導体装置の製造方法は、 配線基板に受動素子用チップおよ び能動素子用チップを実装して組み立てられるものであり、 複数の前記配線基板 が分割用溝部によって区画形成された多数個取り基板の前記配線基板に前記受動 素子用チップを配置する工程と、 前記配線基板の凹部に前記能動素子用チップを 配置する工程と、 前記受動素子用チップおよび前記能動素子用チップを前記配線 基板に半田接続によって実装する工程と、 複数の前記配線基板の凹部に対してポ ッティ ングにより前記分割用溝部を避けて前記封止用樹脂を塗布して前記能動素 子用チップを樹脂封止する工程とを有するものである。 Further, in the method of manufacturing a semiconductor device according to the present invention, the passive element chip and the active element chip are mounted on a wiring board and assembled, and the plurality of wiring boards are defined by dividing grooves. Disposing the passive element chip on the wiring board of the multi-cavity board; and placing the active element chip in a recess of the wiring board. Disposing; mounting the passive element chip and the active element chip on the wiring board by soldering; and avoiding the dividing groove by potting a plurality of recesses of the wiring board. Applying the sealing resin and sealing the active element chip with resin.
また、 本発明の半導体装置の製造方法は、 配線基板に受動素子用チップおよび 能動素子用チップを実装して組み立てられるものであり、 複数の前記配線基板が 形成された多数個取り基板の前記配線基板に前記受動素子用チップおよび前記能 動素子用チップを配置して前記受動素子用チップおよび前記能動素子用チップを 前記配線基板に実装する工程と、 前記配線基板に係合可能なフックを支持するフ ック支持部が対向して設けられたキヤップの一方の前記フック支持部を前記多数 個取り基板のフック孔に斜めに挿入して前記キヤップを前記多数個取り基板に取 り付ける工程とを有し、 前記キヤップによつて前記多数個取り基板の前記配線基 板上の前記受動素子用チッブおよび前記能動素子用チップを覆うものである。 なお、 本発明の半導体装置の製造方法は、 配線基板に受動素子用チップおよび 能動素子用チップを実装して組み立てられるものであり、 選別された前記配線基 板に前記受動素子用チップを配置する工程と、 選別された前記能動素子用チップ を前記配線基板の凹部に配置する工程と、 前記受動素子用チップおよび前記能動 素子用チップを前記配線基板に半田接続によって実装する工程とを有し、 前記半 導体装置の特性が許容範囲に入るようにそれそれに選別された前記配線基板と前 記能動素子用チップとを組み合わせて実装するものである。 図面の簡単な説明  Further, the method of manufacturing a semiconductor device according to the present invention is characterized in that a passive element chip and an active element chip are mounted on a wiring board and assembled, and the wiring of the multi-piece board on which a plurality of the wiring boards are formed is provided. Disposing the passive element chip and the active element chip on a substrate and mounting the passive element chip and the active element chip on the wiring board; and supporting a hook engageable with the wiring board. Attaching the cap to the multi-piece substrate by obliquely inserting one of the hook supports of the cap provided with the hook support portions facing each other into a hook hole of the multi-piece board. The cap for covering the chip for the passive element and the chip for the active element on the wiring board of the multi-piece substrate. In the method of manufacturing a semiconductor device according to the present invention, the passive element chip and the active element chip are mounted on a wiring board and assembled, and the passive element chip is arranged on the selected wiring board. A step of arranging the selected active element chips in the recesses of the wiring board; and mounting the passive element chips and the active element chips on the wiring board by soldering. The above-mentioned wiring board and the active element chip are mounted in combination so that the characteristics of the semiconductor device fall within an allowable range. BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明の半導体装置の製造方法によって組み立てられる高周波モジユー ルの構造の実施の形態の一例を示す図であり、 （a ) は斜視図、 （b ) は断面図 、 図 2は図 1 に示す高周波モジュールの構造を示す底面図、 図 3は図 1 に示す高 周波モジュールの製造方法における組み立て手順の一例を示す製造プロセスフ口 —図、 図 4 ( a ) , ( b ) , ( c )， （ d )， ( e ) , ( f ) , ( g ) , ( h ) , ( i ) は図 8に 示す主要工程に対応した配線基板および高周波モジュールの構造の一例を示す断 面図、 側面図および斜視図、 図 5は図 1 に示す高周波モジュールの製造の際に用 いられる基板とその不良マーク配線基板の構造の一例を示す図であり、 （ a ) は 多数個取り基板の斜視図、 （b ) は部品搭載検査時の不良マーク配線基板の平面 図、 （ c ) はリ フ口一後の不良マーク配線基板の平面図、 （d ) はワイヤボンデ ィ ング後の不良マーク配線基板の平面図、 図 6は本発明の半導体装置の製造方法 の半田ポッティ ング工程におけるノズルの移動軌跡の実施の形態の一例を示す図 であり、 （a ) は配線基板における移動軌跡を示す平面図、 （b ) は多数個取り 基板における移動軌跡を示す斜視図、 図 7は本発明の半導体装置の製造方法の半 田印刷工程と半田ポッティ ング工程における基板の構造の実施の形態の一例を示 す図であり、 （ a ) は半田形成前の多数個取り基板の平面図、 （b ) は半田形成 前の配線基板の平面図、 （ c ) は半田印刷 ' 半田ポッティ ング後の配線基板の平 面図、 図 8は本発明の半導体装置の製造方法の部品搭載工程で用いられる部品搭 載装置の構造の実施の形態の一例を示す図であり、 （a ) は外観斜視図、 （b ) は構成プロック図、 図 9は本発明の半導体装置の製造方法のペレツ ト搭載工程で 用いられるペレツ ト搭載装置の構造の実施の形態の一例を示す図であり、 （a ) は外観斜視図、 （b ) は構成ブロック図、 図 1 0は本発明の半導体装置の製造方 法の部品搭載 ' ペレツ ト搭載工程における配線基板の構造の実施の形態の一例を 示す図であり、 （a ) は部品搭載後の基板平面図、 （b ) はペレッ ト搭載後の基 板平面図、 図 1 1は本発明の半導体装置の製造方法の自動外観検査工程における 部品位置検出時の基板の構造の実施の形態の一例を示す図であり、 （a ) は多数 個取り基板の平面図、 （ b ) は配線基板の平面図、 図 1 2は本発明の半導体装置 の製造方法のレジン塗布工程における基板の構造の実施の形態の一例を示す図で あり、 （ a ) は多数個取り基板の平面図、 （ b ) は配線基板の平面図、 図 1 3は 本発明の半導体装置の製造方法のキヤップ揷入工程で用いられるキヤップの構造 の実施の形態の一例を示す図であり、 （a ) は平面図、 （b ) , ( c ) は側面図、 図 1 4は図 1 3に示すキヤップにマークが付された状態の実施の形態の一例を示 す斜視図、 図 1 5は本発明の半導体装置の製造方法のキャップ挿入工程における 多数個取り基板のフック孔の認識方法の一例を示す図であり、 （a ) は認識状態 を示す正面図、 （b ) は多数個取り基板のフック孔を示す平面図、 図 1 6は本発 明の半導体装置の製造方法のキヤップ揷入工程におけるキヤップ移載方法の実施 の形態の一例を示す移載原理図、 図 1 7は本発明の半導体装置の製造方法のキヤ ップ挿入工程におけるキヤップ挿入方法の実施の形態の一例を示す図であり、 （ a ) は挿入原理図、 （b ) は （a ) のキヤップ揷入状態図、 図 1 8は本発明の半 導体装置の製造方法のキヤップ挿入工程におけるキヤップ装着方法の実施の形態 の一例を示す図であり、 （a ) は装着原理図、 （b ) は （ a ) のキャップ拡大断 面図、 （ c ) は （b ) の C部の拡大部分断面図、 図 1 9は本発明の半導体装置の 製造方法のキヤップ挿入工程におけるキヤップ揷入後の状態の一例を示す図であ り、 （a ) は正面図、 （b ) は配線基板の拡大部分断面図、 図 2 0は本発明の半 導体装置の製造方法のキヤップ挿入工程におけるキヤップ揷入後のキヤップ装着 装置の動作の一例を示す動作原理図、 図 2 1は本発明の半導体装置の製造方法の 特性選別工程における特性検査結果の一例を示す出力特性図、 図 2 2は本発明の 半導体装置の製造方法のペレッ ト特性検査の検査結果の一例を示すペレッ トグレ —ド分け図である。 発明を実施するための最良の形態 FIGS. 1A and 1B are views showing an example of an embodiment of the structure of a high-frequency module assembled by the method for manufacturing a semiconductor device according to the present invention, wherein FIG. 1A is a perspective view, FIG. 1B is a cross-sectional view, and FIG. Fig. 3 is a bottom view showing the structure of the high-frequency module shown in Fig. 3, and Fig. 3 is a manufacturing process diagram showing an example of the assembly procedure in the method for manufacturing the high-frequency module shown in Fig. 1-Fig. 4 (a), (b), (c) , (D), (e), (f), (g), (h), and (i) are cross-sectional views and side views showing an example of the structure of a wiring board and a high-frequency module corresponding to the main steps shown in FIG. Figure and perspective view, and Figure 5 is used when manufacturing the high-frequency module shown in Figure 1. FIGS. 3A and 3B are diagrams showing an example of the structure of a substrate to be inserted and a defective mark wiring substrate, (a) is a perspective view of a multi-piece substrate, (b) is a plan view of the defective mark wiring substrate during component mounting inspection, and (c). ) Is a plan view of the defective mark wiring board after the reflex opening, (d) is a plan view of the defective mark wiring board after wire bonding, and FIG. FIGS. 8A and 8B are diagrams illustrating an example of a movement trajectory of a nozzle according to an embodiment. FIG. 7A is a plan view illustrating a movement trajectory on a wiring board, FIG. 7B is a perspective view illustrating a movement trajectory on a multi-cavity board, and FIG. FIG. 3 is a view showing an example of an embodiment of a substrate structure in a solder printing step and a solder potting step of the method of manufacturing a semiconductor device according to the present invention, wherein (a) is a plan view of a multi-piece substrate before solder formation; (B) is the wiring board before solder formation FIG. 8C is a plan view of the wiring board after solder printing and solder potting. FIG. 8 is an embodiment of the structure of the component mounting apparatus used in the component mounting step of the semiconductor device manufacturing method according to the present invention. FIGS. 9A and 9B are views showing an example of the structure, wherein FIG. 9A is an external perspective view, FIG. 9B is a block diagram of the configuration, and FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing an example of an embodiment, in which (a) is an external perspective view, (b) is a configuration block diagram, and FIG. 10 is a diagram showing a method of manufacturing a semiconductor device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing an example of an embodiment of a structure of a substrate. (A) is a plan view of a substrate after mounting components, (b) is a plan view of a substrate after mounting a pellet, and FIG. Of the board structure at the time of component position detection in the automatic appearance inspection process of 1A is a plan view of a multi-piece substrate, FIG. 1B is a plan view of a wiring board, and FIG. 12 is a view of a resin coating step in a method of manufacturing a semiconductor device according to the present invention. FIGS. 3A and 3B are diagrams illustrating an example of an embodiment of a substrate structure, in which FIG. 3A is a plan view of a multi-piece substrate, FIG. 3B is a plan view of a wiring substrate, and FIG. FIGS. 3A and 3B are diagrams illustrating an example of an embodiment of a structure of a cap used in a cap insertion step, in which FIG. 1A is a plan view, FIGS. 1B and 1C are side views, and FIG. FIG. 15 shows an example of a method of recognizing hook holes of a multi-piece substrate in a cap insertion step of a method of manufacturing a semiconductor device according to the present invention. (A) is a front view showing a recognition state, and (b) is a hook hole of a multi-piece board. Plan view, the implementation of cap transferring method in cap 揷入 process of the manufacturing method of FIG. 1 6 This onset Ming semiconductor device FIG. 17 is a diagram showing an example of an embodiment of a cap insertion method in a cap insertion step of a method of manufacturing a semiconductor device according to the present invention, and FIG. FIG. 18B is a principle diagram, FIG. 18B is a diagram showing the state of the cap inserted in FIG. 17A, and FIG. (A) is a mounting principle diagram, (b) is an enlarged sectional view of the cap of (a), (c) is an enlarged partial cross-sectional view of a portion C of (b), and FIG. 19 is a method of manufacturing a semiconductor device of the present invention. FIGS. 3A and 3B are views showing an example of a state after a cap is inserted in a cap insertion step of FIG. 1A, wherein FIG. 2A is a front view, FIG. 2B is an enlarged partial cross-sectional view of a wiring board, and FIG. An example of the operation of the cap mounting device after cap insertion in the cap insertion process of the manufacturing method is shown. Operation principle diagram, FIG. 21 is an output characteristic diagram showing an example of a characteristic inspection result in a characteristic selection step of the semiconductor device manufacturing method of the present invention, and FIG. 22 is a pellet characteristic inspection of the semiconductor device manufacturing method of the present invention. FIG. 14 is a diagram showing a pellet grade showing an example of an inspection result. BEST MODE FOR CARRYING OUT THE INVENTION
以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原 則として繰り返さない。  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless necessary.
また、 以下の実施の形態では便宜上、 複数の発明を 2つの実施の形態の中で説 明するが、 特に明示した場合を除き、 各ステップは全ての発明について必ずしも 必須のものではないことは言うまでもない。  In the following embodiments, a plurality of inventions will be described in two embodiments for the sake of convenience. However, it is needless to say that each step is not necessarily required for all inventions, unless otherwise specified. No.
さらに、 以下の実施の形態では便宜上その必要があるときは、 複数のセクショ ンまたは実施の形態に分割して説明するが、 特に明示した場合を除き、 それらは お互いに無関係なものではなく、 一方は他方の一部または全部の変形例、 詳細、 補足説明などの関係にある。  Further, in the following embodiments, when necessary for convenience, the description will be made by dividing into a plurality of sections or embodiments, but they are not unrelated to each other, unless otherwise specified. Is related to some or all of the other modifications, details, and supplementary explanations.
また、 以下の実施の形態において、 要素の数等 （個数、 数値、 量、 範囲等を含 む） に言及する場合、 特に明示した場合及び原理的に明らかに特定の数に限定さ れる場合などを除き、 その特定の数に限定されるものではなく、 特定の数以上で も以下でも良いものとする。  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), particularly when explicitly stated, and when clearly limited to a specific number in principle Except for, the number is not limited to the specific number, and may be more or less than the specific number.
さらに、 以下の実施の形態において、 その構成要素 （要素ステップなどを含む ) は、 特に明示した場合及び原理的に明らかに必須であると考えられる場合など を除き、 必ずしも必須のものではないことは言うまでもない。 Furthermore, in the following embodiments, the components (including the element steps, etc.) Needless to say,) is not necessarily required, unless otherwise specified and in cases where it is deemed essential in principle.
同様に、 以下の実施の形態において、 構成要素等の形状、 位置関係等に言及す るときは、 特に明示した場合及び原理的に明らかにそうでないと考えられる場合 などを除き、 実質的にその形状などに近似または類似するものなどを含むものと する。 このことは前記数値及び範囲についても同様である。  Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and in cases where it is considered in principle not to be the case, it is substantially the same. It shall include those that are similar or similar to the shape. This is the same for the above numerical values and ranges.
以下、 本発明の実施の形態を図面に基づいて詳細に説明する。 なお、 実施の形 態を説明するための全図において、 同一の機能を有する部材には同一の符号を付 し、 その繰り返しの説明は省略する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
本発明の実施の形態 1 を、 図 1、 図 2に示す半導体装置 （高周波モジュール 1 ) の構造を示す図、 図 3の高周波モジュール 1の組み立て手順を示す図、 図 4に 示す主要工程ごとの配線基板の断面図、 図 5に示す不良マーク配線基板の図を用 いて説明する。  FIGS. 1 and 2 show the structure of a semiconductor device (high-frequency module 1), FIG. 3 shows a procedure for assembling the high-frequency module 1, and FIG. This will be described with reference to the cross-sectional view of the wiring board and the drawing of the defective mark wiring board shown in FIG.
図 1、 図 2に示す本実施の形態 1の半導体装置の製造方法によって組み立てら れる半導体装置は、 高周波モジュール 1 と呼ばれる （高周波パワーモジュールと もいう） 高周波電力増幅装置であり、 板状の配線基板 2の主面 （上面） にキヤッ プ 4が重ねられ、 外観的には偏平な矩形体構造のものである。  The semiconductor device assembled by the method for manufacturing a semiconductor device according to the first embodiment shown in FIGS. 1 and 2 is a high-frequency power amplifier, which is called a high-frequency module 1 (also referred to as a high-frequency power module). The cap 4 is superimposed on the main surface (upper surface) of the substrate 2, and has a flat rectangular structure in appearance.
したがって、 主に携帯用電話などの小形の携帯用電子機器などに組み込まれる ものであり、 電界効果トランジス夕が形成されるとともにベアチップ実装される 能動部品である半導体ペレッ ト 2 1 (能動素子用チップ） と、 表面実装形のチッ プコンデンサやチップ抵抗などの電子部品 （面実装部品または面付け部品） であ るとともに受動部品であるチップ部品 2 2 (受動素子用チップ） とが配線基板 2 上に搭載 （混載） されている。  Therefore, semiconductor pellets 21 (active element chips), which are mainly incorporated in small portable electronic devices such as mobile phones, are active components that form field-effect transistors and are mounted on bare chips. ) And chip components 22 (passive element chips) that are both electronic components (surface-mounted or surface-mounted components) such as surface-mount type chip capacitors and chip resistors and passive components. (Mixed).
なお、 高周波モジュール 1は、 図 1 ( a ) に示すように、 キャップ 4の外周縁 が配線基板 2の外周縁に一致するか、 それよりも内側に位置するようになってお り、 さらに、 キャップ 4は、 金属板を矩形箱状に絞り成形して、 下面周縁に沿つ て突出した周壁 3を有する構造となっている。  In the high-frequency module 1, as shown in FIG. 1 (a), the outer edge of the cap 4 coincides with or is located inside the outer edge of the wiring board 2. The cap 4 has a structure in which a metal plate is drawn into a rectangular box shape and has a peripheral wall 3 protruding along the lower surface periphery.
また、 図 1 ( b ) に示すように、 キャップ 4には、 その両側中央の周壁 3から 下方に向けて突出するフック支持アーム （フック支持部） 1 7が対向して設けら れており、 さらに、 このフック支持アーム 1 7の先端側の内側には、 これも成形 によって形成された突出するフック爪 1 8が設けられている。 このフック爪 1 8 とフック支持アーム 1 7とによって弾性力を有した係止部であるフック 1 9が形 成されている。 Also, as shown in FIG. 1 (b), the cap 4 is provided with hook support arms (hook support portions) 17 protruding downward from the peripheral wall 3 at the center on both sides thereof. Further, inside the tip side of the hook support arm 17, a protruding hook claw 18 also formed by molding is provided. The hook 19 and the hook support arm 17 form a hook 19 which is a locking portion having elasticity.
なお、 キャップ 4の厚さは、 例えば、 0.1mm程度であり、 メ ッキレスの洋白 (ニッケルと銅と亜鉛の合金） や、 ニッケルメツキを施したリ ン青銅などによつ て形成され、 これにより、 半田との濡れ性を高めている。  The thickness of the cap 4 is, for example, about 0.1 mm, and is formed of a nickelless nickel silver (an alloy of nickel, copper, and zinc), a nickel-plated phosphor bronze, or the like. This enhances the wettability with the solder.
また、 配線基板 2の両側中央部には、 フ ック支持アーム 1 7が配置される窪み 1 5が形成されており、 この窪み 1 5の底には、 さらに一段凹んだ引っ掛かり部 1 6が形成され、 フック 1 9のフック爪 1 8がこの引っ掛かり部 1 6に係合され る。  At the center of both sides of the wiring board 2, there is formed a recess 15 in which the hook support arm 17 is disposed. At the bottom of the recess 15 is a further recessed hook 16. The hook claw 18 of the hook 19 is formed and is engaged with the hook portion 16.
なお、 窪み 1 5が形成されていることにより、 フック爪 1 8が引っ掛かり部 1 6に引っ掛かった状態では、 フック支持アーム 1 7が窪み 1 5より外側に突出す ることはない。  Since the recess 15 is formed, the hook support arm 17 does not protrude outside the recess 15 when the hook claw 18 is hooked on the hook portion 16.
また、 フック支持アーム 1 7が金属板によって形成されていることにより、 フ ヅク 1 9に弾性力を作用させることができる。 したがって、 キャップ 4の周壁 3 の先端が配線基板 2の主面に接触し、 かつ配線基板 2の裏面にフック爪 1 8が弾 力性を有して引っ掛かることにより、 キヤップ 4を配線基板 2に確実に固定する ことができる。  Further, since the hook support arm 17 is formed of a metal plate, an elastic force can be applied to the hook 19. Accordingly, the tip of the peripheral wall 3 of the cap 4 comes into contact with the main surface of the wiring board 2, and the hook 4 is elastically hooked on the back surface of the wiring board 2, so that the cap 4 is attached to the wiring board 2. It can be fixed securely.
その際、 フック 1 9は、 配線基板 2に弾性力を作用させていることにより、 キ ャップ 4を容易に取り外すこともできる。  At this time, since the hook 19 applies an elastic force to the wiring board 2, the cap 4 can be easily removed.
なお、 配線基板 2とキャップ 4との係止部については、 他の構造であってもよ い。  It should be noted that the locking portion between the wiring board 2 and the cap 4 may have another structure.
また、 図 2に示すように、 配線基板 2の裏面には、 複数の外部端子 5が設けら れており、 これらの外部端子 5は、 配線基板 2の裏面の長手方向の両側にそれそ れほぼ一定の間隔で配置され、 一方の列 （図 2に示す上側の列） には、 左から右 に向かって入力端子 （P i n) 6、 グラウン ド端子 （GND) 7、 グラウン ド端 子 （GND) 8およびゲートバイアス端子 （Vg) 9が設けられ、 かつ、 他方の 列 （図 2に示す下側の列） には、 左から右に向かって出力端子 （P o u t ) 1 0 、 グラウン ド端子 （ G N D ) 1 1、 グラウン ド端子 （ G N D ) 1 2および電源端 子 （Vd d) 1 3が設けられている。 Further, as shown in FIG. 2, a plurality of external terminals 5 are provided on the back surface of the wiring board 2, and these external terminals 5 are provided on both sides in the longitudinal direction of the back surface of the wiring board 2. They are arranged at almost constant intervals, and one row (upper row shown in Fig. 2) has, from left to right, an input terminal (P in) 6, a ground terminal (GND) 7, and a ground terminal ( GND) 8 and gate bias terminal (Vg) 9 are provided, and the other column (lower column shown in FIG. 2) has output terminals (P out) 10 from left to right. , A ground terminal (GND) 11, a ground terminal (GND) 12, and a power supply terminal (Vdd) 13 are provided.
さらに、 入力端子 6、 ゲートバイアス端子 9、 出力端子 1 0および電源端子 1 3に対応する配線基板 2の側面には、 図 1 (a) に示すように、 配線基板 2の表 面から裏面に至る箇所に端面スルーホール 2 0が設けられている。 これは、 高周 波モジュール 1をプリン ト配線基板などの実装基板に実装する際、 各外部端子 5 せ、 配線基板 2の裏面の電極部分と側面の端面スルーホール 2 0部分とで接続さ れて実装されることになり、 これにより、 高周波モジュール 1の確実な実装を行 うことができる。  Further, as shown in FIG. 1 (a), the side of the wiring board 2 corresponding to the input terminal 6, the gate bias terminal 9, the output terminal 10 and the power supply terminal 13 is arranged from the front side to the back side as shown in FIG. An end face through hole 20 is provided at every position. This is because when mounting the high-frequency module 1 on a mounting board such as a printed wiring board, each external terminal 5 is connected to the electrode portion on the back surface of the wiring board 2 and the through hole 20 on the side face of the side face. As a result, the high-frequency module 1 can be reliably mounted.
なお、 配線基板 2の裏面において 4つのグラウン ド端子 7 , 8 , 1 1 , 1 2を 区画するように延在する領域には、 高周波モジュール 1を実装する際使用される 実装用接合材 （例えば、 半田） に濡れない材料によって形成されたレジス ト膜 1 4が設けられている。  Note that, on the rear surface of the wiring board 2, a region extending so as to partition the four ground terminals 7, 8, 11 and 12 is provided with a mounting bonding material used when mounting the high-frequency module 1 (for example, , Solder) is provided with a resist film 14 made of a material that does not wet.
また、 高周波モジュール 1では、 図 1 (b) に示すように、 配線基板 2の表面 にチップ部品 2 2が搭載され、 かつ配線基板 2の表面に形成されたキヤビティ部 である凹部 2 aに半導体ペレッ ト 2 1が半田接続部 2 6を介して搭載されている さらに、 チップ部品 2 2は、 半田フィ レッ ト 2 5を形成して配線基板 2の図 5 ( b ) に示すチップ部品用電極 2 b (受動素子用チップ用端子） と半田接続して おり、 一方、 半導体ペレッ ト 2 1は、 その表面電極であるパッ ドが金線などのヮ ィャ 24によって配線基板 2の基板側端子 2 iと接続されている。  In the high-frequency module 1, as shown in FIG. 1 (b), the chip component 22 is mounted on the surface of the wiring board 2, and the recess 2a which is a cavity formed on the surface of the wiring board 2 is provided in the recess 2a. The pellet 21 is mounted via the solder connection part 26. Further, the chip part 22 is formed with a solder fillet 25 to form an electrode for the chip part of the wiring board 2 shown in FIG. 5 (b). 2 b (terminal for a chip for passive element) is soldered. On the other hand, in the semiconductor pellet 21, the pad which is the surface electrode is connected to the board side terminal of the wiring board 2 by a wire 24 such as a gold wire. 2 Connected to i.
なお、 半導体ペレッ ト 2 1 とワイヤ 2 4は、 エポキシ樹脂などの封止用樹脂 2 3によって樹脂封止されている。  The semiconductor pellet 21 and the wires 24 are resin-sealed with a sealing resin 23 such as an epoxy resin.
また、 高周波モジュール 1の大きさは、 例えば、 幅 8 mm、 長さ 1 2.3mm、 高さ 1.8mmである。  The size of the high-frequency module 1 is, for example, 8 mm in width, 12.3 mm in length, and 1.8 mm in height.
次に、 図 1から図 5を用いて、 本実施の形態 1の高周波モジュール 1 (半導体 装置） の製造方法の概略と、 配線基板 2に付される不良マーク 2 eとについて説 明する。  Next, an outline of a method of manufacturing the high-frequency module 1 (semiconductor device) according to the first embodiment and a defect mark 2e attached to the wiring board 2 will be described with reference to FIGS.
高周波モジュール 1は、 図 3に示す組み立て手順 （製造プロセス） によって組 み立てられるものであり、 それぞれの工程は、 チップ部品搭載用の半田印刷 （ス テツプ S 1、 図 4 ( a ) ) 、 半導体ペレッ ト搭載用の半田ポッティ ング （ステツ プ S 2、 図 4 ( b ) ) 、 チップ部品 2 2の搭載である部品搭載 （ステップ S 3、 図 4 ( c ) ) 、 半導体ペレッ ト 2 1の搭載であるペレッ ト搭載 （ステップ S 4、 図 4 ( d ) ) 、 半田のリフロー （洗浄を含む （ステップ S 5 ) ) 、 リフロ一後の 自動外観検査 （ステップ S 6 ) 、 ワイヤボンディ ング （ステップ S 7、 図 4 ( e ) ) 、 ワイヤボンディ ング後の外観検査 （ステップ S 8 ) 、 封止用樹脂 2 3 (レ ジン） の塗布であるレジン塗布 （ステップ S 9、 図 4 ( f ) ) 、 キヤップ揷入 （ マーク付けを含む （ステップ S 1 0 ) 、 図 4 ( g ) ) 、 多数個取り基板 2 7を個 片基板である配線基板 2に分割する基板分割 （ステップ S I 1 ) 、 高周波モジュ —ル 1の特性選別 （ステップ S 1 2、 図 4 ( h ) ) および高周波モジュール 1の テーピング （ステップ S 1 3、 図 4 ( i ) ) となる。 The high-frequency module 1 is assembled by the assembly procedure (manufacturing process) shown in Fig. 3. Each process consists of solder printing for mounting chip components (Step S1, Figure 4 (a)) and solder potting for mounting semiconductor pellets (Step S2, Figure 4 ( b)), component mounting for mounting chip components 22 (Step S3, FIG. 4 (c)), mounting of pellets for mounting semiconductor pellet 21 (Step S4, FIG. 4 (d)), Solder reflow (including cleaning (Step S5)), automatic appearance inspection after reflow (Step S6), wire bonding (Step S7, Fig. 4 (e)), appearance inspection after wire bonding (Step S5) Step S 8), resin application (step S 9, FIG. 4 (f)) which is an application of the sealing resin 23 (resin), cap insertion (including marking (step S 10), FIG. 4) (g)), Multi-cavity board 27 is divided into wiring board 2 which is a single board Substrate division (Step SI 1) that the high-frequency module - a characteristic evaluation of the Le 1 (Step S 1 2, Fig. 4 (h)) and the high frequency module 1 of the taping (Step S 1 3, FIG. 4 (i)).
そこで、 前記各工程のうち、 ステップ S 1の半田印刷〜ステップ S 1 0のキヤ ップ挿入 （マーク付けを含む） までは、 複数の配線基板 2が形成された多数個取 り基板 2 7の状態で各処理を行い、 その後、 ステップ S 1 1で多数個取り基板 2 7を各個片基板である配線基板 2に分割する基板分割を行い、 その結果、 ステツ プ S 1 2の特性選別とステップ S 1 3のテーピングは、 配線基板 2を有した高周 波モジュール 1の形態での処理となる。  Therefore, in each of the above steps, from the solder printing in step S1 to the insertion of the cap (including the marking) in step S10, the multi-piece board 27 on which the plurality of wiring boards 2 are formed is formed. Each process is performed in the state, and then, in step S11, the multi-piece board 27 is divided into wiring boards 2 which are individual boards, and as a result, the characteristic selection and the steps in step S12 are performed. The taping of S 13 is performed in the form of the high-frequency module 1 having the wiring board 2.
したがって、 高周波モジュール 1の組み立て工程の最終段階まで多数個取り基 板 2 7を個々の配線基板 2に分割せずに製造することにより、 高周波モジュール 1の製造コス トおよび材料コス トを低減することができ、 さらに、 円滑な組み立 てを可能にして製造ライ ンの合理化を図ることができる。  Therefore, the manufacturing cost and material cost of the high-frequency module 1 can be reduced by manufacturing the multi-cavity substrate 27 without dividing it into the individual wiring boards 2 until the final stage of the assembly process of the high-frequency module 1 In addition, a smooth assembly can be achieved, and the production line can be streamlined.
なお、 それそれの工程における各処理内容の詳細については、 実施の形態 2で 説明する。  The details of each process in each step will be described in the second embodiment.
また、 本実施の形態 1では、 高周波モジュール 1の製造工程の全体を通した特 徴として、 次のような方法を適用して組み立てる。  In the first embodiment, as a feature throughout the entire manufacturing process of the high-frequency module 1, assembly is performed by applying the following method.
まず、 図 5 ( a ) に示す検査済みの多数個取り基板 2 7の配線基板 2のみにチ ップ部品 2 2および半導体ペレッ ト 2 1 を配置してチップ部品 2 2および半導体 ベレッ ト 2 1 を良品の配線基板 2に実装するものであり、 これにより、 ステップ S 1 ◦のキヤップ揷入工程では、 キヤップ 4を良品の配線基板 2のみに取り付け る。 First, the chip component 22 and the semiconductor pellet 21 are placed only on the wiring board 2 of the inspected multi-cavity board 27 shown in FIG. Is mounted on a non-defective wiring board 2, thereby In the cap insertion process of S 1 ◦, the cap 4 is attached only to the non-defective wiring board 2.
すなわち、 納入 （購入） 段階の多数個取り基板 2 7の配線基板 2の検査 （なお 、 この検査は、 予め基板メーカで行って、 検査済みの基板を納入してもよく、 ま たは、 納入後に行ってもどちらでもよい） で不良と判定されたブロックつまり配 線基板 2には、 図 5 ( a ) に示すように不良マーク 2 eを付し、 以降の一連のェ 程 （ステップ S 3の部品搭載からステップ S 1 0のキャップ挿入まで） では、 そ れそれの工程で不良マーク 2 eを認識してこの不良マーク 2 eが形成された配線 基板 2への作業を省略する。  In other words, the inspection of the wiring board 2 of the multi-piece board 27 at the delivery (purchase) stage (this inspection may be performed in advance by the board maker, and the inspected board may be delivered, or Blocks that are determined to be defective in either case (whichever may be performed later), that is, wiring board 2, are marked with a defect mark 2e as shown in FIG. 5 (a), and a series of subsequent steps (step S3 In the process from mounting of the component to insertion of the cap in step S10), the defective mark 2e is recognized in each process, and the work on the wiring board 2 on which the defective mark 2e is formed is omitted.
これにより、 高周波モジュール 1の製造工程の削減と製造ラインの合理化を図 ることができる。  This makes it possible to reduce the number of manufacturing steps of the high-frequency module 1 and rationalize the manufacturing line.
その結果、 高周波モジュール 1の製造コス トを低減できる。  As a result, the manufacturing cost of the high-frequency module 1 can be reduced.
なお、 多数個取り基板納入段階での基板不良とは、 例えば、 回路ショートや断 線による回路オープンなどの電気的不良、 あるいは、 基板反りや外観的ショート などの外観不良などである。  In addition, the board failure at the stage of delivering a multi-cavity board is, for example, an electrical failure such as a circuit open due to a short circuit or disconnection of the circuit, or a poor appearance such as a warp or short circuit in the appearance.
さらに、 不良マーク 2 eは、 半田付け後の洗浄によって溶解することなく、 か つパターン認識を容易にするために、 半導体用のマークイ ンクなどを用い、 前記 マークインク塗布後、 ベ一ク処理を行う。  Further, the defective mark 2e is not melted by washing after soldering, and in order to facilitate pattern recognition, a mark ink for a semiconductor or the like is used. Do.
また、 同様にして、 各工程の処理後にそれそれ検査を行って工程内で不良品と なった工程不良品を認識し、 この工程不良品となった配線基板 2に不良マーク 2 eを付す。 これにより、 チップ部品 2 2搭載以降の各工程での処理時に不良マ一 ク 2 eを認識することにより、 不良マーク 2 eが付された配線基板 2 (工程不良 品） に対しては次工程の処理を行わないようにする。  In the same manner, after each process, each process is inspected to recognize a process defective product which has become a defective product in the process, and a defective mark 2 e is attached to the wiring board 2 which has become a process defective product. As a result, by recognizing the defective mark 2e at the time of processing in each process after the mounting of the chip component 22, the next process is performed on the wiring board 2 (process defective) having the defective mark 2e. Is not performed.
例えば、 図 5 ( b ) に示すように、 不良マーク 2 eが付された配線基板 2に対 しては、 図 3に示すステップ S 3の部品搭載工程で不良マーク 2 eをパターン認 識により検出して不良ブロックとなる配線基板 2にはチップ部品 2 2の搭載を行 わない。  For example, as shown in FIG. 5 (b), with respect to the wiring board 2 provided with the defect mark 2e, the defect mark 2e is recognized by pattern recognition in the component mounting process in step S3 shown in FIG. The chip component 22 is not mounted on the wiring board 2 which is detected and becomes a defective block.
同様に、 ステップ S 4のペレツ ト搭載工程においても不良マーク 2 eをパター ン認識により検出して不良プロックとなる配線基板 2には半導体ペレツ ト 2 1の 搭載を行わない。 Similarly, in the pellet mounting step of step S4, the defective mark 2e is detected by pattern recognition and the wiring board 2 which becomes a defective block is provided with the semiconductor pellet 21. Do not mount.
さらに、 ステップ S 6の部品 · ペレッ ト搭載後の自動外観検査では、 不良マー ク 2 eをパターン認識により検出し、 検査を行わずに不良としてカウン トする。 その際、 この自動外観検査で不良と判定されたブロック （配線基板 2 ) には、 図 5 ( c ) に示すように、 即乾性インクによる不良マーク 2 eを塗布などによって 付す。  Further, in the automatic appearance inspection after the parts / pellets are mounted in step S6, the defective mark 2e is detected by pattern recognition and counted as defective without performing the inspection. At this time, the block (wiring board 2) determined to be defective in the automatic appearance inspection is provided with a defective mark 2e made of quick-drying ink by coating or the like as shown in FIG. 5 (c).
また、 ステップ S 7のワイヤボンディ ング工程でも納入時の不良マーク 2 eお よび部品 ' ペレツ ト搭載後外観検査時の不良マーク 2 eをパターン認識により検 出して不良ブロックとなる配線基板 2にはワイヤボンディ ングを行わない。 さらに、 ステップ S 8のワイヤボンディ ング後の外観検査では、 ワイヤボンデ イ ング外観不良として、 図 5 ( d ) に示すように、 即乾性インクによる不良マ一 ク 2 eを塗布などによって付す。  Also, in the wire bonding process of step S7, the defective mark 2e at the time of delivery and the defective mark 2e at the time of appearance inspection after mounting the component pellet are detected by pattern recognition, and the wiring board 2 which becomes a defective block is detected. Do not perform wire bonding. Further, in the appearance inspection after the wire bonding in step S8, as shown in FIG. 5 (d), a defective mark 2e made of quick-drying ink is applied as wire bonding appearance defects as shown in FIG. 5 (d).
また、 ステップ S 9のレジン塗布工程では、 納入時の不良マーク 2 e、 部品 ' ペレツ ト搭載後外観検査時の不良マーク 2 eおよびワイヤボンディ ング後外観検 査時の不良マーク 2 eをパターン認識により検出して不良ブロックとなる配線基 板 2にはレジン塗布を行わない。  In addition, in the resin application process in step S9, the defective mark 2e at the time of delivery, the defective mark 2e at the time of appearance inspection after mounting the part pellet, and the defective mark 2e at the time of appearance inspection after wire bonding are pattern-recognized. The resin is not applied to the wiring board 2 which is detected as a defective block and becomes a bad block.
同様に、 ステップ S 1 0のキヤップ挿入工程でも、 納入時の不良マーク 2 e、 部品 'ペレツ ト搭載後外観検査時の不良マーク 2 eおよびワイヤボンディ ング後 外観検査時の不良マーク 2 eをパターン認識により検出して不良プロックとなる 配線基板 2にはキャップ挿入を行わない。  Similarly, in the cap insertion process of step S10, the defective mark 2e at the time of delivery, the defective mark 2e at the time of appearance inspection after mounting the component 'pellet', and the defective mark 2e at the time of appearance inspection after wire bonding are patterned. A cap is not inserted into the wiring board 2 that is detected by recognition and becomes a defective block.
さらに、 ステップ S 1 1の基板分割工程においては、 センサなどにより、 キヤ ップ 4の有無を検出し、 キヤップ 4の付いている配線基板 2を良品として収納し 、 一方、 キャップ 4の付いていない配線基板 2は不良と して処理する。  Further, in the board dividing step of step S11, the presence or absence of the cap 4 is detected by a sensor or the like, and the wiring board 2 with the cap 4 is stored as a good product, while the cap 4 is not attached. Wiring board 2 is treated as defective.
これにより、 次工程の不良のブロック （配線基板 2 ) への作業が省略可能にな るため、 高周波モジュール 1の製造工程の削減と製造ライ ンの合理化を図ること ができる。  This makes it possible to omit the work on the defective block (wiring board 2) in the next process, so that the manufacturing process of the high-frequency module 1 can be reduced and the manufacturing lines can be rationalized.
その結果、 高周波モジュール 1の製造コス トを低減できる。  As a result, the manufacturing cost of the high-frequency module 1 can be reduced.
なお、 多数個取り基板 2 7は、 例えば、 多層配線のセラ ミ ック基板であり、 そ の大きさは、 一例として、 配線基板 2が 4 0個形成されている場合、 7 8 . 7 5 m m x 7 5 .0 0 m m程度である。 ただし、 多数個取り基板 2 7は、 セラミ ック基板 以外のガラスエポキシ系基板などであってもよい。 The multi-cavity substrate 27 is, for example, a ceramic substrate of multilayer wiring, and its size is, for example, 78.75 when 40 wiring substrates 2 are formed. m mx 75.0 mm. However, the multi-piece substrate 27 may be a glass epoxy substrate other than the ceramic substrate.
次に、 本発明の実施の形態 2を、 図 1〜図 2 2を用いて説明する。  Next, a second embodiment of the present invention will be described with reference to FIGS.
なお、 実施の形態 2は、 図 3に示す高周波モジュール 1の組み立て手順 （製造 プロセスフロー） にしたがって、 それぞれの工程での処理の詳細を説明するもの である。  In the second embodiment, the details of the processing in each step will be described in accordance with the assembly procedure (manufacturing process flow) of the high-frequency module 1 shown in FIG.
なお、 多数個取り基板 2 7の各配線基板 2には、 その表面に、 ベアチップ実装 する半導体ペレッ ト 2 1およびチップ部品 2 2の数に応じて、 図 5 ( b ) に示す ように、 1つまたは複数の半導体ペレツ ト搭載用の凹部 2 aやチップ部品搭載用 のチップ部品用電極 2 bが形成されており、 このチップ部品用電極 2 bが、 図 7 ( b ) に示すように、 様々な表面配線 2 dによって接続されている。  As shown in FIG. 5 (b), each wiring board 2 of the multi-cavity board 27 has a surface as shown in FIG. 5 (b) according to the number of semiconductor pellets 21 and chip parts 22 mounted on the bare chip. One or a plurality of recesses 2a for mounting a semiconductor pellet and chip component electrodes 2b for mounting chip components are formed, and as shown in FIG. Various surface wiring connected by 2d.
まず、 図 7 ( a ) に示す多数個取り基板 2 7に対してステップ S 1の半田印刷 を行う。  First, solder printing in step S1 is performed on the multi-piece substrate 27 shown in FIG. 7 (a).
その際、 多数個取り基板 2 7における図 7 ( b ) に示す配線基板 2の表面 2 7 aのチップ部品用電極 2 b (図 5 ( b ) 参照） に半田印刷を行って、 図 4 ( a ) および図 7 ( c ) に示すような印刷半田パターン 2 cを形成する。  At this time, solder printing is performed on the chip component electrode 2b (see FIG. 5 (b)) on the surface 27a of the wiring board 2 shown in FIG. 7 (b) in the multi-piece board 27, and FIG. a) and a printed solder pattern 2c as shown in FIG. 7 (c) is formed.
なお、 前記半田印刷は、 例えば、 半田マスクを用いたスクリーン印刷などであ る。  The solder printing is, for example, screen printing using a solder mask.
前記半田印刷後、 ステップ S 2に示す半田ポッティ ングを行う。  After the solder printing, the solder potting shown in step S2 is performed.
ここでは、 多数個取り基板 2 7のそれそれの配線基板 2の凹部 2 aに半田をポ ッティ ングによって塗布して、 図 4 ( b ) および図 7 ( c ) に示すように、 ポッ ティ ング半田 2 f を形成する。  Here, the solder is applied to the concave portion 2a of each wiring board 2 of the multi-piece board 27 by potting, and the potting is applied as shown in FIGS. 4 (b) and 7 (c). Form solder 2 f.
なお、 図 6に示すように、 半田ポッティ ング用のノズル 2 8から半田を吐出さ せる際のノズル 2 8の移動軌跡 2 9 として、 1枚の多数個取り基板 2 7上におい て、 ノズル 2 8を配線基板 2内の隣接する凹部 2 a間で、 図 6 ( a ) に示すよう に、 最短距離で、 かつ連続動作 （一筆書き動作） で移動させるとともに、 図 6 ( ) に示すように、 多数個取り基板 2 7における隣接する他の配線基板 2に対し ても最短距離で、 かつ連続動作 （一筆書き動作） で移動させる。  As shown in FIG. 6, as a movement trajectory 29 of the nozzle 28 when the solder is ejected from the solder potting nozzle 28, the nozzle 2 8 is moved between adjacent recesses 2a in the wiring board 2 in the shortest distance and in a continuous operation (single-stroke operation) as shown in FIG. 6 (a), and as shown in FIG. 6 (). However, it is moved in a shortest distance and also in a continuous operation (single-stroke operation) with respect to another adjacent wiring substrate 2 in the multi-cavity substrate 27.
また、 このノズル 2 8の移動軌跡 2 9の制御は、 搭載位置座標プログラムによ つて設定する。 The movement trajectory 29 of the nozzle 28 is controlled by a mounting position coordinate program. To set.
本実施の形態 2のように、 まず、 配線基板 2のチップ部品用電極 2 bに半田 （ 印刷半田パターン 2 c ) を印刷し、 その後、 配線基板 2の凹部 2 aに半田をポッ ティ ングによって塗布することにより、 半田印刷を先に行うため、 半田印刷時の 前記半田マスクがポッティ ングの半田によって汚れることを防止できる。  As in the second embodiment, first, solder (printed solder pattern 2c) is printed on the chip component electrodes 2b of the wiring board 2, and then the solder is potted on the recesses 2a of the wiring board 2. By applying, solder printing is performed first, so that the solder mask at the time of solder printing can be prevented from being stained by the solder of the potting.
さらに、 ノズル 2 8による半田ポッティ ング時に、 最短距離でノズル 2 8を移 動させることにより、 その結果、 ポッティ ング時間の短縮を図ることができ、 し たがって、 半田ポッティ ング工程のスループッ トを向上できる。  In addition, by moving the nozzle 28 with the shortest distance during the solder potting by the nozzle 28, the potting time can be shortened as a result, and thus the throughput of the solder potting process can be reduced. Can be improved.
その後、 図 3のステップ S 3に示す部品搭載を行い、 部品搭載後、 ステップ S 4に示すペレッ ト搭載を行う。  After that, the components are mounted in step S3 of FIG. 3, and after the components are mounted, the pellet is mounted in step S4.
ここで、 前記部品搭載で用いる図 8 ( a ) に示す部品搭載装置 3 0の構成につ いて説明する。  Here, the configuration of the component mounting device 30 shown in FIG. 8A used for the component mounting will be described.
部品搭載装置 3 0は、 チヅプ部品 2 2を多数個取り基板 2 7の配線基板 2に移 載し、 そこで、 チップ部品 2 2を配線基板 2上に搭載するものであり、 図 8 ( b ) に示すように、 収納したチップ部品 2 2 (図 5 ( c ) 参照） をその種類 （例え ば、 品種など） ごとに送り出すことが可能な第 1部品供給部 3 1 (部品供給部） および第 2部品供給部 3 2 (部品供給部） と、 多数個取り基板 2 7を支持する X Yステージ 3 4と、 X Yステージ 3 4上においてチップ部品 2 2の搭載を行う搭 載ヘッ ド部 3 3 と、 多数個取り基板 2 7の搬送が行われる基板搬送部 3 5 とから なる。  The component mounting device 30 transfers a large number of chip components 22 to the wiring board 2 of the circuit board 27, and mounts the chip components 22 on the wiring board 2, as shown in FIG. 8 (b). As shown in Fig. 5, the first component supply unit 31 (component supply unit) and the first component supply unit 31 that can send out the stored chip parts 22 (see Fig. 5 (c)) for each type (for example, product type) (2) Component supply section 3 2 (component supply section), XY stage 34 supporting multi-cavity board 27, and mounting head section 33 mounting chip component 22 on XY stage 34 And a board transfer section 35 for transferring the multi-piece board 27.
なお、 第 1部品供給部 3 1および第 2部品供給部 3 2は、 例えば、 テープフィ —ダまたはバルクフィ一ダであり、 基板搬送部 3 5の基板搬送方向に水平な方向 にスライ ド自在に設置されている。  The first component supply unit 31 and the second component supply unit 32 are, for example, a tape feeder or a bulk feeder, and can be freely slid in the direction parallel to the board transfer direction of the board transfer unit 35. Have been.
したがって、 部品搭載装置 3 0においてチップ部品 2 2の搭載を行う際には、 第 1部品供給部 3 1および第 2部品供給部 3 2のうち、 それそれに収納されたチ ップ部品 2 2 (ここでは、 部品 A、 部品 B、 部品 C、 部品 D、 部品 E、 部品 Fの こと） を部品供給部単位で配線基板 2に供給して配置する。  Therefore, when mounting the chip component 22 in the component mounting device 30, when the chip component 22 stored in each of the first component supply unit 31 and the second component supply unit 32 is used. Here, the components A, B, C, D, E, and F) are supplied to the wiring board 2 for each component supply unit and are arranged.
これにより、 図 4 ( c ) および図 1 0 ( a ) に示すように、 配線基板 2上にチ ップ部品 2 2を搭載する。 例えば、 まず、 第 1部品供給部 3 1におけるチップ部品 2 2を全て多数個取り 基板 2 7全体に搭載し、 その後、 第 2部品供給部 3 2におけるチップ部品 2 2を 全て多数個取り基板 2 7全体に搭載する。 As a result, the chip component 22 is mounted on the wiring board 2 as shown in FIG. 4 (c) and FIG. 10 (a). For example, first, all the chip components 22 in the first component supply section 31 are mounted on the entire multi-piece board 27, and then all the chip components 22 in the second component supply section 32 are multi-piece boards 2. 7 Installed on the whole.
これにより、 第 1部品供給部 3 1および第 2部品供給部 3 2の移動距離を短縮 することができ、 その結果、 部品搭載時間のスループッ トを向上できる。  Thereby, the moving distance of the first component supply unit 31 and the second component supply unit 32 can be reduced, and as a result, the throughput of the component mounting time can be improved.
なお、 第 1部品供給部 3 1にある品種のチップ部品 2 2を収納しておき、 一方 、 第 2部品供給部 3 2に他の品種のチップ部品 2 2を収納しておく ことにより、 品種ごとの部品搭載も可能になる。  By storing the chip component 22 of the type in the first component supply unit 31 and storing the chip component 22 of another type in the second component supply unit 32, Each component can be mounted.
また、 チップ部品 2 2の搭載の際には、 配線基板 2のチップ部品用電極 2 bに 形成された印刷半田パターン 2 cを認識して印刷半田パターン 2 c上にチップ部 品用電極 2 bを配置する。  When the chip component 22 is mounted, the printed solder pattern 2 c formed on the chip component electrode 2 b of the wiring board 2 is recognized and the chip component electrode 2 b is formed on the printed solder pattern 2 c. Place.
これによ り、 半田リフロー時、 印刷半田パターン 2 cのセルファライメ ン ト効 果により、 印刷半田パターン 2 cを介してチップ部品 2 2の端子とチップ部品用 電極 2 bとが確実に半田接続されるため、 印刷半田パターン 2 cがチップ部品用 電極 2 bとずれて形成されている場合であっても、 その際発生し易い部品立ちや 部品浮きなどの不良の発生を防ぐことができる。  Thus, at the time of solder reflow, the terminals of the chip component 22 and the electrode 2b for the chip component are securely soldered via the printed solder pattern 2c due to the self-alignment effect of the printed solder pattern 2c. Therefore, even when the printed solder pattern 2c is formed to be displaced from the chip component electrode 2b, it is possible to prevent the occurrence of defects such as component standing and component floating, which are likely to occur at that time.
次に、 ステップ S 4のペレッ ト搭載で用いる図 9 ( a ) に示すペレッ ト搭載装 置 3 6の構成について説明する。  Next, the configuration of the pellet mounting device 36 shown in FIG. 9A used for mounting the pellet in step S4 will be described.
ペレツ ト搭載装置 3 6は、 半導体ペレツ ト 2 1 を多数個取り基板 2 7の配線基 板 2の凹部 2 aに移載し、 そこで、 半導体ペレツ ト 2 1 を配線基板 2の凹部 2 a に搭載するものであり、 図 9 ( b ) に示すように、 収納した半導体ペレツ ト 2 1 をその種類 （例えば、 品種など） ごとに送り出すことが可能なペレッ ト供給系 3 7 と、 半導体ペレツ ト 2 1の搭載を行うボンディ ングへッ ド部 3 8 と、 多数個取 り基板 2 7の搬送が行われる基板搬送部 3 9 と、 ボンディ ング位置などを映し出 すモニタ 4 0 とからなる。  The pellet mounting device 36 transfers a large number of semiconductor pellets 21 to the recess 2 a of the wiring board 2 of the substrate 27, and places the semiconductor pellet 21 in the recess 2 a of the wiring board 2. As shown in Fig. 9 (b), a pellet supply system 37 that can send out the stored semiconductor pellets 21 by type (for example, product type), and a semiconductor pellet It comprises a bonding head section 38 for mounting 21, a board transfer section 39 for transferring a multi-piece board 27, and a monitor 40 for displaying the bonding position and the like.
さらに、 ペレッ ト供給系 3 7には、 例えば、 4つの部品供給部である第 1ペレ ッ ト供給部 3 7 a、 第 2ペレツ ト供給部 3 7 b、 第 3ベレ ツ 卜供給部 3 7 cおよ び第 4ペレッ ト供給部 3 7 dが設けられており、 前記部品供給部は、 例えば、 チ ヅプト レイなどであり、 ペレッ ト供給系 3 7 においてそれそれ回転ブロック 3 7 eに取り付けられている。 なお、 ペレツ ト搭載装置 3 6における半導体ペレッ ト 2 1の搭載方法は、 例えば、 チッブトレイなどのペレッ ト供給部または半導体ゥ ェハからのダイ レク トピックアップ方式である。 Further, the pellet supply system 37 includes, for example, a first pellet supply section 37a, a second pellet supply section 37b, and a third pellet supply section 37, which are four component supply sections. c and a fourth pellet supply unit 37 d are provided, and the component supply unit is, for example, a chip tray, and a rotating block 37 in the pellet supply system 37. attached to e. The method of mounting the semiconductor pellet 21 in the pellet mounting device 36 is, for example, a direct pickup method from a pellet supply unit such as a chip tray or a semiconductor wafer.
したがって、 ペレツ ト搭載装置 3 6のペレツ ト供給系 3 7において半導体ペレ ッ ト 2 1の搭載を行う際には、 第 1ペレツ ト供給部 3 7 a、 第 2ペレツ ト供給部 3 7 b、 第 3ペレツ ト供給部 3 7 cおよび第 4ペレツ ト供給部 3 7 dのうち、 そ れそれに収納された半導体ペレッ ト 2 1 (ここでは、 ペレ ッ ト A、 ペレ ッ ト B、 ペレッ ト 。、 ペレッ ト Dのこと） を部品供給部単位で配線基板 2に供給して配置 する。  Therefore, when mounting the semiconductor pellet 21 in the pellet supply system 37 of the pellet mounting device 36, the first pellet supply part 37a, the second pellet supply part 37b, Of the third pellet supply section 37c and the fourth pellet supply section 37d, the semiconductor pellets 21 accommodated therein (here, pellet A, pellet B, pellet). And Pellet D) are supplied to the wiring board 2 for each component supply unit and are arranged.
これにより、 図 4 ( d ) および図 1 0 ( b ) に示すように、 配線基板 2の凹部 2 aに半導体ペレッ 卜 2 1 を搭載する。  Thus, as shown in FIGS. 4D and 10B, the semiconductor pellet 21 is mounted in the concave portion 2a of the wiring board 2.
例えば、 まず、 第 1ペレツ ト供給部 3 7 aにおける半導体ペレッ ト 2 1 を全て 多数個取り基板 2 7全体に搭載し、 その後、 回転ブロック 3 7 eを回転させて第 2ペレツ ト供給部 3 7 bにおける半導体ペレツ ト 2 1を全て多数個取り基板 2 7 全体に搭載する。 さらに、 回転プロック 3 7 eを回転させて、 順次、 第 3ペレツ ト供給部 3 7 c、 第 4ペレツ ト供給部 3 7 dの半導体ペレッ ト 2 1 をそれそれ多 数個取り基板 2 7全体に搭載する。  For example, first, all the semiconductor pellets 21 in the first pellet supply section 37a are mounted on the whole multi-piece substrate 27, and then the rotating block 37e is rotated to rotate the second pellet supply section 3. All of the semiconductor pellets 21 in 7b are mounted on the entire multi-piece substrate 27. Further, the rotary block 37 e is rotated, and the semiconductor pellets 21 of the third pellet supply section 37 c and the fourth pellet supply section 37 d are sequentially taken into a large number, and the whole board 27 is taken. To be mounted on.
これにより、 第 1ペレ ッ ト供給部 3 7 a、 第 2ペレッ ト供給部 3 7 b、 第 3ぺ レヅ ト供給部 3 7 cおよび第 4ペレツ ト供給部 3 7 dの移動距離を短縮すること ができ、 その結果、 ペレッ ト搭載時間のスループッ トを向上できる。  This reduces the travel distance of the first pellet supply section 37a, the second pellet supply section 37b, the third pellet supply section 37c, and the fourth pellet supply section 37d. As a result, the throughput of the pellet mounting time can be improved.
なお、 それぞれの前記ペレツ ト供給部に異なった品種や異なったグレードの半 導体ペレッ ト 2 1 を収納しておくことによ り、 品種ごとあるいはグレードごとの ペレツ ト搭載も可能になる。  By storing semiconductor pellets 21 of different types and different grades in the respective pellet supply units, it becomes possible to mount pellets for each type or grade.
また、 半導体ペレッ ト 2 1の搭載の際には、 図 1 0 ( b ) に示す配線基板 2の 凹部 2 aの縁部 2 gを認識して凹部 2 aに半導体ペレツ ト 2 1 を配置する。 これにより、 凹部 2 aの位置認識精度を向上でき、 その結果、 凹部 2 aの大き さを半導体ペレッ ト 2 1の大きさより若干大きい程度にすることができる。 したがって、 凹部 2 a内における半導体ペレッ ト 2 1のガタツキを少なくする ことができ、 その結果、 半導体ペレ ッ ト 2 1の水平方向の配置傾き精度を向上で きる。 When the semiconductor pellet 21 is mounted, the edge 2 g of the recess 2 a of the wiring board 2 shown in FIG. 10 (b) is recognized and the semiconductor pellet 21 is placed in the recess 2 a. . Thereby, the position recognition accuracy of the concave portion 2a can be improved, and as a result, the size of the concave portion 2a can be made slightly larger than the size of the semiconductor pellet 21. Therefore, the rattling of the semiconductor pellet 21 in the concave portion 2a can be reduced, and as a result, the accuracy of the horizontal arrangement and inclination of the semiconductor pellet 21 can be improved. Wear.
これにより、 ワイヤボンディ ング時の半導体ペレッ ト 2 1のパッ ド （表面電極 ) の認識を容易にすることができ、 その結果、 ワイヤボンディ ング不良を低減で きる。  As a result, the pads (surface electrodes) of the semiconductor pellet 21 can be easily recognized at the time of wire bonding, and as a result, defective wire bonding can be reduced.
また、 チップ部品 2 2の搭載を先に行い、 その後、 半導体ペレッ ト 2 1の搭載 を行うことにより、 半導体ペレツ ト 2 1の損傷要因を低減することができる。 すなわち、 半導体ペレッ ト 2 1は、 外部からのス ト レスなどによって不良にな る確率がチップ部品 2 2 と比較して高いため、 チップ部品 2 2搭載後に半導体ぺ レッ ト 2 1 を搭載した方が好ましく、 これにより、 半導体ペレッ ト 2 1が損傷す る可能性を低くできる。  Further, by mounting the chip component 22 first and then mounting the semiconductor pellet 21, it is possible to reduce the cause of damage to the semiconductor pellet 21. In other words, since the semiconductor pellet 21 has a higher probability of failure due to stress from the outside than the chip component 22, it is better to mount the semiconductor pellet 21 after mounting the chip component 22. Therefore, the possibility that the semiconductor pellet 21 is damaged can be reduced.
その後、 図 3に示すステップ S 5のリ フ口一を行う。  After that, the reflex of step S5 shown in FIG. 3 is performed.
ここでは、 多数個取り基板 2 7の半田リ フ口一を行って、 配線基板 2上のチッ プ部品 2 2および半導体ペレッ ト 2 1をともに半田接続する。  Here, the solder reflow opening of the multi-piece board 27 is performed, and the chip component 22 and the semiconductor pellet 21 on the wiring board 2 are both connected by soldering.
続いて、 ステップ S 6の自動外観検査を行う。  Subsequently, an automatic appearance inspection in step S6 is performed.
ここでは、 リ フ口一後の多数個取り基板 2 7の外観検査を行い、 リフ口一不良 の有無を検査する。  Here, the appearance inspection of the multi-cavity substrate 27 just after the riff opening is performed to check whether there is any defect in the riff opening.
その際、 搭載部品の位置検出においてレーザ光などを用いて位置検出する場合 、 配線基板 2上で段差箇所を認識することにより、 精度良く搭載部品の位置認識 を行うことができる。  At this time, when the position of the mounted component is detected using a laser beam or the like, the position of the mounted component can be accurately recognized by recognizing the stepped portion on the wiring board 2.
例えば、 図 1 1 ( a ) の多数個取り基板 2 7における配線基板 2に形成された 図 1 1 ( b ) に示すスルーホール 2 hや図 7 ( b ) に示す表面配線 2 dなどを認 識することにより、 精度良く搭載部品の位置を認識できる。  For example, a through hole 2h shown in FIG. 11 (b) and a surface wiring 2d shown in FIG. 7 (b) formed on the wiring board 2 of the multi-piece board 27 shown in FIG. 11 (a) are recognized. With this knowledge, the position of the mounted component can be recognized with high accuracy.
その後、 ステップ S 7に示すワイヤボンディ ングを行う。  Thereafter, wire bonding shown in step S7 is performed.
ここでは、 例えば、 図 4 ( e ) に示すように、 金線などのワイヤ 2 4を用いて ワイヤボンディ ングを行い、 半導体ペレッ ト 2 1の表面電極であるパッ ドとこれ に対応する多数個取り基板 2 7の配線基板 2における基板側端子 2 i (図 5 ( b ) 参照） とをワイヤ 2 4によって接続する。  Here, for example, as shown in FIG. 4 (e), wire bonding is performed using a wire 24 such as a gold wire, and a pad serving as a surface electrode of the semiconductor pellet 21 and a plurality of corresponding pads are formed. The board side terminal 2 i (see FIG. 5 (b)) of the wiring board 2 of the wiring board 27 is connected with the wire 24.
その後、 ステップ S 8に示す外観検査を行う。  After that, the appearance inspection shown in step S8 is performed.
ここでは、 ワイヤボンディ ング後の多数個取り基板 2 7の外観検査を行い、 ヮ ィャボンディ ング不良の有無を検査する。 Here, the appearance inspection of the multi-piece board 27 after wire bonding was performed. Inspect for bonding defects.
その後、 ステップ S 9に示すレジン （封止用樹脂 2 3 ) 塗布を行う。  Then, the resin (encapsulating resin 23) shown in step S 9 is applied.
ここでは、 図 4 ( f ) に示すように、 ポッティ ング方法によって、 多数個取り 基板 2 7の配線基板 2における凹部 2 a上に封止用樹脂 2 3を滴下し、 これによ つて、 半導体ペレッ ト 2 1およびワイヤ 2 4を封止用樹脂 2 3により樹脂封止す る。  Here, as shown in FIG. 4 (f), the sealing resin 23 is dropped on the concave portion 2 a of the wiring board 2 of the multi-piece board 27 by the potting method, thereby forming the semiconductor. The pellet 21 and the wire 24 are sealed with a sealing resin 23.
その際、 図 1 2 ( a ) に示す多数個取り基板 2 7の分割用溝部 2 7 bを避けて 、 配線基板 2の凹部 2 aに対してポッティ ングにより封止用樹脂 2 3を塗布して 半導体ペレッ ト 2 1 を樹脂封止する。  At this time, the sealing resin 23 is applied by potting to the recess 2 a of the wiring board 2, avoiding the dividing groove 27 b of the multi-piece board 27 shown in FIG. 12 (a). The semiconductor pellet 21 is sealed with resin.
すなわち、 多数個取り基板 2 7に形成された個片基板分割用のス リ ッ トである 分割用溝部 2 7 bに封止用樹脂 2 3が掛からないように、 図 1 2 ( b ) に示すレ ジン塗布範囲 4 1に示すように、 個片ブロックごと、 つま り多数個取り基板 2 7 上の各配線基板 2ごとに封止用樹脂 2 3の塗布を行う。  That is, as shown in FIG. 12 (b), the sealing resin 23 is not applied to the dividing groove portion 27 b which is a slit for dividing the individual substrate formed on the multi-cavity substrate 27. As shown in the resin application range 41 shown, the encapsulating resin 23 is applied to each individual block, that is, to each wiring board 2 on the multi-cavity board 27.
したがって、 多数個取り基板 2 7の分割用溝部 2 7 bには封止用樹脂 2 3が掛 からないため、 これにより、 図 1 1 ( b ) に示すスルーホール 2 hなどから封止 用樹脂 2 3が入り込んで基板裏面に回り込み、 その結果、 基板分割時などに悪影 響を及ぼすことを防止できる。  Therefore, the sealing resin 23 is not applied to the dividing groove portion 27 b of the multi-piece substrate 27, so that the sealing resin 23 is removed from the through hole 2 h shown in FIG. 11B. 23 can be prevented from entering and sneaking into the back surface of the substrate, thereby adversely affecting when the substrate is divided.
その後、 ステップ S 1 0に示すキャップ揷入を行う。  After that, cap insertion shown in step S10 is performed.
なお、 本実施の形態 2のキャップ揷入工程では、 図 1 3に示すキャップ 4に対 して、 図 1 4に示すようなマーク付け、 認識マークであるマーク 4 2の U V ( U1 tra Vi ol et ) 乾燥、 マーク 4 2のパターン認識によるマーク外観検査およびキヤ ップ挿入を連続した一貫処理で行い、 さらに、 前記キャップ挿入の際に、 マーク 外観検査によって良品と判定されたキャップ 4のみをキャップ付け （挿入） する ものであり、 これにより、 キャップ揷入工程における組み立て時間の短縮を図る とともに、 他のマーク 4 2が付されたキャップ 4の混入を未然に防ぐことができ る。  In addition, in the cap introduction step of the second embodiment, the cap 4 shown in FIG. 13 is marked with a mark as shown in FIG. 14 and the UV (Ultra Viol et) Drying, mark 4 Inspection of the mark appearance by pattern recognition of mark 2 and cap insertion are performed by continuous integrated processing, and when inserting the cap, only caps 4 judged as good by the mark appearance inspection are capped. In this way, it is possible to shorten the assembling time in the step of inserting the cap and to prevent the cap 4 with the other mark 42 from being mixed.
まず、 前記キャップ揷入工程におけるキャップ 4へのマーク 4 2のマ一キング を行う。  First, the mark 42 is marked on the cap 4 in the cap introduction step.
なお、 図 1 3 ( a ) , ( b ) , ( c ) に示すように、 キャップ 4は、 例えば、 金属 板などからなる箱型のものであり、 多数個取り基板 2 7の配線基板 2に係合可能 な図 1 に示すフヅク 1 9を支持するフック支持アーム 1 7 (フック支持部） が対 向して設けられている。 As shown in FIGS. 13 (a), (b) and (c), the cap 4 is made of, for example, a metal. The hook support arm 17 (hook support portion) that supports the hook 19 shown in FIG. 1 and that can be engaged with the wiring board 2 of the multi-piece board 27 It is provided.
また、 図 1 4に示すように、 認識マークであるマーク 4 2は、 例えば、 高周波 モジュール 1の製造番号または型番号などであり、 文字や記号からなるものであ る。  Further, as shown in FIG. 14, the mark 42, which is a recognition mark, is, for example, a serial number or a model number of the high-frequency module 1, and is composed of characters and symbols.
そこで、 キャップ 4の表面 4 aにマーク 4 2を付す。  Therefore, the mark 4 2 is attached to the surface 4 a of the cap 4.
続いて、 マーク 4 2を U V乾燥し、 乾燥後、 パターン認識によってマーク 4 2 を外観検査を行い、 これによつて良品のマーク 4 2が付されたキャップ 4を選別 する。  Subsequently, the mark 42 is dried by UV. After drying, the appearance of the mark 42 is inspected by pattern recognition, and the caps 4 having the non-defective marks 42 are selected.
その後、 良品となったキヤップ 4を多数個取り基板 2 7の配線基板 2に 1つず つ挿入する （取り付ける） 。  After that, many non-defective caps 4 are inserted into the wiring board 2 of the multi-piece board 27 one by one (attachment).
なお、 マーク 4 2が付されたキヤップ 4のマーク 4 2の検査を行った後に良品 のキャップ 4のみを配線基板 2に取り付けるため、 マーク無し、 マーク不良も し くは他のマーク 4 2のキヤップ 4など不良品キヤップの取り付けを防ぐことがで きる。  In addition, after inspecting the mark 4 2 of the cap 4 with the mark 4 2, only the non-defective cap 4 is attached to the wiring board 2, so there is no mark, mark failure or other mark 4 2 cap. This can prevent defective caps such as 4 from being attached.
これにより、 マーク 4 2に関する不良品キャップが取り付けられることはない ため、 製造ラインの合理化を図ることができる。  As a result, since a defective cap for the mark 42 is not attached, the production line can be rationalized.
次に、 キャップ 4の挿入 （装着） 方法について説明する。  Next, a method of inserting (attaching) the cap 4 will be described.
ここで、 キヤップ揷入工程で使用される図 1 5 ( a ) および図 1 6に示すキヤ ップ装着装置 4 4の構成について説明する。  Here, the configuration of the cap mounting device 44 shown in FIGS. 15A and 16 used in the cap loading step will be described.
キャップ装着装置 4 4は、 多数個取り基板 2 7を支持する X Yテーブル 4 5 と 、 キャップ装着を行う装着ユニッ ト 4 6 と、 X Yテーブル 4 5上に搭載された多 数個取り基板 2 7における認識箇所である複数のフック孔 2 7 c (図 1 5 ( b ) 参照） と、 フック孔 2 7 cを撮像する認識カメラ 4 7 と、 キャップ 4を傾斜させ て配置するァライメン トステーション 4 8 とから構成される。  The cap mounting device 44 includes an XY table 45 supporting the multi-piece substrate 27, a mounting unit 46 for mounting the cap, and a multi-piece substrate 27 mounted on the XY table 45. A plurality of hook holes 27c (see Fig. 15 (b)), which are recognition points, a recognition camera 47 for imaging the hook holes 27c, and an alignment station 48 for disposing the cap 4 at an angle. Consists of
さらに、 装着ュニッ ト 4 6には、 キャップ 4を吸着保持可能な吸着コレッ ト 4 6 aと、 吸着コレツ ト 4 6 aを上下動させる第 1 シリンダ 4 6 bおよび第 1パネ 4 6 cと、 吸着コレッ ト 4 6 aの上下動をガイ ドする第 1スライダ 4 6 dと、 キ ヤップ挿入の際にキャップ 4を押圧するブッシャ一 4 6 i と、 プッシャ一 4 6 i を上下動させる第 2シリンダ 4 6 eおよび第 2パネ 4 6 f と、 プッシャ一 4 6 i の上下動をガイ ドする第 2スライダ 4 6 gとが設けられている。 Further, the mounting unit 46 includes a suction collet 46a capable of holding the cap 4 by suction, a first cylinder 46b and a first panel 46c for vertically moving the suction collet 46a, A first slider 46 d to guide the vertical movement of the suction collet 46 a, and a key The pusher 46 i that presses the cap 4 when inserting the cap, the second cylinder 46 e and the second panel 46 f that moves the pusher 46 i up and down, and the vertical movement of the pusher 46 i A second slider 46 g for guiding is provided.
また、 ァライメン トステーション 4 8には、 キャップ 4を所定角度に傾斜させ て支持する傾斜主治具 4 8 aと、 傾斜主治具 4 8 aによりキャップ 4を傾斜させ て支持した際にキヤヅプ 4をその周囲でガイ ドする傾斜補助治具 4 8 bとが設け られている。  In addition, the alignment station 48 includes an inclined main jig 48 a for supporting the cap 4 at a predetermined angle and a cap 4 when the cap 4 is inclined and supported by the inclined main jig 48 a. An auxiliary tilting jig 48 b is provided to guide around.
なお、 吸着コレッ ト 4 6 aによつて傾斜主治具 4 8 aからキャップ 4を吸着保 持した際に、 傾斜主治具 4 8 aでのキヤップ 4の傾斜角度と同様の角度で吸着コ レッ ト 4 6 aによつて傾斜保持可能なように、 吸着コレッ ト 4 6 aの吸着面 4 6 j は、 傾斜主治具 4 8 aの支持面の角度と同様の角度で形成されている。  When the cap 4 is suction-held from the inclined main jig 48 a by the suction collet 46 a, the suction collet is inclined at the same angle as the inclination angle of the cap 4 at the inclined main jig 48 a. The suction surface 46 j of the suction collet 46 a is formed at the same angle as the angle of the support surface of the main tilting jig 48 a so that the suction collet 46 a can be tilted and held.
キャップ 4の挿入の際には、 まず、 図 1 5 ( a ) に示すように、 多数個取り基 板 2 7を X Yテーブル 4 5に配置し、 その後、 認識カメラ 4 7によって図 1 5 ( b ) に示す多数個取り基板 2 7のフック孔 2 7 cを撮像してこれの位置を検出す る。  When inserting the cap 4, first, as shown in FIG. 15 (a), the multi-cavity substrate 27 is placed on the XY table 45, and thereafter, the recognition An image of the hook hole 27 c of the multi-piece substrate 27 shown in) is detected and its position is detected.
一方、 図 1 6に示すように、 良品と判定されたキャップ 4を、 キャップ装着装 置 4 4のァライメン トステ一シヨン 4 8の傾斜主治具 4 8 aによつて所定角度に 傾斜させて支持し、 その後、 キャップ 4が傾斜した状態を維持させて装着ュニッ ト 4 6の吸着コレッ ト 4 6 aによってキャップ 4を吸着保持する。  On the other hand, as shown in FIG. 16, the cap 4 determined to be non-defective is supported by being inclined at a predetermined angle by the inclination main jig 48 a of the alignment station 48 of the cap mounting device 44. After that, the cap 4 is held by the suction collet 46 a of the mounting unit 46 while the cap 4 is kept inclined.
さらに、 この状態で、 キャップ 4の対向する 2つのフック支持アーム 1 7のう ち、 傾斜によって下側に配置された一方のフック支持アーム 1 Ίが X Yテーブル 4 5上に搭載された多数個取り基板 2 7の所望のフック孔 2 7 c上に配置される ように装着ュニッ ト 4 6ごとキャップ 4を移動させる。  Further, in this state, one of the two hook support arms 17 opposed to each other on the cap 4 and one of the hook support arms 1 に よ っ て arranged on the lower side due to the inclination is mounted on the XY table 45 with a large number of pieces. The cap 4 is moved together with the mounting unit 46 so as to be placed on a desired hook hole 27 c of the substrate 27.
その際、 多数個取り基板 2 7の複数の配線基板 2に対して、 キャップ 4の対向 する 2つのフック支持アーム 1 7のうち傾斜により下側に配置されたフック支持 アーム 1 7を、 図 1 7 ( b ) に示すように、 挿入すべき 2つのフック孔 2 7 cの うちの隣接するキヤップ 4が取り付けられていない側のフック孔 2 7 cに揷入す る。  At this time, with respect to the plurality of wiring boards 2 of the multi-cavity board 27, the hook supporting arm 17 arranged at the lower side due to the inclination of the two hook supporting arms 17 facing the cap 4 is shown in FIG. As shown in FIG. 7 (b), of the two hook holes 27c to be inserted, insert into the hook hole 27c on the side where the adjacent cap 4 is not attached.
なお、 キャップ 4の対向する 2つのフック支持アーム 1 7のうち、 図 1 7 ( a )， ( b ) に示すように、 隣接するキャップ 4が取り付けられていない側のフック 孔 2 7 cに対して、 これに対応するフック支持アーム 1 7 (ここでは A側のフッ ク支持アーム 1 7のこと） を先に挿入することにより、 装着済みのキヤップ 4 と の干渉を避けることができる。 Note that, of the two hook support arms 17 of the cap 4 facing each other, ) And (b), the corresponding hook support arm 17 (here the hook support arm 1 on the A side) is inserted into the hook hole 27 c on the side where the cap 4 is not attached. By inserting (7) first, it is possible to avoid interference with the installed cap (4).
その結果、 前記干渉による トラブルの発生を防止できる。  As a result, it is possible to prevent the occurrence of trouble due to the interference.
ここでは、 図 1 7 ( a ) に示すように、 キャップ装着装置 4 4の装着ュニッ ト Here, as shown in Fig. 17 (a), the mounting unit of the cap mounting device 4 4
4 6の A側の第 1シリンダ 4 6 bによって吸着コレッ ト 4 6 aを下降させ、 さら に、 キャップ 4の傾斜により、 フック支持アーム 1 7のフック 1 9をこれに対応 するフック孔 2 7 cに対して斜めに挿入する。 The suction collet 46a is lowered by the first cylinder 46b on the A side of 46, and the hook 19 of the hook support arm 17 is hooked up by the inclination of the cap 4. Insert at an angle to c.
その際、 キャップ装着装置 4 4の A側において、 キャップ 4のフック支持ァ一 ム 1 7を斜めにして挿入することにより、 フック支持アーム 1 7のフック 1 9を フック孔 2 7 cに接触させないようにして挿入できる。  At this time, by inserting the hook support arm 17 of the cap 4 at an angle on the A side of the cap mounting device 44, the hook 19 of the hook support arm 17 does not contact the hook hole 27c. Can be inserted as follows.
これにより、 フック支持アーム 1 7の挿入時に、 フック 1 9のフック爪 1 8 と フック孔 2 7 c とが接触しないため、 多数個取り基板 2 7におけるフック孔 2 7 c付近の破損を防止することができ、 その結果、 多数個取り基板 2 7の歩留り向 上と品質の向上とを図ることができる。  As a result, when the hook support arm 17 is inserted, the hook claw 18 of the hook 19 does not come into contact with the hook hole 27 c, thereby preventing damage to the vicinity of the hook hole 27 c in the multi-piece board 27. As a result, the yield and quality of the multi-piece substrate 27 can be improved.
その後、 図 1 8 ( a ) に示すように、 隣接するキャップ 4が取り付けられてい ない側のフック孔 2 7 cに挿入した一方 （A側） のフック支持アーム 1 7に対し て配線基板 2を幅よせ 4 6 k ( X Yテーブル 4 5を B側から A側に設定値移動さ せて多数個取り基板 2 7の配線基板 2を移動させる） することによって A側のフ ック支持アーム 1 7に荷重を付与する。  Then, as shown in Fig. 18 (a), the wiring board 2 is inserted into the hook support arm 17 on one side (A side) inserted into the hook hole 27c on the side where the adjacent cap 4 is not attached. The hook support arm 17 on the A side by moving the width 46 k (moving the wiring board 2 of the multi-piece board 27 by moving the XY table 45 from the B side to the A side and moving the set value) Load.
その際、 図 1 8 ( a ) に示すキャップ 4の表面 4 aの A側の端部が吸着コレッ ト 4 6 aの図 1 8 ( b ) に示すァ一ムス ト ッパ 4 6 hに突き当たって支持される ため、 配線基板 2の幅よせ 4 6 kによる荷重が A側のフック支持アーム 1 7に付 与され、 その結果、 A側 （一方） のフック支持アーム 1 7を B側 （他方） のフッ ク支持アーム 1 7から離れる方向にその弾性領域内で橈ませる （図 1 8 ( c ) 参 昭）  At this time, the A-side end of the surface 4a of the cap 4 shown in Fig. 18 (a) abuts the damper stopper 46h shown in Fig. 18 (b) of the suction collet 46a. As a result, a load due to the width 46 k of the wiring board 2 is applied to the hook support arm 17 on the A side, and as a result, the hook support arm 17 on the A side (one side) is connected to the B side (the other side). (See Figure 18 (c)).
なお、 X Yテーブル 4 5の幅よせ 4 6 kの際の移動の前記設定値をフック支持 アーム 1 7のパネ性が失効しない範囲とすることにより、 その弾性領域内で橈ま せることが可能となる。 In addition, by setting the above-mentioned set value of the movement when the width of the XY table 45 is set to 46 k in the range in which the paneling property of the hook support arm 17 does not expire, the radius is set within the elastic range. It is possible to make it.
A側のフック支持アーム 1 7を橈ませたことにより、 キャップ 4における 2つ のフック支持アーム 1 7間の距離が広がり、 その結果、 A側のフック支持アーム 1 7のフック 1 9のフック爪 1 8 (図 1参照） が配線基板 2の引っ掛かり部 1 6 に係合するとともに、 図 1 8 ( b ) に示すように、 B側 （他方） のフック支持ァ —ム 1 7のフック 1 9が多数個取り基板 2 7の他のフック孔 2 7 c上に配置され る。  The radius of the hook support arm 17 on the A side increases the distance between the two hook support arms 17 on the cap 4, and as a result, the hook claw on the hook 19 on the hook support arm 17 on the A side 18 (see FIG. 1) engages with the hooked portion 16 of the wiring board 2 and, as shown in FIG. 18 (b), the hook support arm 17 on the B side (the other side) 17 Are arranged on the other hook holes 27 c of the multi-piece substrate 27.
この状態で、 図 1 9 ( a ) に示すように、 B側の第 2シリンダ 4 6 eおよび第 2バネ 4 6 f によりプッシヤー 4 6 iを下降させてキャップ 4の表面 4 aの B側 の端部を押圧し、 これにより、 A側のフック支持アーム 1 7を挿入した図 1 7 ( a ) に示すフック孔 2 7 c と対向して配置された他のフック孔 2 7 cに B側 （他 方） のフック支持アーム 1 7を挿入する。  In this state, as shown in Fig. 19 (a), the pusher 46i is lowered by the second cylinder 46e and the second spring 46f on the B side to lower the surface 4a of the cap 4 on the B side. By pressing the end, the hook support arm 17 on the A side is inserted, so that the other side of the hook hole 27 c shown in FIG. Insert the other hook support arm 17.
その際、 多数個取り基板 2 7の図 1 8に示す幅よせ 4 6 kにより、 他のフック 孔 2 7 cが A側のフック支持アーム 1 7寄りに配置されているため、 B側のフッ ク支持アーム 1 7の揷入時に、 A側の場合と同様に、 フック 1 9のフック爪 1 8 とフック孔 2 7 cとが接触せず、 多数個取り基板 2 7における他のフック孔 2 7 c付近の破損を防止することができる。  At this time, since the other hook hole 27c is arranged near the hook support arm 17 on the A side due to the width 46k of the multi-piece board 27 shown in FIG. When the hook support arm 17 is inserted, the hook claw 18 of the hook 19 does not contact the hook hole 27 c as in the case of the A side. Damage around 7c can be prevented.
その結果、 多数個取り基板 2 7の歩留り向上と品質の向上とを図ることができ る。  As a result, the yield and quality of the multi-piece substrate 27 can be improved.
その後、 多数個取り基板 2 7の配線基板 2の幅よせ 4 6 kによる A側のフック 支持アーム 1 7への荷重の付与を開放し、 これによつて、 A側のフック支持ァ一 ム 1 7のフック 1 9および B側のフック支持アーム 1 7のフック 1 9を配線基板 2の両側の引っ掛かり部 1 6にそれそれ係合させる。  Thereafter, the load applied to the A-side hook support arm 17 by the width adjustment 46 k of the wiring board 2 of the multi-piece board 27 is released, whereby the A-side hook support arm 1 is released. The hook 19 of 7 and the hook 19 of the hook support arm 17 on the B side are engaged with the hooks 16 on both sides of the wiring board 2, respectively.
その結果、 図 1 9 ( b ) に示すように、 キヤップ 4の多数個取り基板 2 7の配 線基板 2への装着 （取り付け） を完了することができ、 したがって、 キャップ 4 の多数個取り基板 2 7への自動装着を容易に行うことができる。  As a result, as shown in FIG. 19 (b), the mounting (attachment) of the multi-piece board 27 of the cap 4 to the wiring board 2 can be completed, and therefore, the multi-piece board of the cap 4 can be completed. Automatic mounting on 27 can be performed easily.
これにより、 図 4 ( g ) に示すように、 チップ部品 2 2 と半導体ペレッ ト 2 1 とが搭載された配線基板 2をキャップ 4によって覆うことができる。  Thereby, as shown in FIG. 4 (g), the wiring board 2 on which the chip component 22 and the semiconductor pellet 21 are mounted can be covered with the cap 4.
本実施の形態 2のキャップ 4の装着方法によれば、 キャップ 4の脱落、 キヤッ プ 4のがたつきという不具合を無くすことができる。 According to the mounting method of the cap 4 according to the second embodiment, the cap 4 is The problem of rattling of step 4 can be eliminated.
また、 多数個取り基板 2 7を用いた一貫組み立てライン上でキヤップ 4による シールが行えるため、 量産効率を向上できる。  In addition, since the sealing with the cap 4 can be performed on an integrated assembly line using the multi-cavity substrate 27, mass production efficiency can be improved.
さらに、 キャップ半田付けによるシール方法などと比較した場合、 工数を著し く低減することができ、 さらに、 フラックスなどの汚れに対する洗浄工程も省略 することができる。  Further, as compared with a sealing method by soldering a cap or the like, the number of steps can be significantly reduced, and a washing step for dirt such as flux can be omitted.
その後、 図 2 0に示すように、 第 1スライダ 4 6 dおよび第 2スライダ 4 6 g をガイ ドとして吸着コレッ ト 4 6 aとプッシャ一 4 6 i とを上昇させて元の位置 に戻し、 さらに、 装着ユニッ ト 4 6をァライメントステーション 4 8上に移動さ せてキャップ挿入工程を終える。  Thereafter, as shown in FIG. 20, the suction collet 46a and the pusher 46i are raised to the original position by using the first slider 46d and the second slider 46g as guides, and returned to their original positions. Further, the mounting unit 46 is moved to the alignment station 48 to complete the cap insertion process.
その後、 図 3に示すステップ S 1 1の基板分割を行って、 多数個取り基板 2 7 を個片基板である個々の配線基板 2に分割し、 これにより、 図 4 ( h ) に示すよ うな個々の高周波モジュール 1の形態とする。  After that, the board division of step S11 shown in FIG. 3 is performed, and the multi-piece board 27 is divided into individual wiring boards 2 which are individual boards, thereby obtaining a structure as shown in FIG. 4 (h). Each high-frequency module is in the form of 1.
続いて、 ステップ S 1 2に示す特性選別を行って、 それぞれの高周波モジュ一 ル 1の電気的特性を取得するとともに、 その結果により高周波モジュール 1を選 別する。  Subsequently, the characteristic selection shown in step S12 is performed to obtain the electrical characteristics of each high-frequency module 1, and the high-frequency module 1 is selected based on the result.
なお、 高周波モジュール 1では、 セラ ミ ック基板すなわち配線基板 2の配線パ ターン導体抵抗、 配線パターン間容量の口ッ トばらつきおよび半導体ペレッ ト 2 1の特性ばらつきによってモジュール特性が変動する。 したがって、 特性選別の 工程では、 高周波モジュール 1 における配線基板 2の電気的特性をモニタ一する そこで、 高周波モジュール 1の組み立てでは、 予め、 半導体ペレッ ト 2 1の特 性をグレード分類して、 使用する配線基板 2 と半導体ペレッ ト 2 1 との組み合わ せに最適なチップコンデンサゃチップ抵抗などのチップ部品 2 2の定数を選択し て組み立てを行う。  In the high-frequency module 1, module characteristics fluctuate due to variations in the wiring pattern conductor resistance of the ceramic substrate, that is, the wiring substrate 2, variations in the capacitance between the wiring patterns, and variations in the characteristics of the semiconductor pellet 21. Therefore, in the characteristic selection process, the electrical characteristics of the wiring board 2 in the high-frequency module 1 are monitored. Therefore, in assembling the high-frequency module 1, the characteristics of the semiconductor pellet 21 are classified and used in advance. Assembling is performed by selecting the constants of chip components 22 such as a chip capacitor and a chip resistor that are optimal for the combination of the wiring board 2 and the semiconductor pellet 21.
すなわち、 特性選別された配線基板 2および半導体ペレッ ト 2 1 を用意し、 こ の選別された配線基板 2に半導体ペレツ ト 2 1 とチップ部品 2 2 とを実装するこ とにより、 高周波モジュール 1の特性を許容範囲に入れることができ、 その結果 、 特性的に高品質で、 かつ安定した高周波モジュール 1 を組み立てることができ る。 That is, by preparing the wiring board 2 and the semiconductor pellet 21 whose characteristics have been selected and mounting the semiconductor pellet 21 and the chip component 22 on the wiring board 2 thus selected, the high-frequency module 1 is manufactured. The characteristics can be within an acceptable range, and as a result, a high-quality and stable high-frequency module 1 can be assembled. You.
ここで、 図 2 1は、 高周波モジュール 1の配線基板 2の特性における周波数と 出力 （P o u t ) の関係の一例を示したものである。  Here, FIG. 21 shows an example of the relationship between the frequency and the output (Pout) in the characteristics of the wiring board 2 of the high-frequency module 1.
例えば、 図 2 1において出力 Q ( W ) を高周波モジュール 1の出力合否のしき い値とすると、 高周波モジュール 1の第 1サンプル 5 0の場合、 使用周波数帯域 4 9では十分に出力合格 5 2 となり、 高周波モジュール 1 として良品となる。 しかし、 第 2サンプル 5 1の場合、 使用周波数帯域 4 9では、 約半分の領域 （ 使用周波数帯域 4 9における低い周波数側の領域） でしか出力合格 5 2 とならず 、 残りの約半分の領域 （使用周波数帯域 4 9における高い周波数側の領域） では 出力不合格 5 3 となり、 結果的には、 不良品の高周波モジュール 1 となる。  For example, assuming that the output Q (W) in Fig. 21 is the threshold for the pass / fail of the output of the high-frequency module 1, in the case of the first sample 50 of the high-frequency module 1, the output is sufficiently acceptable in the used frequency band 49. It becomes a good product as the high-frequency module 1. However, in the case of the second sample 51, in the used frequency band 49, the output passes only in about half the area (the lower frequency side area in the used frequency band 49), and the output passes 52, and the remaining about half area In the (higher frequency range in the used frequency band 49), the output failed 53, resulting in a defective high-frequency module 1.
また、 図 2 2は、 半導体ペレッ ト 2 1のグレード分類の一例を示したものであ り、 ここでは、 前工程ウェハ検査のデータを元にして自動分類治具詰機によって 半導体べレッ トごとにグレード分けを行ったものを示している。  Fig. 22 shows an example of the grade classification of the semiconductor pellet 21. Here, based on the data of the pre-process wafer inspection, the automatic sorting jig-packing machine is used for each semiconductor pellet. Shows the result of grade classification.
なお、 図 2 2中、 C i s sは容量、 I d s sは漏れ電流、 V t hはスレツシホ —ルド電圧をそれぞれ表しており、 例えば、 図 2 2においてグレード Ν Ο · 3、 4 、 8の 3つの半導体ペレッ ト 2 1 を組み合わせて用いることにより、 最適な回路 定数を設定できる。  In FIG. 22, C iss represents capacitance, I dss represents leakage current, and V th represents threshold voltage. For example, in FIG. 22, three semiconductors of grades Ν Ο · 3, 4 and 8 are shown. The optimal circuit constants can be set by using a combination of pellets 21.
その後、 図 3に示すステップ S 1 3のテーピングを行う。  Thereafter, taping in step S13 shown in FIG. 3 is performed.
すなわち、 選別された複数の高周波モジュール 1 をテーピングして、 図 4 ( i ) に示すリール 4 3に巻き取って収納する。  That is, a plurality of the selected high-frequency modules 1 are taped, wound and stored on a reel 43 shown in FIG. 4 (i).
本実施の形態 2の半導体装置 （高周波モジュール 1 ) の製造方法によれば、 従 来、 1 2個の工程で組み立てていたものを 9個の工程に減らすことができ、 その 結果、 製造ラインの合理化を実現することができる。  According to the method of manufacturing the semiconductor device (high-frequency module 1) of the second embodiment, what was conventionally assembled in 12 steps can be reduced to 9 steps, and as a result, Streamlining can be achieved.
また、 多数個取り基板 2 7を用いての高周波モジュール 1の組み立てによるス ループッ トの向上や基板材料費の低減化を図ることができ、 その結果、 生産性を 従来の組み立て方法の約 3倍、 さらに、 5 0 %の価格低減化を実現できる。  Also, by assembling the high-frequency module 1 using the multi-cavity substrate 27, it is possible to improve the throughput and reduce the material cost of the substrate, and as a result, the productivity is approximately three times that of the conventional assembling method. Further, a price reduction of 50% can be realized.
以上、 本発明者によってなされた発明を発明の実施の形態 1 , 2に基づき具体 的に説明したが、 本発明は前記発明の実施の形態 1 , 2に限定されるものではな く、 その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 例えば、 実施の形態 2の特性選別の工程では、 配線基板 2の電気的特性をモニ 夕一し、 予め、 半導体ペレッ ト 2 1の特性をグレード分類して、 使用する配線基 板 2 と半導体ペレッ ト 2 1 とで最適な組み合わせで組み立てる場合を説明したが 、 配線基板 2 と半導体ペレツ ト 2 1 とを選別して組み合わせても高周波モジュ一 ル 1の特性が得られない場合には、 チップ部品 2 2を交換するなどして高周波モ ジュール 1の特性が得られるようにしてもよい。 As described above, the invention made by the inventor has been specifically described based on the first and second embodiments of the present invention. However, the present invention is not limited to the first and second embodiments of the invention, and the gist thereof is described. It is needless to say that various changes can be made without departing from the scope. For example, in the characteristic selection step of the second embodiment, the electrical characteristics of the wiring board 2 are monitored, the characteristics of the semiconductor pellet 21 are classified in advance, and the wiring substrate 2 and the semiconductor pellet used are classified. Although the case of assembling in the optimal combination with the component 21 has been described, if the characteristics of the high-frequency module 1 cannot be obtained even if the wiring board 2 and the semiconductor pellet 21 are selectively combined, the chip component The characteristics of the high-frequency module 1 may be obtained by exchanging 22 or the like.
また、 前記実施の形態で説明した半導体ペレッ ト 2 1は、 シリコンの半導体ゥ ェハから取得したものであってもよく、 また、 ガリウム ， ヒ素の半導体ウェハか ら取得したものであってもよく、 さらに、 S O I、 G e S i、 T F T ( Thin Fi l m Transi stor ) などを用いても良い。  Further, the semiconductor pellet 21 described in the above embodiment may be obtained from a silicon semiconductor wafer, or may be obtained from a gallium or arsenic semiconductor wafer. Further, SOI, GeSi, TFT (Thin Film Transistor) and the like may be used.
2  Two
5 産業上の利用可能性  5 Industrial applicability
以上のように、 本発明の半導体装置の製造方法は、 チップコンデンサやチップ 抵抗などのチップ部品と、 ベアチップ実装による半導体ペレッ トとを実装し、 か つ多数個取り基板を用いて組み立てるモジュール製品全般の製造方法に好適であ るとともに、 携帯用電話などの小形の携帯用電子機器に組み込むのに適し、 特に 薄形の携帯用電子機器に搭載する高周波モジュール （高周波電力増幅装置） に好 適である。  As described above, the method of manufacturing a semiconductor device according to the present invention is applied to a general module product in which chip components such as chip capacitors and chip resistors and a semiconductor pellet formed by bare chip mounting are mounted and assembled using a multi-cavity substrate. It is suitable for the manufacturing method of small-sized portable electronic devices such as mobile phones, and especially suitable for high-frequency modules (high-frequency power amplifiers) mounted on thin portable electronic devices. is there.

Claims

請 求 の 範 囲 The scope of the claims
1 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立てら れる半導体装置の製造方法であって、  1. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に配置して 前記受動素子用チップおよび前記能動素子用チップを前記配線基板に実装するェ 程と、  Disposing the passive element chip and the active element chip on the wiring board and mounting the passive element chip and the active element chip on the wiring board;
表面に認識マークが付されたキヤップを前記配線基板に取り付けて前記キヤッ プによつて前記受動素子用チップぉよび前記能動素子用チップを覆う工程とを有 することを特徴とする半導体装置の製造方法。  Attaching a cap having a recognition mark on its surface to the wiring board, and covering the passive element chip and the active element chip with the cap. Method.
2 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立てら れる半導体装置の製造方法であって、 2. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に配置して 前記受動素子用チップおよび前記能動素子用チップを前記配線基板に実装するェ 程と、  Disposing the passive element chip and the active element chip on the wiring board and mounting the passive element chip and the active element chip on the wiring board;
表面に認識マークが付されたキャップの前記認識マークの検査を行い、 前記検 査後、 良品のキャップを前記配線基板に取り付けて前記キャップによって前記受 動素子用チップおよび前記能動素子用チップを覆う工程とを有することを特徴と する半導体装置の製造方法。  The recognition mark of the cap having the recognition mark on the surface is inspected, and after the inspection, a non-defective cap is attached to the wiring board, and the passive element chip and the active element chip are covered with the cap. And a method for manufacturing a semiconductor device.
3 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立てら れる半導体装置の製造方法であって、  3. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
複数の前記配線基板が形成された多数個取り基板の前記配線基板に前記受動素 子用チップおよび前記能動素子用チップを配置して前記受動素子用チップおよび 前記能動素子用チッブを前記配線基板に実装する工程と、  The passive element chip and the active element chip are arranged on the wiring board of the multi-piece board on which the plurality of wiring boards are formed, and the passive element chip and the active element chip are mounted on the wiring board. Mounting process,
表面に認識マークが付されたキヤップを前記多数個取り基板の前記配線基板に 1つずつ取り付けて前記キヤップによって前記配線基板上の前記受動素子用チッ ブおよび前記能動素子用チップを覆う工程とを有することを特徴とする半導体装 置の製造方法。  Attaching a cap having a recognition mark on its surface to the wiring board of the multi-piece board one by one, and covering the passive element chip and the active element chip on the wiring board with the cap. A method for manufacturing a semiconductor device, comprising:
4 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立てら れる半導体装置の製造方法であって、 前記受動素子用チップおよび前記能動素子用チップを前記配線基板に配置して 前記受動素子用チップおよび前記能動素子用チップを前記配線基板に実装するェ 程と、 4. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board, Disposing the passive element chip and the active element chip on the wiring board and mounting the passive element chip and the active element chip on the wiring board;
キャップの表面に認識マークを付す工程と、  A process of attaching a recognition mark to the surface of the cap,
前記認識マークが付された前記キヤップを前記配線基板に取り付けて前記キヤ ップによって前記受動素子用チップおよび前記能動素子用チップを覆う工程とを 有し、  Attaching the cap provided with the recognition mark to the wiring board, and covering the passive element chip and the active element chip with the cap.
前記受動素子用チップおよび前記能動素子用チップの前記配線基板への実装と 、 前記キャップへの認識マーク付けと、 キャップ取り付けとを一貫処理で行うこ とを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device, comprising: mounting the passive element chip and the active element chip on the wiring board; attaching a recognition mark to the cap; and attaching the cap in an integrated process.
5 . 複数の配線基板が形成された多数個取り基板の前記配線基板に受動素子用チ ップおよび能動素子用チッブを実装して組み立てられる半導体装置の製造方法で あって、  5. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on the wiring board of a multi-piece board on which a plurality of wiring boards are formed,
検査済みの前記多数個取り基板の前記配線基板に前記受動素子用チップおよび 前記能動素子用チップを配置して前記受動素子用チップおよび前記能動素子用チ ップを良品の配線基板に実装する工程と、  Arranging the passive element chip and the active element chip on the inspected wiring board of the multi-piece substrate, and mounting the passive element chip and the active element chip on a non-defective wiring board; When,
キヤップを前記良品の配線基板のみに取り付けて前記キヤップによって前記受 動素子用チップおよび前記能動素子用チップを覆う工程とを有することを特徴と する半導体装置の製造方法。  Attaching a cap only to the non-defective wiring board, and covering the passive element chip and the active element chip with the cap.
6 . 複数の配線基板が形成された多数個取り基板の前記配線基板に受動素子用チ ップ搭載、 能動素子用チップ搭載、 半田リフロー、 ワイヤボンディ ング、 レジン 塗布、 認識マーク付け、 キャ ップ取り付けおよび基板切断の各処理を順次行って 組み立てられる半導体装置の製造方法であって、 検査済みの前記多数個取り基板 の前記配線基板に不良マークを付す工程を有し、 前記受動素子用チップ搭載以降 の前記各処理ごとに前記不良マークを認識して、 前記不良マークが付された前記 配線基板にはそれそれの前記処理を行わないことを特徴とする半導体装置の製造 方法。 6. Chip mounting for passive elements, chip mounting for active elements, solder reflow, wire bonding, resin coating, recognition marking, capping on the wiring board of the multi-cavity board with multiple wiring boards formed A method of manufacturing a semiconductor device which is assembled by sequentially performing each process of mounting and substrate cutting, comprising a step of attaching a defect mark to the wiring substrate of the inspected multi-cavity substrate, and mounting the chip for a passive element. A method of manufacturing a semiconductor device, comprising: recognizing the defective mark for each of the subsequent processes; and not performing the process on the wiring substrate to which the defective mark is attached.
7 . 複数の配線基板が形成された多数個取り基板の前記配線基板に受動素子用チ ップ搭載、 能動素子用チップ搭載、 半田リフロー、 ワイヤボンディ ング、 レジン 塗布、 認識マーク付け、 キャップ取り付けおよび基板切断の各処理を順次行って 組み立てられる半導体装置の製造方法であって、 7. Chip mounting for passive elements, chip mounting for active elements, solder reflow, wire bonding, resin on the wiring board of the multi-cavity board with multiple wiring boards formed A method of manufacturing a semiconductor device which is assembled by sequentially performing each process of coating, recognition marking, cap mounting, and substrate cutting,
前記各処理後にそれぞれ検査を行って工程不良品を認識して不良マークを付す 工程を有し、  After each of the above-described processes, a step of performing inspection and recognizing a defective process to mark a defect is provided,
前記受動素子用チップ搭載以降の各処理時に前記不良マークを認識して前記ェ 程不良品に対しては次工程の処理を行わないことを特徴とする半導体装置の製造 方法。  A method of manufacturing a semiconductor device, comprising: recognizing the defective mark at each processing after mounting the passive element chip; and not performing the next processing for the defective product.
8 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立てら れる半導体装置の製造方法であって、  8. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記配線基板の受動素子用チップ用端子に半田を印刷する工程と、  A step of printing solder on the passive element chip terminals of the wiring board,
前記半田印刷後、 前記配線基板の凹部に半田をポッティ ングによって塗布する 工程と、  After the solder printing, a step of applying solder to the recesses of the wiring board by potting,
前記受動素子用チップを前記配線基板に配置する工程と、  Arranging the passive element chip on the wiring board;
前記能動素子用チップを前記配線基板の前記凹部に配置する工程と、 半田リフローを行って前記受動素子用チップおよび前記能動素子用チップを前 記配線基板に半田接続によって実装する工程とを有することを特徴とする半導体 装置の製造方法。  Arranging the active element chip in the concave portion of the wiring board; and performing solder reflow to mount the passive element chip and the active element chip on the wiring board by solder connection. A method for manufacturing a semiconductor device, comprising:
9 . 請求の範囲第 8項記載の半導体装置の製造方法であって、 ポッティ ング用の ノズルから前記半田を吐出させる際に、 前記ノズルを前記配線基板内および隣接 する他の配線基板に対して最短距離で移動させて複数の前記配線基板の前記凹部 に前記半田を吐出させることを特徴とする半導体装置の製造方法。  9. The method for manufacturing a semiconductor device according to claim 8, wherein, when the solder is discharged from a potting nozzle, the nozzle is moved with respect to another wiring substrate in the wiring substrate and an adjacent wiring substrate. A method of manufacturing a semiconductor device, wherein the solder is discharged to the recesses of the plurality of wiring boards by moving the solder at a shortest distance.
1 0 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、  10. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記配線基板の受動素子用チップ用端子に半田を印刷する工程と、  A step of printing solder on the passive element chip terminals of the wiring board,
前記配線基板の凹部にポッティ ングにより半田を塗布する工程と、  Applying solder to the recesses of the wiring board by potting;
前記受動素子用チップを前記配線基板上に配置する工程と、  Disposing the passive element chip on the wiring board;
前記能動素子用チップを前記配線基板の前記凹部に配置する工程と、 半田リフローを行って前記受動素子用チップおよび前記能動素子用チップを前 記配線基板に半田接続によって実装する工程とを有することを特徴とする半導体 装置の製造方法。 Arranging the active element chip in the concave portion of the wiring board; and performing solder reflow to mount the passive element chip and the active element chip on the wiring board by solder connection. Semiconductor characterized by Device manufacturing method.
1 1 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、  1 1. A method of manufacturing a semiconductor device which can be assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記受動素子用チップを前記配線基板に配置する工程と、  Arranging the passive element chip on the wiring board;
前記受動素子用チップ配置後、 前記能動素子用チップを前記配線基板の凹部に 配置する工程と、  After disposing the passive element chip, disposing the active element chip in the recess of the wiring board;
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に半田接続 によって実装する工程とを有することを特徴とする半導体装置の製造方法。 Mounting the passive element chip and the active element chip on the wiring board by soldering.
1 2 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、 1 2. A method of manufacturing a semiconductor device which can be assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記受動素子用チップの前記配線基板への搭載を行う部品搭載装置に設けられ た複数の部品供給部のうち、 それぞれの部品供給部に収納された前記受動素子用 チップを部品供給部単位で前記配線基板に供給して配置する工程と、  Among the plurality of component supply units provided in the component mounting apparatus that mounts the passive element chip on the wiring board, the passive element chips stored in the respective component supply units are described in units of the component supply unit. A step of supplying and arranging the wiring board,
前記能動素子用チップを前記配線基板の凹部に配置する工程と、  Disposing the active element chip in a concave portion of the wiring board;
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に半田接続 によって実装する工程とを有することを特徴とする半導体装置の製造方法。 Mounting the passive element chip and the active element chip on the wiring board by soldering.
1 3 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、 1 3. A method of manufacturing a semiconductor device which can be assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記配線基板の受動素子用チップ用端子に形成された印刷半田パターンを認識 して前記印刷半田パターン上に前記受動素子用チップを配置する工程と、 前記能動素子用チップを前記配線基板の凹部に配置する工程と、  Recognizing the printed solder pattern formed on the passive element chip terminal of the wiring board and arranging the passive element chip on the printed solder pattern; and placing the active element chip in the recess of the wiring board. Arranging,
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に半田接続 によって実装する工程とを有することを特徴とする半導体装置の製造方法。 Mounting the passive element chip and the active element chip on the wiring board by soldering.
1 4 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、 14. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記受動素子用チップを前記配線基板に配置する工程と、  Arranging the passive element chip on the wiring board;
前記能動素子用チップの前記配線基板への搭載を行うペレツ ト搭載装置に設け られた複数のペレツ ト供給部のうち、 それそれのペレツ ト供給部に収納された前 記能動素子用チップをペレツ ト供給部単位で前記配線基板に供給して前記配線基 板の凹部に配置する工程と、 Among the plurality of pellet supply units provided in the pellet mounting device for mounting the active element chip on the wiring substrate, the active element chip stored in each of the pellet supply units is pelletized. To the wiring board in units of Placing in a recess of the plate;
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に半田接続 によって実装する工程とを有することを特徴とする半導体装置の製造方法。 Mounting the passive element chip and the active element chip on the wiring board by soldering.
1 5 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、 15. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
前記受動素子用チップを前記配線基板に配置する工程と、  Arranging the passive element chip on the wiring board;
前記配線基板の凹部の縁部を認識して前記凹部に前記能動素子用チップを配置 する工程と、  Recognizing an edge of a concave portion of the wiring board and disposing the active element chip in the concave portion;
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に半田接続 によって実装する工程とを有することを特徴とする半導体装置の製造方法。 Mounting the passive element chip and the active element chip on the wiring board by soldering.
1 6 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、 16. A method of manufacturing a semiconductor device, which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
複数の前記配線基板が分割用溝部によって区画形成された多数個取り基板の前 記配線基板に前記受動素子用チップを配置する工程と、  A step of arranging the passive element chips on the wiring board of the multi-piece board in which the plurality of wiring boards are defined by the dividing grooves;
前記配線基板の凹部に前記能動素子用チップを配置する工程と、  Arranging the active element chip in a concave portion of the wiring board;
前記受動素子用チップおよび前記能動素子用チップを前記配線基板に半田接続 によって実装する工程と、  Mounting the passive element chip and the active element chip on the wiring board by soldering;
複数の前記配線基板の凹部に対してポッティ ングにより前記分割用溝部を避け て前記封止用樹脂を塗布して前記能動素子用チップを樹脂封止する工程とを有す ることを特徴とする半導体装置の製造方法。  Applying the sealing resin to the recesses of the plurality of wiring boards by potting so as to avoid the division grooves, and sealing the active element chip with the resin. A method for manufacturing a semiconductor device.
1 7 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、  17. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
複数の前記配線基板が形成された多数個取り基板の前記配線基板に前記受動素 子用チップおよび前記能動素子用チップを配置して前記受動素子用チップおよび 前記能動素子用チップを前記配線基板に実装する工程と、  The passive element chip and the active element chip are arranged on the wiring board of the multi-piece board on which the plurality of wiring boards are formed, and the passive element chip and the active element chip are mounted on the wiring board. Mounting process,
前記配線基板に係合可能なフックを支持するフック支持部が対向して設けられ たキヤップの一方の前記フック支持部を前記多数個取り基板のフック孔に斜めに 挿入して前記キャップを前記多数個取り基板に取り付ける工程とを有し、 前記キヤップによって前記多数個取り基板の前記配線基板上の前記受動素子用 チップおよび前記能動素子用チップを覆うことを特徴とする半導体装置の製造方 法。 One of the hook support portions of a cap provided with a hook support portion that supports hooks that can be engaged with the wiring board is obliquely inserted into a hook hole of the multi-piece board to attach the cap to the multi-piece board. Mounting the passive element on the wiring board of the multi-piece board by the cap. A method for manufacturing a semiconductor device, comprising covering a chip and the active element chip.
1 8 . 請求の範囲第 1 7項記載の半導体装置の製造方法であって、 前記多数個取 り基板に複数の前記キヤップを取り付ける際に、 前記キヤップの対向する前記フ ック支持部のうち、 隣接するキャップが取り付けられていない側に配置される前 記フック支持部から前記多数個取り基板の前記フック孔に挿入して前記キヤップ を前記多数個取り基板に取り付けることを特徴とする半導体装置の製造方法。 18. The method for manufacturing a semiconductor device according to claim 17, wherein when attaching the plurality of caps to the multi-piece substrate, the plurality of hook support portions of the cap facing each other. A semiconductor device, wherein the cap is attached to the multi-piece substrate by inserting the hook into the hook hole of the multi-piece board from the hook support portion arranged on the side where the adjacent cap is not attached. Manufacturing method.
1 9 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、 1 9. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
複数の前記配線基板が形成された多数個取り基板の前記配線基板に前記受動素 子用チップおよび前記能動素子用チップを配置して前記受動素子用チップおよび 前記能動素子用チップを前記配線基板に実装する工程と、  The passive element chip and the active element chip are arranged on the wiring board of the multi-piece board on which the plurality of wiring boards are formed, and the passive element chip and the active element chip are mounted on the wiring board. Mounting process,
前記配線基板に係合可能なフックを支持するフック支持部が対向して設けられ たキャップの一方の前記フック支持部を前記多数個取り基板のフック孔に斜めに 挿入する工程と、  A step of obliquely inserting one of the hook support portions of the cap provided with a hook support portion for supporting a hook engageable with the wiring board into a hook hole of the multi-piece board;
前記フック孔に挿入した前記一方のフック支持部に対して前記配線基板によつ て荷重を付与して前記一方のフック支持部を他方のフック支持部から離れる方向 にその弾性領域内で橈ませて前記他方のフック支持部のフックを前記多数個取り 基板の他のフック孔上に配置する工程と、  A load is applied by the wiring board to the one hook support inserted into the hook hole, and the one hook support is bent in a direction away from the other hook support within its elastic region. Disposing the hooks of the other hook support portion on the other hook holes of the multi-piece substrate,
前記他のフック孔に前記他方のフック支持部を挿入する工程と、  Inserting the other hook support into the other hook hole;
前記配線基板による荷重の付与を開放して前記フックおよび前記他のフックを 前記配線基板に係合させて前記キヤップを前記多数個取り基板に取り付ける工程 とを有することを特徴とする半導体装置の製造方法。  Releasing the application of the load by the wiring board, engaging the hook and the other hooks with the wiring board, and attaching the cap to the multi-piece board. Method.
2 0 . 配線基板に受動素子用チップおよび能動素子用チップを実装して組み立て られる半導体装置の製造方法であって、  20. A method for manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element on a wiring board,
選別された前記配線基板に前記受動素子用チップを配置する工程と、 選別された前記能動素子用チップを前記配線基板の凹部に配置する工程と、 前記受動素子用チップおよび前記能動素子用チップを前記配線基板に半田接続 によって実装する工程とを有し、 前記半導体装置の特性が許容範囲に入るようにそれそれに選別された前記配線 基板と前記能動素子用チップとを組み合わせて実装することを特徴とする半導体 装置の製造方法。 Arranging the passive element chip on the selected wiring board; arranging the selected active element chip in a recess of the wiring board; and arranging the passive element chip and the active element chip. Mounting on the wiring board by solder connection, A method of manufacturing a semiconductor device, comprising: combining and mounting the wiring substrate and the active element chip selected so that the characteristics of the semiconductor device fall within an allowable range.
PCT/JP2000/000828 2000-02-15 2000-02-15 Method for manufacturing semiconductor device WO2001061744A1 (en)

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PCT/JP2000/000828 WO2001061744A1 (en) 2000-02-15 2000-02-15 Method for manufacturing semiconductor device
AU2000224628A AU2000224628A1 (en) 2000-02-15 2000-02-15 Method for manufacturing semiconductor device
TW089106119A TW550766B (en) 2000-02-15 2000-03-31 Manufacturing method semiconductor device
CNB018033148A CN1222036C (en) 2000-02-15 2001-02-15 Semiconductor device fabrication method and device thereof
US10/129,305 US6852553B2 (en) 2000-02-15 2001-02-15 Semiconductor device fabrication method and semiconductor device fabrication apparatus
KR1020027010498A KR100689129B1 (en) 2000-02-15 2001-02-15 Semiconductor device fabrication method and semiconductor device fabrication device
AU32308/01A AU3230801A (en) 2000-02-15 2001-02-15 Semiconductor device fabrication method and semiconductor device fabrication device
PCT/JP2001/001091 WO2001061754A1 (en) 2000-02-15 2001-02-15 Semiconductor device fabrication method and semiconductor device fabrication device
US10/983,689 US6946306B2 (en) 2000-02-15 2004-11-09 Method of manufacturing a semiconductor device and a fabrication apparatus for a semiconductor device
US11/178,423 US20050250254A1 (en) 2000-02-15 2005-07-12 Method of manufacturing a semiconductor device and a fabrication apparatus for a semiconductor device

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Publication number Priority date Publication date Assignee Title
WO2016103791A1 (en) * 2014-12-26 2016-06-30 シャープ株式会社 Cap mounting method and cap mounting apparatus for semiconductor element package

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Publication number Priority date Publication date Assignee Title
JPH0653342A (en) * 1992-07-29 1994-02-25 Toshiba Corp Semiconductor device
JPH09252011A (en) * 1996-01-12 1997-09-22 Toshiba Corp Lid mounting apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653342A (en) * 1992-07-29 1994-02-25 Toshiba Corp Semiconductor device
JPH09252011A (en) * 1996-01-12 1997-09-22 Toshiba Corp Lid mounting apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016103791A1 (en) * 2014-12-26 2016-06-30 シャープ株式会社 Cap mounting method and cap mounting apparatus for semiconductor element package
JPWO2016103791A1 (en) * 2014-12-26 2017-08-31 シャープ株式会社 Cap mounting method and cap mounting apparatus for semiconductor device package

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