WO2001039248A3 - Kontakt für grabenkondensator einer dram zellanordnung - Google Patents

Kontakt für grabenkondensator einer dram zellanordnung Download PDF

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Publication number
WO2001039248A3
WO2001039248A3 PCT/DE2000/003987 DE0003987W WO0139248A3 WO 2001039248 A3 WO2001039248 A3 WO 2001039248A3 DE 0003987 W DE0003987 W DE 0003987W WO 0139248 A3 WO0139248 A3 WO 0139248A3
Authority
WO
WIPO (PCT)
Prior art keywords
transition
read
contact
buried strap
cell arrangement
Prior art date
Application number
PCT/DE2000/003987
Other languages
English (en)
French (fr)
Other versions
WO2001039248A2 (de
WO2001039248A8 (de
Inventor
Herbert Benzinger
Frank Richter
Original Assignee
Infineon Technologies Ag
Herbert Benzinger
Frank Richter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Herbert Benzinger, Frank Richter filed Critical Infineon Technologies Ag
Priority to JP2001540819A priority Critical patent/JP2003515922A/ja
Priority to KR1020027006639A priority patent/KR20020073339A/ko
Publication of WO2001039248A2 publication Critical patent/WO2001039248A2/de
Publication of WO2001039248A3 publication Critical patent/WO2001039248A3/de
Publication of WO2001039248A8 publication Critical patent/WO2001039248A8/de
Priority to US10/156,540 priority patent/US6750509B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

Die Erfindung betrifft eine DRAM Zellanordnung, bei welcher jeweils eine Speicherzelle (1) einen Speicherkondensator (2) und einen Auslesetransistor (3) aufweist. Zum Anschluss an den Auslesetransistor wird durch Ausdiffusion von Dotierstoffen aus der Elektrode des Speicherkondensators (2) ein Buried Strap Kontakt (11) erzeugt. Der Buried Strap Kontakt (11) ist durch die Implantationen (12) des Source/Drain-Gebietes (5) des Auslesetransistors (3) überlagert, so dass die Implantationen (12) des Source/Drain-Gebietes (5) die Grenze der Raumladungszone eines p/n-Übergangs der Speicherzelle (1) bilden. Dadurch wird erreicht, dass die Generationszentren und Defekte in einem Buried Strap Kontakt mehr als eine Diffusionslänge für Minoritätsladungsträger von der Raumladungszone eines p/n-Überganges entfernt sind. Somit rekombinieren derartige Minoritätsladungsträger bevor diese den p/n-Übergang erreichen können und sind daher elektrisch unwirksam. Dies bedeutet eine erhebliche Verringerung der Leckströme über den p/n-Übergang und damit ei Erhöhung der Retentionzeit.
PCT/DE2000/003987 1999-11-26 2000-11-14 Kontakt für grabenkondensator einer dram zellanordnung WO2001039248A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001540819A JP2003515922A (ja) 1999-11-26 2000-11-14 Ｄｒａｍセル構造におけるトレンチコンデンサーのための接続部
KR1020027006639A KR20020073339A (ko) 1999-11-26 2000-11-14 디램 셀 배열의 트렌치 캐패시터를 위한 컨택트
US10/156,540 US6750509B2 (en) 1999-11-26 2002-05-28 DRAM cell configuration and method for fabricating the DRAM cell configuration

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19957123A DE19957123B4 (de) 1999-11-26 1999-11-26 Verfahren zur Herstellung einer Zellenanordnung für einen dynamischen Halbleiterspeicher
DE19957123.6 1999-11-26

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/156,540 Continuation US6750509B2 (en) 1999-11-26 2002-05-28 DRAM cell configuration and method for fabricating the DRAM cell configuration

Publications (3)

Publication Number Publication Date
WO2001039248A2 WO2001039248A2 (de) 2001-05-31
WO2001039248A3 true WO2001039248A3 (de) 2002-02-28
WO2001039248A8 WO2001039248A8 (de) 2002-03-28

Family

ID=7930539

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/003987 WO2001039248A2 (de) 1999-11-26 2000-11-14 Kontakt für grabenkondensator einer dram zellanordnung

Country Status (6)

Country Link
US (1) US6750509B2 (de)
JP (1) JP2003515922A (de)
KR (1) KR20020073339A (de)
DE (1) DE19957123B4 (de)
TW (1) TW495925B (de)
WO (1) WO2001039248A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001083520A2 (en) * 2000-05-02 2001-11-08 Theravance,Inc Polyacid glycopeptide derivatives
DE10128211C1 (de) 2001-06-11 2002-07-11 Infineon Technologies Ag Speicher mit einer Speicherzelle, umfassend einen Auswahltransistor und einen Speicherkondensator sowie Verfahren zu seiner Herstellung
DE10131709B4 (de) * 2001-06-29 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung einseitiger Buried-Straps
DE10228547C1 (de) * 2002-06-26 2003-10-30 Infineon Technologies Ag Verfahren zur Herstellung eines vergrabenen Strap-Kontakts in einer Speicherzelle
US6818534B2 (en) * 2002-08-19 2004-11-16 Infineon Technologies Richmond, Lp DRAM having improved leakage performance and method for making same
US7015091B1 (en) * 2004-11-18 2006-03-21 Promos Technologies, Inc. Integration of silicon carbide into DRAM cell to improve retention characteristics
US9059030B2 (en) 2011-10-07 2015-06-16 Micron Technology, Inc. Memory cells having capacitor dielectric directly against a transistor source/drain region
US9111781B2 (en) * 2012-02-24 2015-08-18 Infineon Technologies Ag Trench capacitors and methods of forming the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555520A (en) * 1993-12-03 1996-09-10 Kabushiki Kaisha Toshiba Trench capacitor cells for a dram having single monocrystalline capacitor electrode
JPH11121710A (ja) * 1997-10-09 1999-04-30 Fujitsu Ltd 半導体装置及びその製造方法
EP0920059A2 (de) * 1997-11-28 1999-06-02 Siemens Aktiengesellschaft Speicherzellenanordnung und Verfahren zu deren Herstellung
JPH11168186A (ja) * 1997-12-03 1999-06-22 Toshiba Corp 半導体記憶装置およびその製造方法
US5926707A (en) * 1995-12-15 1999-07-20 Samsung Electronics Co., Ltd. Methods for forming integrated circuit memory devices having deep storage electrode contact regions therein for improving refresh characteristics

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
JP2994110B2 (ja) * 1991-09-09 1999-12-27 株式会社東芝 半導体記憶装置
JP3480745B2 (ja) * 1993-09-16 2003-12-22 株式会社東芝 半導体装置の製造方法
US5936271A (en) * 1994-11-15 1999-08-10 Siemens Aktiengesellschaft Unit cell layout and transfer gate design for high density DRAMs having a trench capacitor with signal electrode composed of three differently doped polysilicon layers
US5543348A (en) * 1995-03-29 1996-08-06 Kabushiki Kaisha Toshiba Controlled recrystallization of buried strap in a semiconductor memory device
US5827765A (en) * 1996-02-22 1998-10-27 Siemens Aktiengesellschaft Buried-strap formation in a dram trench capacitor
US5981332A (en) * 1997-09-30 1999-11-09 Siemens Aktiengesellschaft Reduced parasitic leakage in semiconductor devices
JP2000058780A (ja) * 1997-12-02 2000-02-25 Toshiba Corp 半導体装置及びその製造方法
US6265741B1 (en) * 1998-04-06 2001-07-24 Siemens Aktiengesellschaft Trench capacitor with epi buried layer
US5945704A (en) * 1998-04-06 1999-08-31 Siemens Aktiengesellschaft Trench capacitor with epi buried layer
US5945707A (en) * 1998-04-07 1999-08-31 International Business Machines Corporation DRAM cell with grooved transfer device
US6440794B1 (en) * 1999-05-28 2002-08-27 International Business Machines Corporation Method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555520A (en) * 1993-12-03 1996-09-10 Kabushiki Kaisha Toshiba Trench capacitor cells for a dram having single monocrystalline capacitor electrode
US5926707A (en) * 1995-12-15 1999-07-20 Samsung Electronics Co., Ltd. Methods for forming integrated circuit memory devices having deep storage electrode contact regions therein for improving refresh characteristics
JPH11121710A (ja) * 1997-10-09 1999-04-30 Fujitsu Ltd 半導体装置及びその製造方法
EP0920059A2 (de) * 1997-11-28 1999-06-02 Siemens Aktiengesellschaft Speicherzellenanordnung und Verfahren zu deren Herstellung
JPH11168186A (ja) * 1997-12-03 1999-06-22 Toshiba Corp 半導体記憶装置およびその製造方法
US6204527B1 (en) * 1997-12-03 2001-03-20 Kabushiki Kaisha Toshiba Semiconductor memory device and method for producing same

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"SUBSTRATE PLATE TRENCH DRAM CELL WITH AN INCREASED BACKGROUND DOPING (HALO) SURROUNDING THE STRAP REGION", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 37, no. 10, 1 October 1994 (1994-10-01), pages 341 - 342, XP000475688, ISSN: 0018-8689 *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 09 30 July 1999 (1999-07-30) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 11 30 September 1999 (1999-09-30) *

Also Published As

Publication number Publication date
KR20020073339A (ko) 2002-09-23
DE19957123B4 (de) 2006-11-16
DE19957123A1 (de) 2001-06-07
US6750509B2 (en) 2004-06-15
WO2001039248A2 (de) 2001-05-31
US20020163842A1 (en) 2002-11-07
WO2001039248A8 (de) 2002-03-28
TW495925B (en) 2002-07-21
JP2003515922A (ja) 2003-05-07

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