WO2001033631A1 - Boitier pour dispositif haute frequence - Google Patents

Boitier pour dispositif haute frequence Download PDF

Info

Publication number
WO2001033631A1
WO2001033631A1 PCT/JP2000/007498 JP0007498W WO0133631A1 WO 2001033631 A1 WO2001033631 A1 WO 2001033631A1 JP 0007498 W JP0007498 W JP 0007498W WO 0133631 A1 WO0133631 A1 WO 0133631A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
package
frequency
conductor
cap member
Prior art date
Application number
PCT/JP2000/007498
Other languages
English (en)
Japanese (ja)
Inventor
Masakiyo Horioka
Yoshihisa Okumura
Kunio Tochi
Makoto Aoki
Kiyoshi Mizushima
Original Assignee
Nikko Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikko Company filed Critical Nikko Company
Priority to AU79587/00A priority Critical patent/AU7958700A/en
Publication of WO2001033631A1 publication Critical patent/WO2001033631A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a high-frequency element package, a method for manufacturing the same, and a method for packaging a high-frequency element.
  • High-frequency semiconductors such as surface acoustic wave (SAW) filters or MMICs (Microwave Monolithic Integrated Circuits) and GaAsFETs are indispensable for such high-frequency devices. Is being developed and improved.
  • a high-frequency element is hermetically sealed in dry air or an inert gas such as nitrogen or a rare gas using a hollow ceramic package.
  • an inert gas such as nitrogen or a rare gas
  • a hermetic sealing structure a structure in which a high-frequency element is sealed in a metal case is known.
  • the use of a metal case or the like is limited because it is expensive and it is difficult to reduce the size and weight.
  • a structure is also known in which a high-frequency element is mounted on a substrate, and then a lid made of ceramic, metal, or the like is bonded to the substrate using solder, low-melting glass, thermosetting resin, or the like.
  • the laminated ceramic package 60 has a laminated structure in which the central portion is a single layer and the periphery is two to three layers, and the latter forms a stepped wall.
  • the high-frequency semiconductor element (bare chip) 61 is mounted in a concave part (on the first layer in the figure) in the center of the package, and is wire-bonded to the electrode or conductor line 62 formed on the shelf (the second layer).
  • Connected by A third layer is further provided on the edge of the package, and the lid 65 (usually a metal lid) is seam-welded to the element via, for example, a seal ring 64, thereby affecting the element. Airtight sealing is realized without any problems, and high airtightness is maintained inside.
  • the laminated structure may have two layers, or may have four or more layers.
  • the signal transmission line 62 such as a strip line formed on the shelf is connected to external electrodes 66 provided on the side and bottom surfaces of the package 60 (FIG. 10 (a)), Are connected to the external electrodes 66 by filling vias or through holes 67 provided through the bottom surface of the substrate (FIG. 10 (b)). Thereby, input / output of a high-frequency signal to / from the element (bare chip) 61 is performed.
  • a conductive paste is printed on a ceramic green sheet formed in a predetermined shape in a thick film, these sheets are laminated, cut into individual pieces, and then, It is formed by firing the electrodes and conductor lines simultaneously with firing the green sheet. Therefore, (1) the mounting area of the element, (2) the internal electrode for mounting the element (bare chip), the external electrode for connecting the packaged element module to the external circuit, and the connection between the internal and external electrodes It has the advantage that the conductor line and (3) the support for the sealing lid can be formed simultaneously by applying a conventional lamination technique.
  • the impedance given by the parasitic capacitance increases as the frequency increases, and the influence increases. This can be corrected by a capacitor or the like, but in a conventional stacked package, it is difficult to correct the impedance with high accuracy because the parasitic capacitance differs for each package. In addition, the mounting of the correction capacity further complicates the package structure. Further, in the conventional package manufacturing method and packaging method, a package piece of a millimeter order is baked, an element is mounted on the package piece, wire-bonded, and a lip is welded. In other words, it was necessary to handle micro ceramic packages and semiconductor chips, etc., and miniaturization of components had increased production costs.
  • the inspection requires the manufacture of jigs and inspection pads for each product. Furthermore, in order to automate the inspection, an inspection device including a large-scale positioning device suitable for handling minute components is required. In addition, due to the inability to configure the jig, it was practically difficult to perform temperature characteristics and other precise inspections on individual packages.
  • An object of the present invention is to solve the above-described problems in the high-frequency package according to the related art, which can be manufactured and inspected at low cost, and has a millimeter wave band (20 to 100 GH).
  • An object of the present invention is to provide a high-performance package structure that can be used even in a high frequency region including z).
  • Another object of the present invention is to provide an inexpensive and efficient manufacturing method and a packaging method for such a high-performance high-frequency package. Disclosure of the invention
  • the present inventors have studied the above-mentioned problems in a package having a multilayer substrate structure, which has been conventionally considered to be necessary for hermetic sealing at a required level for a high-frequency element. Since the formation of the electrodes and conductor lines by firing is performed simultaneously with the firing of the substrate material, dimensional fluctuations and non-uniformity of the conductors due to shrinkage of firing of the substrate material are inevitable, which causes signal degradation in the high frequency band. It was also concluded that this was one of the main causes of the parasitic capacitance variation (non-uniformity) from package to package.
  • the electrodes necessary for mounting the element, the input / output conductor lines and the Z or circuit are provided on the fired ceramic substrate, and the cured organic polymer material or inorganic material is provided.
  • a sealing auxiliary layer made of a material By bonding the cap-type lid with an adhesive via a sealing auxiliary layer made of a material, a high-level hermetic seal is achieved, and a package exhibiting excellent characteristics in a high frequency band can be realized.
  • a high-precision line width and line length of the conductor line can be obtained. Therefore, by using a strip line for impedance correction, stable impedance can be obtained even at high frequencies.
  • a plurality of package regions are provided on the fired substrate, and a package substrate structure according to the above (1) to (2) is formed for each region, and element mounting and hermetic sealing with a cap member are performed. After that, the process of dividing into individual pieces is adopted to improve the efficiency of the manufacturing process. In addition, by applying the semiconductor A8 inspection technology to such an assembled substrate, the inspection efficiency is improved-advanced ( Precision inspection and temperature characteristic inspection), and completed the present invention.
  • the present invention provides the following high-frequency element package, a method of manufacturing the same, and a method of packaging the high-frequency element.
  • a package for a high-frequency element including a cap member, wherein the ceramic substrate includes: an internal electrode for mounting the element formed after firing of the substrate material; an external electrode; a conductor line connecting between the electrodes; and an element mounting area.
  • a sealing auxiliary layer made of a cured body of an organic polymer material or an inorganic material provided in a shape compatible with the end face of the cap member between the substrate and the portion; After being electrically connected to the cap member A package for a high-frequency element, wherein the package is hermetically sealed by adhering to a cured organic polymer material layer with an adhesive.
  • the element is a GaAs FET, and the conductor lines connected to the gate (G) and the drain (D) are on a straight line, and the distributed constant line connected to the source (s) is orthogonal to this.
  • a plurality of element mounting regions connected by conductor lines are provided on a substrate, and the whole including these elements or one or more of these elements that need to be hermetically sealed by the cap member.
  • FIGS. 1 (a) and 1 (b) are a plan view and a cross-sectional view, respectively, schematically showing the substrate structure of the high-frequency element package of the present invention.
  • 2 (a) and 2 (b) are a plan view and a cross-sectional view, respectively, which schematically show the sealing structure of the high-frequency element package of the present invention.
  • FIG. 3 is a perspective view schematically showing a packaging process of a high-frequency device according to the present invention.
  • FIG. 4 is a plan view schematically showing the structures of the strip line and the coplanar line.
  • FIG. 5 is a plan view schematically showing a conventional microphone opening X structure.
  • 6 (a) and 6 (b) are a plan view schematically showing the micro X structure according to the present invention and a side view excluding a part of the sealing structure, respectively.
  • FIG. 7 (a) is a side view schematically showing the structure of the distributed constant type GaAsFET package according to the present invention (however, excluding a part of the sealing structure).
  • FIG. 7 (b) and FIG. (c) is a plan view schematically showing two types of structures corresponding to (a).
  • FIG. 8 is a circuit diagram showing an example of a balanced-unbalanced conversion circuit.
  • FIG. 9 is a plan view schematically showing the structure of a package with a built-in balanced-unbalanced conversion circuit according to the present invention.
  • FIG. 10 is a cross-sectional view schematically showing a structure of a conventional high-frequency element package as ⁇ and (b) according to a difference in a connection structure with an external electrode.
  • FIG. 11 is an explanatory view schematically showing a collective substrate packaging process for a high-frequency device according to the present invention.
  • FIG. 12 is an explanatory view schematically showing a packaging substrate packaging process of the high-frequency device according to the present invention, following FIG.
  • FIG. 13 is an explanatory diagram that schematically shows a packaging substrate packaging process of the high-frequency device according to the present invention, following FIG. 12.
  • FIG. 14 is a schematic diagram showing a comparison between a 10 GHz band oscillator according to the prior art and a 10 GHz band oscillator according to the present invention.
  • FIG. 1 and 2 show the basic structure of the high-frequency element package 10 of the present invention.
  • FIG. 1 schematically shows the package substrate 1 before sealing (FIG. 1): a plan view showing an element mounting surface.
  • FIG. 1 (b) is a cross-sectional view of the package substrate of FIG. 1 (a) taken along the line AA ′ in the figure), and
  • FIG. 2 is a state in which the element is sealed using a cap member 8. It is a top view and a sectional view.
  • Fig. 3 schematically shows the flow of manufacturing and packaging of this package.
  • the package substrate 1 of the present invention is used for performing input and output to and from the fired ceramic substrate having the element mounting area 2.
  • electrodes or conductor lines and Z or circuit inner electrode 3 for mounting bare chip, outer electrode 6 for package mounting and conductor line 4 and side electrode 5 connecting between them
  • a sealing auxiliary layer 7 made of a cured body of an organic polymer material or an inorganic material. Preferred Alternatively, the sealing auxiliary layer is subjected to a surface activation treatment.
  • the internal electrode 3 and the conductor line 4 may be integrated.
  • the high-frequency element 11 is mounted at the center of the element mounting area 2, and the electrodes 13 on the element surface and the package internal electrodes 3 are connected by bonding wires 12 (see FIG. Thereafter, the cap member 8 is sealed by bonding the cap member 8 to the sealing auxiliary layer 7 of the substrate using an adhesive 9 (corresponding to FIG. 3 (f)).
  • the sealing auxiliary layer 7 and the adhesive layer 9 are drawn to have the same width as the end face of the cap member, but the sealing layer composed of the sealing auxiliary layer 7 and the adhesive layer 9 is As long as the high-frequency characteristics are not affected, the substrate may have a larger spread on the substrate surface.
  • the electrodes and conductor lines are not affected by dimensional fluctuations caused by shrinkage of the substrate material due to firing shrinkage, so it is possible to incorporate high-level impedance adjustment and other functions using strip lines, etc. , And a high level of sealing can be realized.
  • FIGS. 1 and 2 shows the most basic embodiment of the present invention, and the shape of the substrate and the structure of the conductor line are changed as necessary.
  • the substrate structure, the cap member, and the adhesive layer, which are basic elements of the package of the present invention will be described in detail with reference to typical application examples.
  • the substrate structure in the package of the present invention includes a fired substrate (a fired ceramic substrate is simply referred to as a “ceramic substrate” unless otherwise noted) and the elements provided on the surface thereof. It includes electrodes, conductor lines, and Z or circuits for input and output of the I / O.
  • a conventional multilayer ceramic package also includes a structure in which ceramic is used as a substrate material and electrodes, conductor paths, and the like (hereinafter, also simply referred to as “electrodes”) are provided thereon.
  • electrodes electrodes
  • conventional multilayer ceramic packages as described above, A thick paste of conductive paste is printed on the green sheet and the electrodes are formed by firing the green sheet simultaneously with firing.Since shrinking of the green sheet is inevitable during firing, the parasitic capacitance of the package is reduced for each piece. different. This non-uniformity (variation) is mainly due to poor uniformity in the shrinkage of the electrodes co-fired in the production of the multilayer ceramic package, making it difficult to form electrodes with high precision.
  • the substrate material various ceramic materials can be used, but a material satisfying the following conditions is particularly preferable.
  • the element (bare chip) to be mounted must have the same coefficient of linear expansion.
  • alumina particularly 96 alumina containing 96% by weight of alumina
  • a dielectric material having a dielectric constant and a Q value higher than that of alumina may also be used.
  • lower inorganic dielectric Body materials can also be used.
  • the thickness of the substrate is selected according to the dimensions of the substrate and the required strength.
  • the dimensions and shape of the substrate are determined by the size of the element to be mounted.
  • the electrodes and the conductor lines for inputting and outputting to the substrate and the elements provided on the surface thereof include internal electrodes and packages for connection to the elements as shown in FIGS. 1 and 2. It includes external electrodes (including side electrodes) provided for surface mounting, and conductor lines connecting between the internal and external electrodes.
  • Electrodes and conductor lines can be formed by, for example, thick film printing. Further, in the present invention, since there is no step of “firing” after the formation of the electrode, a highly accurate electrode formation by thin film formation and other metallization methods can be used.
  • the conductor material may be a conventional one.
  • conductive paste for thick film such as Ag, Ag—Pt, Ag—Pd, Au, Cu, and Ni, and for thin film formation. Examples include, but are not limited to, Au, Cu, A and Ni, and the like. These methods may be combined.
  • an electroless plating for example, an electroless gold plating
  • Applying electroless gold plating has the effects of (1) improving wire bonding, (2) improving solderability, and (3) improving conductor resistance.
  • the internal and external electrode shapes may be the same as those of the conventional package.
  • 1 and 2 show the mode of electrically connecting the element and the package by bonding wires, but other connection structures such as a bump structure may be used, and the internal electrodes are shaped according to each connection structure.
  • FIGS. 1 and 2 show a mode of connection with the internal electrode-conductor line-side electrode-external electrode, but a filled through hole may be used instead of the side electrode.
  • a flat line strip line, Cross-trip lines, coplanar lines are typical applications.
  • a stripline can be formed by providing a conductor line with an appropriate line width on the surface of the substrate and providing ground (GND) on the backside of the substrate (Fig. 4 (a)).
  • the line width d is 0.641 ⁇ 01.
  • a strip line with a characteristic impedance of 50 ⁇ can be formed by providing a conductor line consisting of a t-force and GND on the entire back surface.
  • Fig. 4 (b) shows the structure of a coplanar waveguide. This is one in which conductor layers are provided on both sides of the transmission line in Fig. 4 (a). Although the figure shows a structure in which the conductor layers on both sides are connected to the GND layer on the back via a through hole, a structure without a GND layer on the back or a coplanar line structure with GND excluding through holes may be used. .
  • the coplanar waveguide has a problem that it is difficult to design, it is suitable at 10 GHz or more, and a characteristic satisfying practical use is obtained up to a frequency of 100 GHz or more.
  • FIG. 5 schematically shows a plan view of a conventional structure of an ultra-high frequency ceramic package 20 applied at 10 GHz or more called Micro X.
  • the element 21 mounted in the center is a GaAs FET bare chip with high electron mobility.
  • the substrate 22 on which the bare chip is mounted is a multilayer laminated substrate similar to that of FIG. 10 and the like.
  • Micro X a conductor line that connects to the gate, drain, and source terminals. , D, and S are arranged perpendicular to each other to suppress the parasitic capacitance.
  • These conductor lines are inner layer wiring inside the substrate and are generally connected to strip lines formed separately outside the chip mounting substrate (in the figure, they are shown as one integrated inside and outside the substrate). There is.)
  • the parasitic capacitance C does not disappear even if the terminals are orthogonal to each other to form the microphone opening X structure.
  • inductance L due to the bonding wire 23 connecting each electrode of the GaAsFET and the conductor line.
  • the uniformity of the parasitic capacitance C is poor because the shrinkage rate during firing is not uniform for each package. Since the bonding accuracy is high, the wire bonding itself can usually be formed with high uniformity.However, in the conventional laminated substrate structure, dimensional changes due to shrinkage of the inner wiring due to firing shrinkage are unavoidable. Non-uniformity (variation) also becomes a problem. When the frequency is 10 GHz or more, the frequency change of impedance due to C and L increases, and a frequency band in which an appropriate signal wave current is not applied to the semiconductor chip occurs. In Micro X, this problem is reduced by connecting to (micro) strip lines separately formed on the chip mounting substrate.
  • the connection structure between the electrodes on the element and these conductor lines is reduced. Tend to be complicated.
  • the parasitic capacitance C is not only uniform in each package, but also a highly accurate stripline (or coplanar type conductor). Wave line) can be built into the package for impedance correction. Examples are shown in Figs. These have conductor lines provided on the substrate, and can correct the inductance L and the parasitic capacitance C of the bonding wire with high accuracy.
  • the width and interval of the conductor wiring can be precisely controlled, it is possible to additionally provide a high-precision planar inductor on the substrate. Therefore, circuits having various functions can be provided on the surface by combining such a planar inductor and a capacitance element such as Z or a chip capacitance available at high precision on a substrate.
  • a circuit is a balanced-unbalanced conversion circuit.
  • balun a balanced-unbalanced conversion element
  • LNA low-noise amplifier
  • mixers that are driven by low voltages to achieve a wide dynamic range and high gain
  • Equilibration of the high-frequency circuit eliminates the need for MMICs such as power switch transistors and DC / DC converters for negative voltage generation, and eliminates the need for MMICs for mobile communications.
  • the wave circuit can be significantly reduced in size and cost.
  • the LNA is balanced in the example of the configuration of the mobile phone receiver from the antenna (ANT) to the low noise amplifier (LNA :) via the antenna switch (ANT-SW) and then to the SAW filter
  • the subsequent stage Either upgrade the SAW filter to a balanced type, or use a balanced converter between the LNA and the SAW filter.
  • the balun can be composed of a combination of an inductor and a capacitor, as shown in the equivalent circuit of FIG. 8, and in the present invention, by mounting the circuit shown in FIG. A package can be used (an example of this configuration will be described in detail in Embodiment 3).
  • an inductor electrode is formed on a fired substrate such as an alumina substrate, so that a highly accurate inductor electrode can be formed.
  • a high-performance circuit can be constructed by using a small, large-capacity chip capacitor with a high Q value. If necessary, the characteristic impedance may be adjusted using conductor lines.
  • the present invention can be applied to all circuits having high-frequency components that require hermetic sealing.
  • a high-frequency circuit including one or more GaAs FETs, SAW filters, or MMICs, it is possible to seal each of these high-frequency elements, two or more of them, or the entire circuit as described above. Is described in detail in Example 5.
  • the cap member functioning as a lid may have any shape and height so as to form a space having a size sufficient to accommodate the element when brought into close contact with the surface of the substrate. Also, it is sufficient if the protective member has sufficient strength.
  • Caps made of inorganic material, organic material, and metal can be used for sealing. Alumina, quartz glass, etc. made of inorganic material, plastic made of organic material Metals such as paints, epoxies, and the like include iohaku (Western white), phosphor bronze, and copper.
  • the high-frequency device will be surrounded by a conductive material, and almost perfect shielding can be obtained by grounding the cap to GND. Also, there is a high shielding effect without grounding.
  • a metal cap If a metal cap is used, it must be insulated from the conductor tracks on the substrate surface. Insulation between the metal cap and the conductor line can be achieved by providing an insulating layer between the cap and the conductor line by thick-film printing or the like. In the present invention, the sealing auxiliary layer also functions as an insulation layer.
  • a sealing auxiliary layer which is a cured body of the sealing auxiliary layer or an inorganic material layer is provided on a ceramic substrate having a region for mounting a high-frequency element, and a cap
  • a major feature is that the member is bonded to the sealing auxiliary layer with an adhesive to perform sealing.
  • an adhesive eliminates the need for a heat treatment at several hundred degrees Celsius, which is required when sealing with solder-glass frit. Also, by activating the surface of the sealing auxiliary layer prior to bonding, highly reliable bonding and sealing that can withstand repeated thermal expansion after mounting the element module can be realized.
  • the sealing method according to the present invention is used for sealing SAW filters, GaAs FETs, MMIC power amplifiers, etc., which are used in a high frequency or ultra-high frequency band, generate a large amount of heat, and have a high level of required moisture resistance. Must be adopted.
  • the sealing auxiliary layer is formed on the substrate in a shape compatible with the end surface of the cap member. Specifically, a polymer resin is printed and cured in the area including the joint with the cap member on the substrate, or an inorganic material layer is formed by thick-film printing or other methods and then fired and sealed. An auxiliary layer.
  • the organic polymer material that can be used as the sealing auxiliary layer in the present invention includes, as a main component, a resin having heat resistance, moisture resistance, and insulation properties, such as an epoxy resin, a phenol resin, and an epoxy phenol resin. It is preferable to use resin materials in which a curing agent, a reppelling agent, an antifoaming agent, an inorganic filler, and the like are dispersed in order to impart coatability such as screen printing to these materials.
  • the leveling agent or the defoaming agent include those containing silicone oil as a main component. However, when a silicone-based leveling agent or antifoaming agent is used, the amount added should be 0.01 to 2.0 wt. % Is preferably used.
  • the leveling agent is modified with epoxy. It is preferable to add the inorganic filler in consideration of the anchoring effect at the time of epoxy bonding, but in this case, use a filler with an average particle size of about 0.5 to 10 m suitable for screen printing. Is preferred.
  • the sealing auxiliary layer When the sealing auxiliary layer intersects with the wiring or the like on the substrate surface, which is printed on the substrate by a common method such as screen printing, the sealing auxiliary layer absorbs irregularities due to the conductive path on the substrate surface, and the cap member is made of metal.
  • the cap member In some cases, in order to ensure insulation from the wiring conductors on the board, cover the surfaces of the electrodes or conductor lines, that is, make them thicker than these conductor paths, and make the resin layer surface as a whole. The height must be even. This can be realized by adjusting the viscosity to an appropriate value with the above-mentioned additives and the like.
  • a layer having a thickness of about 10 to 50 may be used (the same applies to the case of an inorganic material described later).
  • the organic polymer layer is cured to form a sealing auxiliary layer.
  • the inorganic material that can be used as the sealing auxiliary layer is not particularly limited, and various inorganic glasses and oxides can be used. Among them, crystallized silica glass is preferred.
  • crystallized silica glass S i 0 2 - M G_ ⁇ one Z n O- A l 2 ⁇ 3 system, P b O-Z N_ ⁇ one B 2 ⁇ 3 - S i 0 2, and the like,
  • glass other than this may be a glass that precipitates microcrystals during sintering and does not contain lead.
  • Crystallized silica glass may have pinholes of about several meters, but no problem occurs if the thickness is about 10 to 20 m.
  • the sealing auxiliary layer Will overlap with part of the wiring conductor, but the plating layer formed by electroless plating, especially the Au plating layer surface, is chemically inert, and the adhesion between the conductor layer and the sealing auxiliary layer is reduced. I do. Therefore, it is necessary to form a sealing auxiliary layer before plating.
  • the glass component contains lead
  • the lead component elutes into the plating solution during the Au plating, and becomes a catalyst poison. In crystallized silica glass, such a situation does not occur, and it is considered that Au plating progresses smoothly and contributes to the improvement of characteristics.
  • the sealing auxiliary layer is bonded to the cap member.
  • the surface activation treatment of the sealing auxiliary layer includes various chemical or physical treatments for increasing the affinity with the adhesive. Among them, ultraviolet treatment and plasma treatment are preferred.
  • the ultraviolet treatment is performed by irradiating the surface of the sealing auxiliary layer with ultraviolet light.
  • UV irradiation The chemical affinity of the sealing auxiliary layer for the adhesive increases, and a high degree of hermetic sealing can be realized. Irradiation energy depends on the type of the sealing auxiliary layer and the like, but in the case of a polymer resin material, it may be generally within a range of 400 to 160 mJ. In general, if it exceeds 160 OmJ, the adhesive strength is rather lowered. In addition, the oxidation of the conductor thick film proceeds easily. On the other hand, a remarkable effect is not obtained below 40 OmJ. Usually, the range of 400 to 100 OmJ is preferable.
  • the wavelength of the irradiation ultraviolet rays is selected so as to include a wavelength range in which active points are formed in the cured polymer resin layer.
  • the energy irradiation amount is larger as long as it does not adversely affect the conductor layer and the like on the substrate surface.
  • Such ultraviolet irradiation can be performed using, for example, a low-pressure mercury lamp.
  • Plasma treatment is also preferable as the surface activation treatment of the sealing auxiliary layer in the present invention.
  • the plasma treatment is performed by applying a high-frequency AC voltage between electrodes filled with decompressed gas to generate a glow discharge between the electrodes and bringing the plasma of the gas component into contact with the substrate.
  • the plasma treatment removes the contaminant layer and promotes surface roughening and formation of Z or chemically active sites.
  • the substrate on which the above-mentioned sealing auxiliary layer is formed is placed in a plasma processing apparatus capable of reducing pressure, and the atmosphere in the apparatus is appropriately replaced with a plasma processing gas. Perform by applying.
  • the gas used for the plasma treatment is not particularly limited as long as it is non-oxidizing gas. Examples of such a gas include an inert gas such as helium, neon, and argon, and nitrogen. Argon is preferred.
  • the pressure of the processing gas is 1 mTorr to 1 O Torr, preferably 1 O mTorr to: L Torr, and more preferably about 100 to 300 mTorr.
  • the high-frequency power supply may have a frequency in the range of 1 to 100 MHz and a power of about 10 to 300 W.
  • the sealing auxiliary layer is a polymer material, it is preferably about 50 to 200 W, and when it is an inorganic material, it is preferably about 200 to 300 W.
  • the processing time depends on the type of the sealing auxiliary layer, but is usually in the range of 10 to 300 seconds. When an inorganic material is used, 3 to 5 minutes is preferable. If the processing time is too short, the effect of the processing will not be sufficiently exhibited. If the treatment time is too long, the etching effect of the plasma is exerted on the electrode and the conductor layer on the substrate surface, which is not preferable.
  • the adhesive is not limited as long as it has good adhesiveness to the above-mentioned cured surface and excellent airtightness.
  • examples of such an adhesive include an epoxy-based adhesive and an epoxy-phenol-based adhesive.
  • the high-frequency device of the present invention can be manufactured by a method schematically shown in FIG.
  • the present invention further provides a manufacturing method using a collective substrate.
  • perforations (through holes) 72 are formed at predetermined positions of the inorganic insulator substrate 71 (FIG. 11 (a)).
  • the formation of through-holes is possible in any way. For example, drilling with a single laser beam, drilling with a drill, and the like can be given. It may be fired after punching on a ceramic green sheet.
  • a conductor is printed, filled and Z or plated in the through hole 72 to form electrodes and conductor lines 73 on the surface of the substrate and electrode terminals on the back surface (not shown) of the substrate (FIG. 11).
  • the formation of the electrodes and the like is similar to the case where the individual substrate is used. Also, for example, when a coplanar line is used, the side conductor layer is formed, when a distributed constant type is used, a GND layer on the back side is formed, or when an additional circuit is mounted, an inductor pattern is also formed. Good.
  • a sealing auxiliary layer 74 is formed as in the case of the individual substrate (FIG. 12 (a)), and the surface is activated (FIG. 12 (b)).
  • the module is separated into individual modules packaged on the substrate surface. Separation into individual chips can be performed, for example, by a conventional method such as sawing, but by forming a shallow dividing line on the substrate and applying a deformation force along the dividing line after resin sealing.
  • the substrate may be divided. It is preferable to divide the through hole along the through hole, and the divided through hole can be used as a conductive portion to the back surface or a side electrode.
  • the manufacturing method of the present invention further provides a method for further improving the efficiency of the entire package manufacturing process by inspecting the semiconductor device after being formed as a collective substrate and before dividing it into individual pieces (this method is described in the next section).
  • Packaging method This will be described in detail in the description of the method. ).
  • a packaging method for a high-frequency device according to the present invention can be realized using the above-described package.
  • an electronic component is mounted on a ceramic substrate having a sealing auxiliary layer, and the electronic component is sealed by bonding a cap member.
  • the package structure is as described above.
  • Examples of the mounting method include a resin bonding method using a conductive paste or a bonding method using brazing or the like. After bonding, for example, flux cleaning is performed using an alternative chlorofluorocarbon (HFCFC), and electrical bonding between the electronic component and the thick film substrate is performed by wire bonding or the like.
  • HFCFC chlorofluorocarbon
  • the wire length is as short as possible and the wire thickness is large.
  • a gold wire having a diameter of 10 to 50; m, preferably 15 to 30 / m is used.
  • the environmental conditions (especially humidity) during the sealing process are important. For example, air dehumidified by activated alumina etc. with a dew point of 140 ° C or less is blown, and the dew point of the working area is 120 ° C or less.
  • the sealing operation is carried out under the condition maintained at.
  • the adhesive strength of the ceramic lid of the sample prepared in this way is higher than that of the sample with a low melting point glass that is generally used for conventional oscillators, etc. Will be much stronger.
  • a method of packaging an element using a collective substrate that is, a step of forming a plurality of package substrate regions by vertically and horizontally providing dividing lines including through holes on a ceramic substrate; Step of forming a conductive path for conducting the front and back surfaces of the substrate through the through hole: connecting the internal electrode for mounting the element and the internal electrode to the conductive path inside the through hole on the surface on the element mounting side in each substrate area.
  • the procedure up to the mounting of the element is the same as that described with reference to FIGS. 11 and 12. Thereafter, the element is mounted and the connection is performed by wire bonding (FIG. 13 (a)). After wire bonding, the substrate surface is sealed with a cap member 77, and then separated into individual packaged modules (FIG. 13 (c)). For separation into individual chips, the substrate may be divided by forming a shallow dividing line on the substrate and applying a deforming force along the dividing line after resin sealing. By dividing along the through hole 72, the inner surface of the through hole 72 can be used as a conductive portion to the back surface or a side electrode 79.
  • the aggregate substrate is divided in a state where the edge of each substrate region is structurally reinforced by bonding the cap member, so that the stress at the time of division tends to concentrate on the division line, and the division of each substrate region is performed. Can be realized more reliably.
  • the manufacturing method or the packaging method of the present invention it is possible to realize an efficient method for inspecting a high-frequency package or a packaged module.
  • Wafer probers are widely used for precision measurement, intermediate inspection, and shipping inspection of semiconductor products, and include a test head, a probe card, and a stage that can be moved in the XY and vertical directions.
  • the probe card is a replaceable part that is attached to the test head and includes a plurality of wires and a plurality of probe pins electrically connected to the wires.
  • the semiconductor wafer before being diced is placed on a stage, and the probe pins are brought into contact with the electrodes of the semiconductor products collectively formed on the wafer, so that a current flowing between the electrodes is obtained. Is measured, and defective products are identified by inspection of electrical characteristics.
  • the inspection method of the present invention is known as an inspection apparatus for a semiconductor wafer, a wafer probe which has not been used for inspection of a high-frequency package and / or a packaged high-frequency element has been disclosed. It is characterized in that it is used for inspection. Specifically, the above-mentioned collective substrate is placed on the stage of a wafer probe with the element mounting area side down, and probe pins are brought into contact with the electrodes on the back surface of the substrate to inspect individual high-frequency elements. . Before mounting the device, various inspections can be performed on the front side of the board.
  • a semiconductor wafer inspection method using a wafer prober can be used almost as it is.
  • Wafer prober inspection processing capacity does not exceed 1 second per product area even in precision measurement.
  • Multiple high-frequency devices (or packages) may be inspected simultaneously by applying a multi-prober. In this case, the inspection time per product area is reduced to 1/2 to 1/3 second.
  • the calibration up to the probe tip can be performed by using the calibration substrate.
  • the intrinsic characteristics of the product can be accurately measured. It is also easy to inspect temperature characteristics. Quality assurance regarding temperature characteristics has always been a major problem with ceramic electronic components. Major changes, such as maintenance, were necessary and were not realistic.
  • a wafer prober is a small device that can be carried around and can be calibrated at the probe level such as S-LT (Short-Open-Load-Through) calibration. Precise measurement can be easily performed.
  • the high-frequency element package of the present invention can be applied to a wide range of high-frequency elements of several tens of MHz to 100 GHz.
  • Electrodes and conductive lines are formed on a 0.64 mm thick 5 mm square 96 alumina substrate by thick film printing using a thick film conductor paste of Ag-Pd alloy (Fig. 3 (b)).
  • silicone oil content 0.6 wt
  • silica fine powder with an average particle size of 5 zm as inorganic filler and epoxy as hardener
  • BPA bisphenol A resole type phenolic resin
  • an adhesive containing bisphenol A-type epoxy resin as the main component is adjusted in advance, and the surface tension of the adhesive before bonding is equal to the surface tension of the resin on the surface to be bonded.
  • Epoxy adduct (curing agent), inorganic fine particles, and varnish are added and ripened so that the state can be realized, and the coating is applied to the surface to be bonded.
  • Alumina ceramic with a thickness (wall thickness) of 0.5 mm in dry air Sealing was performed by bonding a cap made of glass (Fig. 3 ( ⁇ )).
  • the above package was kept in an environment of 12 It :, 2 atm, and 100% humidity in an environmental tester, and the characteristic degradation was evaluated using the transmission characteristics (201 ogMagl SI) as an index.
  • the same test was performed on a SAW filter module manufactured in the same manner as above except that the organic polymer cured layer was not provided.
  • the SAW filter module of the present invention maintained almost the initial characteristics even after the elapse of 50 hours, indicating that the SAW filter module of the present invention has excellent airtightness. Further, in the comparative test example, remarkable deterioration of characteristics was observed after 50 hours, and it was confirmed that the effect of the present invention was at a level that could not be realized by mere sealing with an adhesive.
  • a silica glass paste (same as the sample A in (b) below) was printed on a 96-alumina substrate so as to have a thickness of 15 m, and was fired at 850 ° C. When the surface after firing was observed with an electron microscope, it was confirmed that fine crystals had precipitated. Was done. This is considered to be aluminobarium silicate-based microcrystals.
  • a water drop was dropped on the surface of the crystallized silica glass using a contact angle goniometer, and the contact angle was measured. The result was 8 to 15 °.
  • the contact angle was 70-80 ° on a 96-alumina substrate with a clean surface without a crystallized silica glass coating layer, confirming that the application of the crystallized silica glass layer was useful for improving wettability.
  • Electrodes and conductor lines are formed on a 0.64 mm thick 5 mm square 96 alumina substrate using an Ag-Pd alloy thick conductor paste (Fig. 3 (b)), and an inorganic glass material is further applied to the substrate surface. It was printed along its edge (Fig. 3 (c)). The same sample as above except that no inorganic glass layer was provided was prepared as a control.
  • FIG. 6 shows a microphone opening X structure constructed according to the present invention, wherein (a) is a plan view and (b) is a side view as viewed from the direction A in (a).
  • the microphone opening X structure package of the present invention shown in FIG. 6 has a conductor line G on a ceramic substrate 32 having a substantially rectangular element mounting area (a state where a GaAs FET bare chip 31 is mounted in the figure) in the center. , D, and S are formed at right angles from the region, and a sealing auxiliary layer 33 is provided circumferentially.
  • the sealing auxiliary layer 33 has a thickness sufficient to cover the conductor line at the intersection with the conductor line.
  • a 96-alumina thick-film printed circuit board is excellent in cost performance, but as a substrate material, 99.3% purity alumina substrate or 99.99% aluminum substrate is used. Mina substrates can also be used. The parasitic capacitance is suppressed by making G, D, and S orthogonal.
  • the conductor lines G, D, and S are planar lines formed on the substrate after firing, and are directly connected to the bare chip by wire bonding or the like.
  • the conductor line may be formed by thick-film printing as in the first embodiment, but a high-precision thin-film electrode can also be used for high-performance requirements and ultrahigh-frequency applications.
  • FIG. 6 shows a configuration example in which the conductor lines are the strip lines or coplanar lines shown in FIG.
  • the conductor lines G, D, and S are formed on a ceramic substrate 42 having a substantially rectangular element mounting area (a state in which a GaAsFET bare chip 41 is mounted in the figure) in the center.
  • Each substrate has a substrate structure formed at right angles from the region and provided with a sealing auxiliary layer 43 in a circumferential shape.
  • the sealing auxiliary layer 43 has a sufficient thickness to cover the conductor line at the intersection with the conductor line. After the formation of the sealing auxiliary layer 43, the sealing is performed by the cap member 45 via the adhesive layer 44.
  • the back surface of the substrate has a conductor layer 46 that covers substantially the entire surface.
  • the conductor layer 46 may be formed by thick film printing or by bonding a metal foil.
  • S is connected to the GND layer 46 on the back surface through a through hole.
  • the conductor lines G and D are arranged in a straight line, as in FIG. 6, so that the effect of suppressing the parasitic capacitance is high.
  • the degree of freedom in selecting the distributed constant lines is high and the frequency is increased. It has features that it is easy, it can suppress electrode loss and parasitic capacitance by using G and D distributed constant lines, and S can be grounded immediately to GND by through holes, so that GND impedance can be suppressed.
  • Well 3 Fig. 9 shows an example of the configuration of a SAW filter package 50 incorporating a balanced-unbalanced conversion circuit.
  • the point that the conductor line was provided on the substrate 52 on which the element 51 was mounted was the same as in Examples 1 and 2, but in this example, by further mounting the inductor and chip capacitor, The built-in balance-unbalance conversion circuit shown.
  • High-precision ink can be formed by thick film printing.
  • the conductive material can be formed by printing a thick film or a thin film, or by placing a thin wire in a coil shape.
  • a coil having a diameter of about 0.5 to 10 mm can usually be formed with a line width of about 60 to 300.
  • a coil having a line width of about 1 to 100 and a diameter of about 0.1 to 2 mm can be formed.
  • a rectangular spiral inductor (square-shaped inductor) is used, but the shape can be changed according to the purpose as long as it can be arranged on the substrate surface.
  • Such inductors include various inductor patterns composed of a crank or a loop or a conductor path forming a part thereof, in addition to the spiral inductors. More than H, usually about 1 to 50 nH is used.
  • the rectangular inductor has a conductor width of the inductor pattern and a space between conductor lines of 100 im, and is balanced by using an inductor having the following inductance value and a chip capacity.
  • Converter center frequency 8 5 o
  • the balanced converter is arranged only at the output terminal, but can be arranged also at the input terminal side.
  • the sealing structure is not shown in FIG. 9, the outline is the same as in Examples 1 and 2.
  • the inductor electrode and chip capacity need not be included in the hermetic seal unless they are directly connected to the SAW fill chip by wire bonding.
  • the SAW filter is hermetically sealed according to the first embodiment, and the conversion balance circuit is arranged on one of the front and back surfaces of the package substrate. May be connected.
  • the surface of a 96-alumina substrate 71 contains 90 individual substrate areas with an area of 5 mm wide and 5 mm long per area As described above, a divided region was provided in the center of the substrate, and a through hole 72 was formed on the divided line.
  • a conductive paste was filled and printed on the side surfaces of the through holes, and conductive patterns 73 were printed on the front and back surfaces of each individual substrate region.
  • a sealing auxiliary layer 74 is printed circumferentially between the element mounting area and the edge of the substrate area, and this is cured or fired to activate the surface.
  • the sealing auxiliary layer after the treatment is indicated by 75.
  • the SAW filter chip 76 was mounted in the center of the element mounting area, and wire bonding was performed. All of these operations are the same as in Example 1. Board table After wire bonding was completed in all the individual regions on the surface, a cap member 77 was adhered to the surface of the substrate and sealed to form a package structure 78. These operations are the same as in the first embodiment.
  • the above-mentioned collective substrate was placed on the stage of a commercially available wafer prober with its back surface facing upward, and the characteristics of each high-frequency element were inspected according to a previously programmed procedure.
  • the wafer probe was subjected to SOLT calibration in advance using a calibration substrate, and measurement was performed at 20 ° C.
  • the substrate was removed from the stage, and a total of 90 individual modules packaged with high-frequency devices were obtained by applying force along the dividing line.
  • the time required for the inspection was 90 seconds in total, which was significantly shorter than the case of inspecting the same number of individual high-frequency elements by the conventional method.
  • a GaAsFET chip and a dielectric resonator were used.
  • the entire circuit is hermetically sealed with a metal cap.
  • the conductor lines between the elements are formed as high-precision thin-film electrodes by the photoresist method.
  • Oscillators applied at 10 GHz or higher obtain oscillation characteristics by tuning the GaAs semiconductor for oscillation with a TE-type dielectric resonator (DRO).
  • DRO dielectric resonator
  • the DR ⁇ dimension is large compared to the micro X-package dimensions, and the DRO's resonant electromagnetic field is not disturbed.
  • the frequency increases, the DRO dimensions decrease, and the resonant fields become disturbed by the micro X-package.
  • the resonance of the package itself adversely affects the oscillation characteristics. Therefore, in higher frequency bands, it is necessary to mount GaAs semiconductors on a pair chip.
  • a high-performance millimeter-wave band module can be realized at a low cost, for example, by using an inexpensive sealing member or by performing impedance correction using a strip line with technical accumulation. .
  • the development of new technologies requires a large amount of development costs, and in the advanced technology field, reducing development costs is directly linked to lower product prices.
  • the sealing technology of the present invention does not require new technologies such as thick-film coplanar waveguides, which are being tried in band modules, and can achieve improved characteristics by applying stripline technology with accumulated technology to the millimeter-wave band. module To achieve both low price and high performance.
  • a high-frequency element package or a packaged high-frequency module can be manufactured and inspected as a collective substrate, the handling property is greatly improved, and the inspection is speeded up. But it has tremendous utility.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

L'invention concerne un boîtier destiné à un dispositif haute fréquence. Ce boîtier se caractérise en ce que des électrodes de haute précision se trouvent sur les deux côtés d'un substrat de céramique cuite. Une couche auxiliaire d'étanchéité durcie constituée d'une matière polymérique organique ou d'une matière inorganique est formée périphériquement, un dispositif étant monté sur le substrat entouré par cette couche auxiliaire d'étanchéité et connecté électriquement aux électrodes. Un élément de capuchon est lié à la couche auxiliaire d'étanchéité par un adhésif de manière étanche au gaz. Ledit boîtier peut être fabriqué et inspecté à peu de frais, et utilisé dans une gamme haute fréquence comprenant la bande d'ondes millimétriques (20-100GHz).
PCT/JP2000/007498 1999-10-29 2000-10-26 Boitier pour dispositif haute frequence WO2001033631A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU79587/00A AU7958700A (en) 1999-10-29 2000-10-26 Package for high-frequency device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP30989399 1999-10-29
JP11/309893 1999-10-29

Publications (1)

Publication Number Publication Date
WO2001033631A1 true WO2001033631A1 (fr) 2001-05-10

Family

ID=17998597

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/007498 WO2001033631A1 (fr) 1999-10-29 2000-10-26 Boitier pour dispositif haute frequence

Country Status (2)

Country Link
AU (1) AU7958700A (fr)
WO (1) WO2001033631A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7236064B2 (en) 2004-09-23 2007-06-26 Samsung Electro-Mechanics Co. Ltd. Laminated balun transformer
JP2007300173A (ja) * 2006-04-27 2007-11-15 Epson Toyocom Corp 電子デバイス用パッケージ、及び電子デバイス
JP2009537999A (ja) * 2006-05-23 2009-10-29 コンチネンタル オートモーティヴ ゲゼルシャフト ミット ベシュレンクテル ハフツング 遮蔽部を備えた電子装置
JP2009544201A (ja) * 2006-07-20 2009-12-10 エプコス アクチエンゲゼルシャフト 電気モジュール
JP2012222537A (ja) * 2011-04-07 2012-11-12 Seiko Epson Corp パッケージ、振動子、発振器及び電子機器
JP2014089958A (ja) * 2012-10-29 2014-05-15 Optosys Ag 近接センサ
JP2015126498A (ja) * 2013-12-27 2015-07-06 京セラクリスタルデバイス株式会社 圧電発振器
JP2021085795A (ja) * 2019-11-29 2021-06-03 株式会社デンソー レーダ装置
TWI802991B (zh) * 2021-09-13 2023-05-21 日商雅馬哈智能機器控股股份有限公司 超音波振動式不良檢測裝置及線材不良檢測系統

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60181917U (ja) * 1984-05-11 1985-12-03 クラリオン株式会社 弾性表面波素子
JPS63174341A (ja) * 1987-01-14 1988-07-18 Hitachi Ltd 半導体装置
JPH01165148A (ja) * 1987-12-21 1989-06-29 Mitsubishi Electric Corp 半導体装置
JPH0287557A (ja) * 1988-09-24 1990-03-28 Murata Mfg Co Ltd Ｉｃチップの製造方法
JPH07135270A (ja) * 1993-11-11 1995-05-23 Hitachi Ltd 半導体集積回路装置の製造方法
US5528135A (en) * 1992-08-18 1996-06-18 Kabushiki Kaisya Sumitomo Kinzoku Ceramics Sheet ceramic package having electrically independent products units
JPH09232461A (ja) * 1996-02-23 1997-09-05 Nikko Co セラミックリッドによる中空パッケージ構造を有する電子部品の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60181917U (ja) * 1984-05-11 1985-12-03 クラリオン株式会社 弾性表面波素子
JPS63174341A (ja) * 1987-01-14 1988-07-18 Hitachi Ltd 半導体装置
JPH01165148A (ja) * 1987-12-21 1989-06-29 Mitsubishi Electric Corp 半導体装置
JPH0287557A (ja) * 1988-09-24 1990-03-28 Murata Mfg Co Ltd Ｉｃチップの製造方法
US5528135A (en) * 1992-08-18 1996-06-18 Kabushiki Kaisya Sumitomo Kinzoku Ceramics Sheet ceramic package having electrically independent products units
JPH07135270A (ja) * 1993-11-11 1995-05-23 Hitachi Ltd 半導体集積回路装置の製造方法
JPH09232461A (ja) * 1996-02-23 1997-09-05 Nikko Co セラミックリッドによる中空パッケージ構造を有する電子部品の製造方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7236064B2 (en) 2004-09-23 2007-06-26 Samsung Electro-Mechanics Co. Ltd. Laminated balun transformer
JP2007300173A (ja) * 2006-04-27 2007-11-15 Epson Toyocom Corp 電子デバイス用パッケージ、及び電子デバイス
JP2009537999A (ja) * 2006-05-23 2009-10-29 コンチネンタル オートモーティヴ ゲゼルシャフト ミット ベシュレンクテル ハフツング 遮蔽部を備えた電子装置
JP4746697B2 (ja) * 2006-05-23 2011-08-10 コンチネンタル オートモーティヴ ゲゼルシャフト ミット ベシュレンクテル ハフツング 遮蔽部を備えた電子装置
US8289726B2 (en) 2006-05-23 2012-10-16 Continental Automotive Gmbh Electrical device with screen
JP2009544201A (ja) * 2006-07-20 2009-12-10 エプコス アクチエンゲゼルシャフト 電気モジュール
JP2012222537A (ja) * 2011-04-07 2012-11-12 Seiko Epson Corp パッケージ、振動子、発振器及び電子機器
JP2014089958A (ja) * 2012-10-29 2014-05-15 Optosys Ag 近接センサ
JP2015126498A (ja) * 2013-12-27 2015-07-06 京セラクリスタルデバイス株式会社 圧電発振器
JP2021085795A (ja) * 2019-11-29 2021-06-03 株式会社デンソー レーダ装置
WO2021106471A1 (fr) * 2019-11-29 2021-06-03 株式会社デンソー Dispositif radar
JP7226274B2 (ja) 2019-11-29 2023-02-21 株式会社デンソー レーダ装置
TWI802991B (zh) * 2021-09-13 2023-05-21 日商雅馬哈智能機器控股股份有限公司 超音波振動式不良檢測裝置及線材不良檢測系統

Also Published As

Publication number Publication date
AU7958700A (en) 2001-05-14

Similar Documents

Publication Publication Date Title
US6570469B2 (en) Multilayer ceramic device including two ceramic layers with multilayer circuit patterns that can support semiconductor and saw chips
CN100533970C (zh) 弹性表面波装置以及通信装置
US7520054B2 (en) Process of manufacturing high frequency device packages
US7125744B2 (en) High-frequency module and method for manufacturing the same
US7808796B2 (en) Electronic component module and method for manufacturing the same
JP2002076832A (ja) 表面弾性波素子を含む高周波モジュール部品及びその製造方法
US20040178858A1 (en) Piezoelectric oscillator, portable phone employing piezoelectric oscillator, and electronic apparatus employing piezoelectric oscillator
US20020101304A1 (en) Surface accoustic wave device, method for producing the same, and circuit module using the same
US20090288852A1 (en) Electronic device and method of manufacturing the same
JP4137356B2 (ja) 表面弾性波素子を含む高周波モジュール部品の製造方法
US20110174533A1 (en) Electronic apparatus, method of manufacturing substrate, and method of manufacturing electronic apparatus
US20120228755A1 (en) Semiconductor module and manufacturing method thereof
WO2001033631A1 (fr) Boitier pour dispositif haute frequence
CN112563237A (zh) 射频SiP陶瓷封装外壳及其制作方法
US6888239B1 (en) Ceramic package sealing structure and ceramic package having said sealing structure
JP5309039B2 (ja) 高周波用配線基板、電子部品収納用パッケージ、電子装置および通信機器
US20190006254A1 (en) Microelectronic package construction enabled through ceramic insulator strengthening and design
JP2008072748A (ja) 表面弾性波素子を含む高周波モジュール部品及びその集合体
CN100378967C (zh) 陶瓷封装及其制造方法
JP2010034212A (ja) 高周波セラミックパッケージおよびその作製方法
JP2970723B2 (ja) 半導体パッケージおよびその製造方法
JP2001102469A (ja) 半導体素子収納用パッケージ
JP2002299982A (ja) 水晶発振器の製造方法
JP4206185B2 (ja) 高周波半導体装置
WO2001011771A1 (fr) Filtre lc et son procede de fabrication

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 535230

Kind code of ref document: A

Format of ref document f/p: F

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase