WO2001033631A1 - Package for high-frequency device - Google Patents

Package for high-frequency device Download PDF

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Publication number
WO2001033631A1
WO2001033631A1 PCT/JP2000/007498 JP0007498W WO0133631A1 WO 2001033631 A1 WO2001033631 A1 WO 2001033631A1 JP 0007498 W JP0007498 W JP 0007498W WO 0133631 A1 WO0133631 A1 WO 0133631A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
package
frequency
conductor
cap member
Prior art date
Application number
PCT/JP2000/007498
Other languages
French (fr)
Japanese (ja)
Inventor
Masakiyo Horioka
Yoshihisa Okumura
Kunio Tochi
Makoto Aoki
Kiyoshi Mizushima
Original Assignee
Nikko Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikko Company filed Critical Nikko Company
Priority to AU79587/00A priority Critical patent/AU7958700A/en
Publication of WO2001033631A1 publication Critical patent/WO2001033631A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates to a high-frequency element package, a method for manufacturing the same, and a method for packaging a high-frequency element.
  • High-frequency semiconductors such as surface acoustic wave (SAW) filters or MMICs (Microwave Monolithic Integrated Circuits) and GaAsFETs are indispensable for such high-frequency devices. Is being developed and improved.
  • a high-frequency element is hermetically sealed in dry air or an inert gas such as nitrogen or a rare gas using a hollow ceramic package.
  • an inert gas such as nitrogen or a rare gas
  • a hermetic sealing structure a structure in which a high-frequency element is sealed in a metal case is known.
  • the use of a metal case or the like is limited because it is expensive and it is difficult to reduce the size and weight.
  • a structure is also known in which a high-frequency element is mounted on a substrate, and then a lid made of ceramic, metal, or the like is bonded to the substrate using solder, low-melting glass, thermosetting resin, or the like.
  • the laminated ceramic package 60 has a laminated structure in which the central portion is a single layer and the periphery is two to three layers, and the latter forms a stepped wall.
  • the high-frequency semiconductor element (bare chip) 61 is mounted in a concave part (on the first layer in the figure) in the center of the package, and is wire-bonded to the electrode or conductor line 62 formed on the shelf (the second layer).
  • Connected by A third layer is further provided on the edge of the package, and the lid 65 (usually a metal lid) is seam-welded to the element via, for example, a seal ring 64, thereby affecting the element. Airtight sealing is realized without any problems, and high airtightness is maintained inside.
  • the laminated structure may have two layers, or may have four or more layers.
  • the signal transmission line 62 such as a strip line formed on the shelf is connected to external electrodes 66 provided on the side and bottom surfaces of the package 60 (FIG. 10 (a)), Are connected to the external electrodes 66 by filling vias or through holes 67 provided through the bottom surface of the substrate (FIG. 10 (b)). Thereby, input / output of a high-frequency signal to / from the element (bare chip) 61 is performed.
  • a conductive paste is printed on a ceramic green sheet formed in a predetermined shape in a thick film, these sheets are laminated, cut into individual pieces, and then, It is formed by firing the electrodes and conductor lines simultaneously with firing the green sheet. Therefore, (1) the mounting area of the element, (2) the internal electrode for mounting the element (bare chip), the external electrode for connecting the packaged element module to the external circuit, and the connection between the internal and external electrodes It has the advantage that the conductor line and (3) the support for the sealing lid can be formed simultaneously by applying a conventional lamination technique.
  • the impedance given by the parasitic capacitance increases as the frequency increases, and the influence increases. This can be corrected by a capacitor or the like, but in a conventional stacked package, it is difficult to correct the impedance with high accuracy because the parasitic capacitance differs for each package. In addition, the mounting of the correction capacity further complicates the package structure. Further, in the conventional package manufacturing method and packaging method, a package piece of a millimeter order is baked, an element is mounted on the package piece, wire-bonded, and a lip is welded. In other words, it was necessary to handle micro ceramic packages and semiconductor chips, etc., and miniaturization of components had increased production costs.
  • the inspection requires the manufacture of jigs and inspection pads for each product. Furthermore, in order to automate the inspection, an inspection device including a large-scale positioning device suitable for handling minute components is required. In addition, due to the inability to configure the jig, it was practically difficult to perform temperature characteristics and other precise inspections on individual packages.
  • An object of the present invention is to solve the above-described problems in the high-frequency package according to the related art, which can be manufactured and inspected at low cost, and has a millimeter wave band (20 to 100 GH).
  • An object of the present invention is to provide a high-performance package structure that can be used even in a high frequency region including z).
  • Another object of the present invention is to provide an inexpensive and efficient manufacturing method and a packaging method for such a high-performance high-frequency package. Disclosure of the invention
  • the present inventors have studied the above-mentioned problems in a package having a multilayer substrate structure, which has been conventionally considered to be necessary for hermetic sealing at a required level for a high-frequency element. Since the formation of the electrodes and conductor lines by firing is performed simultaneously with the firing of the substrate material, dimensional fluctuations and non-uniformity of the conductors due to shrinkage of firing of the substrate material are inevitable, which causes signal degradation in the high frequency band. It was also concluded that this was one of the main causes of the parasitic capacitance variation (non-uniformity) from package to package.
  • the electrodes necessary for mounting the element, the input / output conductor lines and the Z or circuit are provided on the fired ceramic substrate, and the cured organic polymer material or inorganic material is provided.
  • a sealing auxiliary layer made of a material By bonding the cap-type lid with an adhesive via a sealing auxiliary layer made of a material, a high-level hermetic seal is achieved, and a package exhibiting excellent characteristics in a high frequency band can be realized.
  • a high-precision line width and line length of the conductor line can be obtained. Therefore, by using a strip line for impedance correction, stable impedance can be obtained even at high frequencies.
  • a plurality of package regions are provided on the fired substrate, and a package substrate structure according to the above (1) to (2) is formed for each region, and element mounting and hermetic sealing with a cap member are performed. After that, the process of dividing into individual pieces is adopted to improve the efficiency of the manufacturing process. In addition, by applying the semiconductor A8 inspection technology to such an assembled substrate, the inspection efficiency is improved-advanced ( Precision inspection and temperature characteristic inspection), and completed the present invention.
  • the present invention provides the following high-frequency element package, a method of manufacturing the same, and a method of packaging the high-frequency element.
  • a package for a high-frequency element including a cap member, wherein the ceramic substrate includes: an internal electrode for mounting the element formed after firing of the substrate material; an external electrode; a conductor line connecting between the electrodes; and an element mounting area.
  • a sealing auxiliary layer made of a cured body of an organic polymer material or an inorganic material provided in a shape compatible with the end face of the cap member between the substrate and the portion; After being electrically connected to the cap member A package for a high-frequency element, wherein the package is hermetically sealed by adhering to a cured organic polymer material layer with an adhesive.
  • the element is a GaAs FET, and the conductor lines connected to the gate (G) and the drain (D) are on a straight line, and the distributed constant line connected to the source (s) is orthogonal to this.
  • a plurality of element mounting regions connected by conductor lines are provided on a substrate, and the whole including these elements or one or more of these elements that need to be hermetically sealed by the cap member.
  • FIGS. 1 (a) and 1 (b) are a plan view and a cross-sectional view, respectively, schematically showing the substrate structure of the high-frequency element package of the present invention.
  • 2 (a) and 2 (b) are a plan view and a cross-sectional view, respectively, which schematically show the sealing structure of the high-frequency element package of the present invention.
  • FIG. 3 is a perspective view schematically showing a packaging process of a high-frequency device according to the present invention.
  • FIG. 4 is a plan view schematically showing the structures of the strip line and the coplanar line.
  • FIG. 5 is a plan view schematically showing a conventional microphone opening X structure.
  • 6 (a) and 6 (b) are a plan view schematically showing the micro X structure according to the present invention and a side view excluding a part of the sealing structure, respectively.
  • FIG. 7 (a) is a side view schematically showing the structure of the distributed constant type GaAsFET package according to the present invention (however, excluding a part of the sealing structure).
  • FIG. 7 (b) and FIG. (c) is a plan view schematically showing two types of structures corresponding to (a).
  • FIG. 8 is a circuit diagram showing an example of a balanced-unbalanced conversion circuit.
  • FIG. 9 is a plan view schematically showing the structure of a package with a built-in balanced-unbalanced conversion circuit according to the present invention.
  • FIG. 10 is a cross-sectional view schematically showing a structure of a conventional high-frequency element package as ⁇ and (b) according to a difference in a connection structure with an external electrode.
  • FIG. 11 is an explanatory view schematically showing a collective substrate packaging process for a high-frequency device according to the present invention.
  • FIG. 12 is an explanatory view schematically showing a packaging substrate packaging process of the high-frequency device according to the present invention, following FIG.
  • FIG. 13 is an explanatory diagram that schematically shows a packaging substrate packaging process of the high-frequency device according to the present invention, following FIG. 12.
  • FIG. 14 is a schematic diagram showing a comparison between a 10 GHz band oscillator according to the prior art and a 10 GHz band oscillator according to the present invention.
  • FIG. 1 and 2 show the basic structure of the high-frequency element package 10 of the present invention.
  • FIG. 1 schematically shows the package substrate 1 before sealing (FIG. 1): a plan view showing an element mounting surface.
  • FIG. 1 (b) is a cross-sectional view of the package substrate of FIG. 1 (a) taken along the line AA ′ in the figure), and
  • FIG. 2 is a state in which the element is sealed using a cap member 8. It is a top view and a sectional view.
  • Fig. 3 schematically shows the flow of manufacturing and packaging of this package.
  • the package substrate 1 of the present invention is used for performing input and output to and from the fired ceramic substrate having the element mounting area 2.
  • electrodes or conductor lines and Z or circuit inner electrode 3 for mounting bare chip, outer electrode 6 for package mounting and conductor line 4 and side electrode 5 connecting between them
  • a sealing auxiliary layer 7 made of a cured body of an organic polymer material or an inorganic material. Preferred Alternatively, the sealing auxiliary layer is subjected to a surface activation treatment.
  • the internal electrode 3 and the conductor line 4 may be integrated.
  • the high-frequency element 11 is mounted at the center of the element mounting area 2, and the electrodes 13 on the element surface and the package internal electrodes 3 are connected by bonding wires 12 (see FIG. Thereafter, the cap member 8 is sealed by bonding the cap member 8 to the sealing auxiliary layer 7 of the substrate using an adhesive 9 (corresponding to FIG. 3 (f)).
  • the sealing auxiliary layer 7 and the adhesive layer 9 are drawn to have the same width as the end face of the cap member, but the sealing layer composed of the sealing auxiliary layer 7 and the adhesive layer 9 is As long as the high-frequency characteristics are not affected, the substrate may have a larger spread on the substrate surface.
  • the electrodes and conductor lines are not affected by dimensional fluctuations caused by shrinkage of the substrate material due to firing shrinkage, so it is possible to incorporate high-level impedance adjustment and other functions using strip lines, etc. , And a high level of sealing can be realized.
  • FIGS. 1 and 2 shows the most basic embodiment of the present invention, and the shape of the substrate and the structure of the conductor line are changed as necessary.
  • the substrate structure, the cap member, and the adhesive layer, which are basic elements of the package of the present invention will be described in detail with reference to typical application examples.
  • the substrate structure in the package of the present invention includes a fired substrate (a fired ceramic substrate is simply referred to as a “ceramic substrate” unless otherwise noted) and the elements provided on the surface thereof. It includes electrodes, conductor lines, and Z or circuits for input and output of the I / O.
  • a conventional multilayer ceramic package also includes a structure in which ceramic is used as a substrate material and electrodes, conductor paths, and the like (hereinafter, also simply referred to as “electrodes”) are provided thereon.
  • electrodes electrodes
  • conventional multilayer ceramic packages as described above, A thick paste of conductive paste is printed on the green sheet and the electrodes are formed by firing the green sheet simultaneously with firing.Since shrinking of the green sheet is inevitable during firing, the parasitic capacitance of the package is reduced for each piece. different. This non-uniformity (variation) is mainly due to poor uniformity in the shrinkage of the electrodes co-fired in the production of the multilayer ceramic package, making it difficult to form electrodes with high precision.
  • the substrate material various ceramic materials can be used, but a material satisfying the following conditions is particularly preferable.
  • the element (bare chip) to be mounted must have the same coefficient of linear expansion.
  • alumina particularly 96 alumina containing 96% by weight of alumina
  • a dielectric material having a dielectric constant and a Q value higher than that of alumina may also be used.
  • lower inorganic dielectric Body materials can also be used.
  • the thickness of the substrate is selected according to the dimensions of the substrate and the required strength.
  • the dimensions and shape of the substrate are determined by the size of the element to be mounted.
  • the electrodes and the conductor lines for inputting and outputting to the substrate and the elements provided on the surface thereof include internal electrodes and packages for connection to the elements as shown in FIGS. 1 and 2. It includes external electrodes (including side electrodes) provided for surface mounting, and conductor lines connecting between the internal and external electrodes.
  • Electrodes and conductor lines can be formed by, for example, thick film printing. Further, in the present invention, since there is no step of “firing” after the formation of the electrode, a highly accurate electrode formation by thin film formation and other metallization methods can be used.
  • the conductor material may be a conventional one.
  • conductive paste for thick film such as Ag, Ag—Pt, Ag—Pd, Au, Cu, and Ni, and for thin film formation. Examples include, but are not limited to, Au, Cu, A and Ni, and the like. These methods may be combined.
  • an electroless plating for example, an electroless gold plating
  • Applying electroless gold plating has the effects of (1) improving wire bonding, (2) improving solderability, and (3) improving conductor resistance.
  • the internal and external electrode shapes may be the same as those of the conventional package.
  • 1 and 2 show the mode of electrically connecting the element and the package by bonding wires, but other connection structures such as a bump structure may be used, and the internal electrodes are shaped according to each connection structure.
  • FIGS. 1 and 2 show a mode of connection with the internal electrode-conductor line-side electrode-external electrode, but a filled through hole may be used instead of the side electrode.
  • a flat line strip line, Cross-trip lines, coplanar lines are typical applications.
  • a stripline can be formed by providing a conductor line with an appropriate line width on the surface of the substrate and providing ground (GND) on the backside of the substrate (Fig. 4 (a)).
  • the line width d is 0.641 ⁇ 01.
  • a strip line with a characteristic impedance of 50 ⁇ can be formed by providing a conductor line consisting of a t-force and GND on the entire back surface.
  • Fig. 4 (b) shows the structure of a coplanar waveguide. This is one in which conductor layers are provided on both sides of the transmission line in Fig. 4 (a). Although the figure shows a structure in which the conductor layers on both sides are connected to the GND layer on the back via a through hole, a structure without a GND layer on the back or a coplanar line structure with GND excluding through holes may be used. .
  • the coplanar waveguide has a problem that it is difficult to design, it is suitable at 10 GHz or more, and a characteristic satisfying practical use is obtained up to a frequency of 100 GHz or more.
  • FIG. 5 schematically shows a plan view of a conventional structure of an ultra-high frequency ceramic package 20 applied at 10 GHz or more called Micro X.
  • the element 21 mounted in the center is a GaAs FET bare chip with high electron mobility.
  • the substrate 22 on which the bare chip is mounted is a multilayer laminated substrate similar to that of FIG. 10 and the like.
  • Micro X a conductor line that connects to the gate, drain, and source terminals. , D, and S are arranged perpendicular to each other to suppress the parasitic capacitance.
  • These conductor lines are inner layer wiring inside the substrate and are generally connected to strip lines formed separately outside the chip mounting substrate (in the figure, they are shown as one integrated inside and outside the substrate). There is.)
  • the parasitic capacitance C does not disappear even if the terminals are orthogonal to each other to form the microphone opening X structure.
  • inductance L due to the bonding wire 23 connecting each electrode of the GaAsFET and the conductor line.
  • the uniformity of the parasitic capacitance C is poor because the shrinkage rate during firing is not uniform for each package. Since the bonding accuracy is high, the wire bonding itself can usually be formed with high uniformity.However, in the conventional laminated substrate structure, dimensional changes due to shrinkage of the inner wiring due to firing shrinkage are unavoidable. Non-uniformity (variation) also becomes a problem. When the frequency is 10 GHz or more, the frequency change of impedance due to C and L increases, and a frequency band in which an appropriate signal wave current is not applied to the semiconductor chip occurs. In Micro X, this problem is reduced by connecting to (micro) strip lines separately formed on the chip mounting substrate.
  • the connection structure between the electrodes on the element and these conductor lines is reduced. Tend to be complicated.
  • the parasitic capacitance C is not only uniform in each package, but also a highly accurate stripline (or coplanar type conductor). Wave line) can be built into the package for impedance correction. Examples are shown in Figs. These have conductor lines provided on the substrate, and can correct the inductance L and the parasitic capacitance C of the bonding wire with high accuracy.
  • the width and interval of the conductor wiring can be precisely controlled, it is possible to additionally provide a high-precision planar inductor on the substrate. Therefore, circuits having various functions can be provided on the surface by combining such a planar inductor and a capacitance element such as Z or a chip capacitance available at high precision on a substrate.
  • a circuit is a balanced-unbalanced conversion circuit.
  • balun a balanced-unbalanced conversion element
  • LNA low-noise amplifier
  • mixers that are driven by low voltages to achieve a wide dynamic range and high gain
  • Equilibration of the high-frequency circuit eliminates the need for MMICs such as power switch transistors and DC / DC converters for negative voltage generation, and eliminates the need for MMICs for mobile communications.
  • the wave circuit can be significantly reduced in size and cost.
  • the LNA is balanced in the example of the configuration of the mobile phone receiver from the antenna (ANT) to the low noise amplifier (LNA :) via the antenna switch (ANT-SW) and then to the SAW filter
  • the subsequent stage Either upgrade the SAW filter to a balanced type, or use a balanced converter between the LNA and the SAW filter.
  • the balun can be composed of a combination of an inductor and a capacitor, as shown in the equivalent circuit of FIG. 8, and in the present invention, by mounting the circuit shown in FIG. A package can be used (an example of this configuration will be described in detail in Embodiment 3).
  • an inductor electrode is formed on a fired substrate such as an alumina substrate, so that a highly accurate inductor electrode can be formed.
  • a high-performance circuit can be constructed by using a small, large-capacity chip capacitor with a high Q value. If necessary, the characteristic impedance may be adjusted using conductor lines.
  • the present invention can be applied to all circuits having high-frequency components that require hermetic sealing.
  • a high-frequency circuit including one or more GaAs FETs, SAW filters, or MMICs, it is possible to seal each of these high-frequency elements, two or more of them, or the entire circuit as described above. Is described in detail in Example 5.
  • the cap member functioning as a lid may have any shape and height so as to form a space having a size sufficient to accommodate the element when brought into close contact with the surface of the substrate. Also, it is sufficient if the protective member has sufficient strength.
  • Caps made of inorganic material, organic material, and metal can be used for sealing. Alumina, quartz glass, etc. made of inorganic material, plastic made of organic material Metals such as paints, epoxies, and the like include iohaku (Western white), phosphor bronze, and copper.
  • the high-frequency device will be surrounded by a conductive material, and almost perfect shielding can be obtained by grounding the cap to GND. Also, there is a high shielding effect without grounding.
  • a metal cap If a metal cap is used, it must be insulated from the conductor tracks on the substrate surface. Insulation between the metal cap and the conductor line can be achieved by providing an insulating layer between the cap and the conductor line by thick-film printing or the like. In the present invention, the sealing auxiliary layer also functions as an insulation layer.
  • a sealing auxiliary layer which is a cured body of the sealing auxiliary layer or an inorganic material layer is provided on a ceramic substrate having a region for mounting a high-frequency element, and a cap
  • a major feature is that the member is bonded to the sealing auxiliary layer with an adhesive to perform sealing.
  • an adhesive eliminates the need for a heat treatment at several hundred degrees Celsius, which is required when sealing with solder-glass frit. Also, by activating the surface of the sealing auxiliary layer prior to bonding, highly reliable bonding and sealing that can withstand repeated thermal expansion after mounting the element module can be realized.
  • the sealing method according to the present invention is used for sealing SAW filters, GaAs FETs, MMIC power amplifiers, etc., which are used in a high frequency or ultra-high frequency band, generate a large amount of heat, and have a high level of required moisture resistance. Must be adopted.
  • the sealing auxiliary layer is formed on the substrate in a shape compatible with the end surface of the cap member. Specifically, a polymer resin is printed and cured in the area including the joint with the cap member on the substrate, or an inorganic material layer is formed by thick-film printing or other methods and then fired and sealed. An auxiliary layer.
  • the organic polymer material that can be used as the sealing auxiliary layer in the present invention includes, as a main component, a resin having heat resistance, moisture resistance, and insulation properties, such as an epoxy resin, a phenol resin, and an epoxy phenol resin. It is preferable to use resin materials in which a curing agent, a reppelling agent, an antifoaming agent, an inorganic filler, and the like are dispersed in order to impart coatability such as screen printing to these materials.
  • the leveling agent or the defoaming agent include those containing silicone oil as a main component. However, when a silicone-based leveling agent or antifoaming agent is used, the amount added should be 0.01 to 2.0 wt. % Is preferably used.
  • the leveling agent is modified with epoxy. It is preferable to add the inorganic filler in consideration of the anchoring effect at the time of epoxy bonding, but in this case, use a filler with an average particle size of about 0.5 to 10 m suitable for screen printing. Is preferred.
  • the sealing auxiliary layer When the sealing auxiliary layer intersects with the wiring or the like on the substrate surface, which is printed on the substrate by a common method such as screen printing, the sealing auxiliary layer absorbs irregularities due to the conductive path on the substrate surface, and the cap member is made of metal.
  • the cap member In some cases, in order to ensure insulation from the wiring conductors on the board, cover the surfaces of the electrodes or conductor lines, that is, make them thicker than these conductor paths, and make the resin layer surface as a whole. The height must be even. This can be realized by adjusting the viscosity to an appropriate value with the above-mentioned additives and the like.
  • a layer having a thickness of about 10 to 50 may be used (the same applies to the case of an inorganic material described later).
  • the organic polymer layer is cured to form a sealing auxiliary layer.
  • the inorganic material that can be used as the sealing auxiliary layer is not particularly limited, and various inorganic glasses and oxides can be used. Among them, crystallized silica glass is preferred.
  • crystallized silica glass S i 0 2 - M G_ ⁇ one Z n O- A l 2 ⁇ 3 system, P b O-Z N_ ⁇ one B 2 ⁇ 3 - S i 0 2, and the like,
  • glass other than this may be a glass that precipitates microcrystals during sintering and does not contain lead.
  • Crystallized silica glass may have pinholes of about several meters, but no problem occurs if the thickness is about 10 to 20 m.
  • the sealing auxiliary layer Will overlap with part of the wiring conductor, but the plating layer formed by electroless plating, especially the Au plating layer surface, is chemically inert, and the adhesion between the conductor layer and the sealing auxiliary layer is reduced. I do. Therefore, it is necessary to form a sealing auxiliary layer before plating.
  • the glass component contains lead
  • the lead component elutes into the plating solution during the Au plating, and becomes a catalyst poison. In crystallized silica glass, such a situation does not occur, and it is considered that Au plating progresses smoothly and contributes to the improvement of characteristics.
  • the sealing auxiliary layer is bonded to the cap member.
  • the surface activation treatment of the sealing auxiliary layer includes various chemical or physical treatments for increasing the affinity with the adhesive. Among them, ultraviolet treatment and plasma treatment are preferred.
  • the ultraviolet treatment is performed by irradiating the surface of the sealing auxiliary layer with ultraviolet light.
  • UV irradiation The chemical affinity of the sealing auxiliary layer for the adhesive increases, and a high degree of hermetic sealing can be realized. Irradiation energy depends on the type of the sealing auxiliary layer and the like, but in the case of a polymer resin material, it may be generally within a range of 400 to 160 mJ. In general, if it exceeds 160 OmJ, the adhesive strength is rather lowered. In addition, the oxidation of the conductor thick film proceeds easily. On the other hand, a remarkable effect is not obtained below 40 OmJ. Usually, the range of 400 to 100 OmJ is preferable.
  • the wavelength of the irradiation ultraviolet rays is selected so as to include a wavelength range in which active points are formed in the cured polymer resin layer.
  • the energy irradiation amount is larger as long as it does not adversely affect the conductor layer and the like on the substrate surface.
  • Such ultraviolet irradiation can be performed using, for example, a low-pressure mercury lamp.
  • Plasma treatment is also preferable as the surface activation treatment of the sealing auxiliary layer in the present invention.
  • the plasma treatment is performed by applying a high-frequency AC voltage between electrodes filled with decompressed gas to generate a glow discharge between the electrodes and bringing the plasma of the gas component into contact with the substrate.
  • the plasma treatment removes the contaminant layer and promotes surface roughening and formation of Z or chemically active sites.
  • the substrate on which the above-mentioned sealing auxiliary layer is formed is placed in a plasma processing apparatus capable of reducing pressure, and the atmosphere in the apparatus is appropriately replaced with a plasma processing gas. Perform by applying.
  • the gas used for the plasma treatment is not particularly limited as long as it is non-oxidizing gas. Examples of such a gas include an inert gas such as helium, neon, and argon, and nitrogen. Argon is preferred.
  • the pressure of the processing gas is 1 mTorr to 1 O Torr, preferably 1 O mTorr to: L Torr, and more preferably about 100 to 300 mTorr.
  • the high-frequency power supply may have a frequency in the range of 1 to 100 MHz and a power of about 10 to 300 W.
  • the sealing auxiliary layer is a polymer material, it is preferably about 50 to 200 W, and when it is an inorganic material, it is preferably about 200 to 300 W.
  • the processing time depends on the type of the sealing auxiliary layer, but is usually in the range of 10 to 300 seconds. When an inorganic material is used, 3 to 5 minutes is preferable. If the processing time is too short, the effect of the processing will not be sufficiently exhibited. If the treatment time is too long, the etching effect of the plasma is exerted on the electrode and the conductor layer on the substrate surface, which is not preferable.
  • the adhesive is not limited as long as it has good adhesiveness to the above-mentioned cured surface and excellent airtightness.
  • examples of such an adhesive include an epoxy-based adhesive and an epoxy-phenol-based adhesive.
  • the high-frequency device of the present invention can be manufactured by a method schematically shown in FIG.
  • the present invention further provides a manufacturing method using a collective substrate.
  • perforations (through holes) 72 are formed at predetermined positions of the inorganic insulator substrate 71 (FIG. 11 (a)).
  • the formation of through-holes is possible in any way. For example, drilling with a single laser beam, drilling with a drill, and the like can be given. It may be fired after punching on a ceramic green sheet.
  • a conductor is printed, filled and Z or plated in the through hole 72 to form electrodes and conductor lines 73 on the surface of the substrate and electrode terminals on the back surface (not shown) of the substrate (FIG. 11).
  • the formation of the electrodes and the like is similar to the case where the individual substrate is used. Also, for example, when a coplanar line is used, the side conductor layer is formed, when a distributed constant type is used, a GND layer on the back side is formed, or when an additional circuit is mounted, an inductor pattern is also formed. Good.
  • a sealing auxiliary layer 74 is formed as in the case of the individual substrate (FIG. 12 (a)), and the surface is activated (FIG. 12 (b)).
  • the module is separated into individual modules packaged on the substrate surface. Separation into individual chips can be performed, for example, by a conventional method such as sawing, but by forming a shallow dividing line on the substrate and applying a deformation force along the dividing line after resin sealing.
  • the substrate may be divided. It is preferable to divide the through hole along the through hole, and the divided through hole can be used as a conductive portion to the back surface or a side electrode.
  • the manufacturing method of the present invention further provides a method for further improving the efficiency of the entire package manufacturing process by inspecting the semiconductor device after being formed as a collective substrate and before dividing it into individual pieces (this method is described in the next section).
  • Packaging method This will be described in detail in the description of the method. ).
  • a packaging method for a high-frequency device according to the present invention can be realized using the above-described package.
  • an electronic component is mounted on a ceramic substrate having a sealing auxiliary layer, and the electronic component is sealed by bonding a cap member.
  • the package structure is as described above.
  • Examples of the mounting method include a resin bonding method using a conductive paste or a bonding method using brazing or the like. After bonding, for example, flux cleaning is performed using an alternative chlorofluorocarbon (HFCFC), and electrical bonding between the electronic component and the thick film substrate is performed by wire bonding or the like.
  • HFCFC chlorofluorocarbon
  • the wire length is as short as possible and the wire thickness is large.
  • a gold wire having a diameter of 10 to 50; m, preferably 15 to 30 / m is used.
  • the environmental conditions (especially humidity) during the sealing process are important. For example, air dehumidified by activated alumina etc. with a dew point of 140 ° C or less is blown, and the dew point of the working area is 120 ° C or less.
  • the sealing operation is carried out under the condition maintained at.
  • the adhesive strength of the ceramic lid of the sample prepared in this way is higher than that of the sample with a low melting point glass that is generally used for conventional oscillators, etc. Will be much stronger.
  • a method of packaging an element using a collective substrate that is, a step of forming a plurality of package substrate regions by vertically and horizontally providing dividing lines including through holes on a ceramic substrate; Step of forming a conductive path for conducting the front and back surfaces of the substrate through the through hole: connecting the internal electrode for mounting the element and the internal electrode to the conductive path inside the through hole on the surface on the element mounting side in each substrate area.
  • the procedure up to the mounting of the element is the same as that described with reference to FIGS. 11 and 12. Thereafter, the element is mounted and the connection is performed by wire bonding (FIG. 13 (a)). After wire bonding, the substrate surface is sealed with a cap member 77, and then separated into individual packaged modules (FIG. 13 (c)). For separation into individual chips, the substrate may be divided by forming a shallow dividing line on the substrate and applying a deforming force along the dividing line after resin sealing. By dividing along the through hole 72, the inner surface of the through hole 72 can be used as a conductive portion to the back surface or a side electrode 79.
  • the aggregate substrate is divided in a state where the edge of each substrate region is structurally reinforced by bonding the cap member, so that the stress at the time of division tends to concentrate on the division line, and the division of each substrate region is performed. Can be realized more reliably.
  • the manufacturing method or the packaging method of the present invention it is possible to realize an efficient method for inspecting a high-frequency package or a packaged module.
  • Wafer probers are widely used for precision measurement, intermediate inspection, and shipping inspection of semiconductor products, and include a test head, a probe card, and a stage that can be moved in the XY and vertical directions.
  • the probe card is a replaceable part that is attached to the test head and includes a plurality of wires and a plurality of probe pins electrically connected to the wires.
  • the semiconductor wafer before being diced is placed on a stage, and the probe pins are brought into contact with the electrodes of the semiconductor products collectively formed on the wafer, so that a current flowing between the electrodes is obtained. Is measured, and defective products are identified by inspection of electrical characteristics.
  • the inspection method of the present invention is known as an inspection apparatus for a semiconductor wafer, a wafer probe which has not been used for inspection of a high-frequency package and / or a packaged high-frequency element has been disclosed. It is characterized in that it is used for inspection. Specifically, the above-mentioned collective substrate is placed on the stage of a wafer probe with the element mounting area side down, and probe pins are brought into contact with the electrodes on the back surface of the substrate to inspect individual high-frequency elements. . Before mounting the device, various inspections can be performed on the front side of the board.
  • a semiconductor wafer inspection method using a wafer prober can be used almost as it is.
  • Wafer prober inspection processing capacity does not exceed 1 second per product area even in precision measurement.
  • Multiple high-frequency devices (or packages) may be inspected simultaneously by applying a multi-prober. In this case, the inspection time per product area is reduced to 1/2 to 1/3 second.
  • the calibration up to the probe tip can be performed by using the calibration substrate.
  • the intrinsic characteristics of the product can be accurately measured. It is also easy to inspect temperature characteristics. Quality assurance regarding temperature characteristics has always been a major problem with ceramic electronic components. Major changes, such as maintenance, were necessary and were not realistic.
  • a wafer prober is a small device that can be carried around and can be calibrated at the probe level such as S-LT (Short-Open-Load-Through) calibration. Precise measurement can be easily performed.
  • the high-frequency element package of the present invention can be applied to a wide range of high-frequency elements of several tens of MHz to 100 GHz.
  • Electrodes and conductive lines are formed on a 0.64 mm thick 5 mm square 96 alumina substrate by thick film printing using a thick film conductor paste of Ag-Pd alloy (Fig. 3 (b)).
  • silicone oil content 0.6 wt
  • silica fine powder with an average particle size of 5 zm as inorganic filler and epoxy as hardener
  • BPA bisphenol A resole type phenolic resin
  • an adhesive containing bisphenol A-type epoxy resin as the main component is adjusted in advance, and the surface tension of the adhesive before bonding is equal to the surface tension of the resin on the surface to be bonded.
  • Epoxy adduct (curing agent), inorganic fine particles, and varnish are added and ripened so that the state can be realized, and the coating is applied to the surface to be bonded.
  • Alumina ceramic with a thickness (wall thickness) of 0.5 mm in dry air Sealing was performed by bonding a cap made of glass (Fig. 3 ( ⁇ )).
  • the above package was kept in an environment of 12 It :, 2 atm, and 100% humidity in an environmental tester, and the characteristic degradation was evaluated using the transmission characteristics (201 ogMagl SI) as an index.
  • the same test was performed on a SAW filter module manufactured in the same manner as above except that the organic polymer cured layer was not provided.
  • the SAW filter module of the present invention maintained almost the initial characteristics even after the elapse of 50 hours, indicating that the SAW filter module of the present invention has excellent airtightness. Further, in the comparative test example, remarkable deterioration of characteristics was observed after 50 hours, and it was confirmed that the effect of the present invention was at a level that could not be realized by mere sealing with an adhesive.
  • a silica glass paste (same as the sample A in (b) below) was printed on a 96-alumina substrate so as to have a thickness of 15 m, and was fired at 850 ° C. When the surface after firing was observed with an electron microscope, it was confirmed that fine crystals had precipitated. Was done. This is considered to be aluminobarium silicate-based microcrystals.
  • a water drop was dropped on the surface of the crystallized silica glass using a contact angle goniometer, and the contact angle was measured. The result was 8 to 15 °.
  • the contact angle was 70-80 ° on a 96-alumina substrate with a clean surface without a crystallized silica glass coating layer, confirming that the application of the crystallized silica glass layer was useful for improving wettability.
  • Electrodes and conductor lines are formed on a 0.64 mm thick 5 mm square 96 alumina substrate using an Ag-Pd alloy thick conductor paste (Fig. 3 (b)), and an inorganic glass material is further applied to the substrate surface. It was printed along its edge (Fig. 3 (c)). The same sample as above except that no inorganic glass layer was provided was prepared as a control.
  • FIG. 6 shows a microphone opening X structure constructed according to the present invention, wherein (a) is a plan view and (b) is a side view as viewed from the direction A in (a).
  • the microphone opening X structure package of the present invention shown in FIG. 6 has a conductor line G on a ceramic substrate 32 having a substantially rectangular element mounting area (a state where a GaAs FET bare chip 31 is mounted in the figure) in the center. , D, and S are formed at right angles from the region, and a sealing auxiliary layer 33 is provided circumferentially.
  • the sealing auxiliary layer 33 has a thickness sufficient to cover the conductor line at the intersection with the conductor line.
  • a 96-alumina thick-film printed circuit board is excellent in cost performance, but as a substrate material, 99.3% purity alumina substrate or 99.99% aluminum substrate is used. Mina substrates can also be used. The parasitic capacitance is suppressed by making G, D, and S orthogonal.
  • the conductor lines G, D, and S are planar lines formed on the substrate after firing, and are directly connected to the bare chip by wire bonding or the like.
  • the conductor line may be formed by thick-film printing as in the first embodiment, but a high-precision thin-film electrode can also be used for high-performance requirements and ultrahigh-frequency applications.
  • FIG. 6 shows a configuration example in which the conductor lines are the strip lines or coplanar lines shown in FIG.
  • the conductor lines G, D, and S are formed on a ceramic substrate 42 having a substantially rectangular element mounting area (a state in which a GaAsFET bare chip 41 is mounted in the figure) in the center.
  • Each substrate has a substrate structure formed at right angles from the region and provided with a sealing auxiliary layer 43 in a circumferential shape.
  • the sealing auxiliary layer 43 has a sufficient thickness to cover the conductor line at the intersection with the conductor line. After the formation of the sealing auxiliary layer 43, the sealing is performed by the cap member 45 via the adhesive layer 44.
  • the back surface of the substrate has a conductor layer 46 that covers substantially the entire surface.
  • the conductor layer 46 may be formed by thick film printing or by bonding a metal foil.
  • S is connected to the GND layer 46 on the back surface through a through hole.
  • the conductor lines G and D are arranged in a straight line, as in FIG. 6, so that the effect of suppressing the parasitic capacitance is high.
  • the degree of freedom in selecting the distributed constant lines is high and the frequency is increased. It has features that it is easy, it can suppress electrode loss and parasitic capacitance by using G and D distributed constant lines, and S can be grounded immediately to GND by through holes, so that GND impedance can be suppressed.
  • Well 3 Fig. 9 shows an example of the configuration of a SAW filter package 50 incorporating a balanced-unbalanced conversion circuit.
  • the point that the conductor line was provided on the substrate 52 on which the element 51 was mounted was the same as in Examples 1 and 2, but in this example, by further mounting the inductor and chip capacitor, The built-in balance-unbalance conversion circuit shown.
  • High-precision ink can be formed by thick film printing.
  • the conductive material can be formed by printing a thick film or a thin film, or by placing a thin wire in a coil shape.
  • a coil having a diameter of about 0.5 to 10 mm can usually be formed with a line width of about 60 to 300.
  • a coil having a line width of about 1 to 100 and a diameter of about 0.1 to 2 mm can be formed.
  • a rectangular spiral inductor (square-shaped inductor) is used, but the shape can be changed according to the purpose as long as it can be arranged on the substrate surface.
  • Such inductors include various inductor patterns composed of a crank or a loop or a conductor path forming a part thereof, in addition to the spiral inductors. More than H, usually about 1 to 50 nH is used.
  • the rectangular inductor has a conductor width of the inductor pattern and a space between conductor lines of 100 im, and is balanced by using an inductor having the following inductance value and a chip capacity.
  • Converter center frequency 8 5 o
  • the balanced converter is arranged only at the output terminal, but can be arranged also at the input terminal side.
  • the sealing structure is not shown in FIG. 9, the outline is the same as in Examples 1 and 2.
  • the inductor electrode and chip capacity need not be included in the hermetic seal unless they are directly connected to the SAW fill chip by wire bonding.
  • the SAW filter is hermetically sealed according to the first embodiment, and the conversion balance circuit is arranged on one of the front and back surfaces of the package substrate. May be connected.
  • the surface of a 96-alumina substrate 71 contains 90 individual substrate areas with an area of 5 mm wide and 5 mm long per area As described above, a divided region was provided in the center of the substrate, and a through hole 72 was formed on the divided line.
  • a conductive paste was filled and printed on the side surfaces of the through holes, and conductive patterns 73 were printed on the front and back surfaces of each individual substrate region.
  • a sealing auxiliary layer 74 is printed circumferentially between the element mounting area and the edge of the substrate area, and this is cured or fired to activate the surface.
  • the sealing auxiliary layer after the treatment is indicated by 75.
  • the SAW filter chip 76 was mounted in the center of the element mounting area, and wire bonding was performed. All of these operations are the same as in Example 1. Board table After wire bonding was completed in all the individual regions on the surface, a cap member 77 was adhered to the surface of the substrate and sealed to form a package structure 78. These operations are the same as in the first embodiment.
  • the above-mentioned collective substrate was placed on the stage of a commercially available wafer prober with its back surface facing upward, and the characteristics of each high-frequency element were inspected according to a previously programmed procedure.
  • the wafer probe was subjected to SOLT calibration in advance using a calibration substrate, and measurement was performed at 20 ° C.
  • the substrate was removed from the stage, and a total of 90 individual modules packaged with high-frequency devices were obtained by applying force along the dividing line.
  • the time required for the inspection was 90 seconds in total, which was significantly shorter than the case of inspecting the same number of individual high-frequency elements by the conventional method.
  • a GaAsFET chip and a dielectric resonator were used.
  • the entire circuit is hermetically sealed with a metal cap.
  • the conductor lines between the elements are formed as high-precision thin-film electrodes by the photoresist method.
  • Oscillators applied at 10 GHz or higher obtain oscillation characteristics by tuning the GaAs semiconductor for oscillation with a TE-type dielectric resonator (DRO).
  • DRO dielectric resonator
  • the DR ⁇ dimension is large compared to the micro X-package dimensions, and the DRO's resonant electromagnetic field is not disturbed.
  • the frequency increases, the DRO dimensions decrease, and the resonant fields become disturbed by the micro X-package.
  • the resonance of the package itself adversely affects the oscillation characteristics. Therefore, in higher frequency bands, it is necessary to mount GaAs semiconductors on a pair chip.
  • a high-performance millimeter-wave band module can be realized at a low cost, for example, by using an inexpensive sealing member or by performing impedance correction using a strip line with technical accumulation. .
  • the development of new technologies requires a large amount of development costs, and in the advanced technology field, reducing development costs is directly linked to lower product prices.
  • the sealing technology of the present invention does not require new technologies such as thick-film coplanar waveguides, which are being tried in band modules, and can achieve improved characteristics by applying stripline technology with accumulated technology to the millimeter-wave band. module To achieve both low price and high performance.
  • a high-frequency element package or a packaged high-frequency module can be manufactured and inspected as a collective substrate, the handling property is greatly improved, and the inspection is speeded up. But it has tremendous utility.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

A package for a high-frequency device, characterized in that high-precision electrodes are provided on both sides of a fired ceramic substrate, a cured sealing auxiliary layer of an organic polymer material or an inorganic material is formed along the periphery, a device is mounted on the substrate surrounded by the sealing auxiliary layer and electrically connected to the electrodes, and a cap member is bonded to the sealing auxiliary layer with an adhesive gas-tightly. The package can be manufactured and inspected at low cost and used in high-frequency range including the millimeter-wave band (20 100GHz).

Description

明 細 書  Specification
高周波素子用パッケージ 技術分野 Technical field for high-frequency device packages
本発明は、 高周波素子用パッケージ、 その製造方法及び高周波素子のパッ ケージング方法に関する。 背景技術  The present invention relates to a high-frequency element package, a method for manufacturing the same, and a method for packaging a high-frequency element. Background art
高周波機器の普及は著しく、 携帯電話機の運用台数は全世界で 1億 5千万 台を超え、 次世代型の携帯電話機も 2001年春には運用が始まる予定である。 また、 ディジタル衛星放送も 2000年秋に開始され、 2 1世紀を迎えるにあた り高周波機器は再び著しく伸長しょうとしている。 このような高周波機器に は、 表面弾性波(SAW)フィル夕、 あるいは、 MMIC (Mi crowave Mono l i th i c I n t egrated C i rcu i t)、 GaAsFET等の高周波用半導体が不可欠であり、 新型デ バイスの開発や改良が進められている。  The spread of high-frequency equipment is remarkable, and the number of mobile phones operated exceeds 150 million units worldwide. The operation of next-generation mobile phones is scheduled to begin in the spring of 2001. Digital satellite broadcasting also started in the fall of 2000, and in the 21st century, high-frequency equipment is about to grow significantly again. High-frequency semiconductors such as surface acoustic wave (SAW) filters or MMICs (Microwave Monolithic Integrated Circuits) and GaAsFETs are indispensable for such high-frequency devices. Is being developed and improved.
これらの高周波用半導体素子は、 例えば、 SAWフィル夕では湿度により表 面弾性波の速度が変化し、 また、 非酸化物半導体である GaAsは大気中で酸化 して高性能な特性が発現しなくなるため、 大気中の湿気または酸素等の流通 を遮断した条件下に保持することが不可欠である。 低周波半導体素子では、 この目的のために樹脂封止が慣用されているが、 SAWフィル夕ではその原理 上、 榭脂封止を用いることができない。 その他の高周波素子についても、 高 周波帯域では封止材料の誘電率が特性に悪影響を及ぼすため樹脂封止は好ま しくない。  In these high-frequency semiconductor devices, for example, in a SAW filter, the velocity of surface acoustic waves changes depending on the humidity, and GaAs, a non-oxide semiconductor, oxidizes in the air and does not exhibit high-performance characteristics. Therefore, it is indispensable to maintain the conditions in which the flow of moisture or oxygen in the atmosphere is cut off. Resin encapsulation is commonly used in low-frequency semiconductor devices for this purpose, but resin encapsulation cannot be used for SAW filters due to its principle. For other high-frequency devices, resin encapsulation is not preferred in the high-frequency band because the dielectric constant of the sealing material adversely affects the characteristics.
このため、 一般に、 高周波素子については、 中空構造のセラミックパッケ ージを用いて乾燥空気または窒素 ·希ガス等の不活性ガス中に気密封止する 構造が採られている。 気密封止構造としては、 高周波素子を金属ケースに封入する構造が知られ ているが、 金属ケース等は高価であり、 小型化や軽量化がしにくいため、 用 途が限定される。 For this reason, generally, a high-frequency element is hermetically sealed in dry air or an inert gas such as nitrogen or a rare gas using a hollow ceramic package. As a hermetic sealing structure, a structure in which a high-frequency element is sealed in a metal case is known. However, the use of a metal case or the like is limited because it is expensive and it is difficult to reduce the size and weight.
高周波素子を基板上に搭載した後、 セラミックや金属等の蓋体をハンダ、 低融点ガラスまたは熱硬化性樹脂等を用いて基板上に接合する構造も知られ ている。  A structure is also known in which a high-frequency element is mounted on a substrate, and then a lid made of ceramic, metal, or the like is bonded to the substrate using solder, low-melting glass, thermosetting resin, or the like.
しかし、 キャップ型 (すなわち、 断面がコの字または円弧状の) 蓋体を用 いる場合、 その端面をハンダゃフリットガラスのような接合材料によって基 板に接合するため、 基板上の素子が熱によってダメージを受けるおそれがあ る。 キャップ型蓋体を接着剤によって基板に接合する封止法も検討されてい るが、 接着剤層と基板及びキャップ部材との熱膨張係数が異なるため、 素子 を使用する際、 接着部に熱応力が加わり、 経時的に気密性が劣化する。 この ため、 これまでは実用的には用いられていない。  However, when a cap-type (that is, a U-shaped or arc-shaped cross section) lid is used, the end surface of the lid is bonded to the substrate with a bonding material such as solder frit glass, so that the elements on the substrate are thermally heated. May be damaged by the A sealing method in which the cap-type lid is bonded to the substrate with an adhesive is also being studied. And the airtightness deteriorates over time. For this reason, it has not been used practically until now.
そこで、 従来は、 積層技術を用いて底面と壁体を有するセラミックパッケ ージを形成し、 開放された上面は蓋 (リツド) で封止する構造が広く用いら れている (例えば、 特開平 1卜 135661号公報) 。  Therefore, conventionally, a structure in which a ceramic package having a bottom surface and a wall body is formed by using a lamination technique, and an open upper surface is sealed with a lid (lid) has been widely used (for example, see Japanese Patent Application Laid-Open No. H10-163873). No. 135661).
従来の積層セラミックパッケージの典型的な構造を、 第 1 0図(a)及び (b) A typical structure of a conventional multilayer ceramic package is shown in Figs. 10 (a) and (b).
(いずれも断面図) に模式的に示す。 (All are cross-sectional views).
第 1 0図では、 積層セラミックパッケージ 6 0は、 中央部が単層で周囲が 2〜3層の積層構造を有しており、 後者によって階段状の壁体が形成されて いる。 高周波用半導体素子 (ベアチップ) 6 1はパッケージ中央の凹部 (図 では第 1層上) に搭載され、 棚部 (同第 2層) に形成された電極または導体 線路 6 2にワイヤボンディング 6 3等によって接続される。 パッケージの縁 部にはさらに第 3層が設けられており、 これに例えばシールリング 6 4等を 介して蓋 6 5 (—般には金属リツド) をシーム溶接することにより、 素子に 影響を及ぼすことなく気密封止が実現され、 内部は高い気密性が保たれる。 なお、 積層構造は 2層の場合もあり得るし、 4層以上の場合もあり得る。 前記棚部に形成されたストリップ線路等の信号伝送線路 6 2は、 パッケー ジ 6 0の側面及び底面に設けられた外部電極 6 6に接続されるか (第 1 0図 (a) ) 、 パッケージの底面を貫いて設けられた充填ビアまたはスルーホール 6 7によって外部電極 6 6に接続される (第 1 0図(b) ) 。 これによつて、 素子 (ベアチップ) 6 1への高周波信号の入出力が行われる。 In FIG. 10, the laminated ceramic package 60 has a laminated structure in which the central portion is a single layer and the periphery is two to three layers, and the latter forms a stepped wall. The high-frequency semiconductor element (bare chip) 61 is mounted in a concave part (on the first layer in the figure) in the center of the package, and is wire-bonded to the electrode or conductor line 62 formed on the shelf (the second layer). Connected by A third layer is further provided on the edge of the package, and the lid 65 (usually a metal lid) is seam-welded to the element via, for example, a seal ring 64, thereby affecting the element. Airtight sealing is realized without any problems, and high airtightness is maintained inside. It should be noted that the laminated structure may have two layers, or may have four or more layers. The signal transmission line 62 such as a strip line formed on the shelf is connected to external electrodes 66 provided on the side and bottom surfaces of the package 60 (FIG. 10 (a)), Are connected to the external electrodes 66 by filling vias or through holes 67 provided through the bottom surface of the substrate (FIG. 10 (b)). Thereby, input / output of a high-frequency signal to / from the element (bare chip) 61 is performed.
このような従来の積層セラミックパッケージは、 所定形状に成形されたセ ラミックグリーンシ一ト上に導体ペーストを厚膜印刷した後、 これらのシー トを積層し、 個別ピースに切断し、 しかる後、 グリーンシートの焼成と同時 に電極及び導体線路の焼成を行って形成される。 従って、 (1 )素子の搭載領 域、 (2)素子 (ベアチップ) 搭載用の内部電極、 パッケージングされた素子 モジュールを外部回路と接続するための外部電極及び内部 ·外部電極間を接 続する導体線路、 並びに(3)封止用リツドの支持体が慣用の積層技術を適用 して同時に形成できるという利点を有する。  In such a conventional multilayer ceramic package, a conductive paste is printed on a ceramic green sheet formed in a predetermined shape in a thick film, these sheets are laminated, cut into individual pieces, and then, It is formed by firing the electrodes and conductor lines simultaneously with firing the green sheet. Therefore, (1) the mounting area of the element, (2) the internal electrode for mounting the element (bare chip), the external electrode for connecting the packaged element module to the external circuit, and the connection between the internal and external electrodes It has the advantage that the conductor line and (3) the support for the sealing lid can be formed simultaneously by applying a conventional lamination technique.
しかし、 従来構造のパッケージでは、 1 0 G H zを超える高周波領域で信 号の特性劣化が大きいことが知られている。 このため、 積層セラミックパッ ケージにおいて入出力用の伝送線路部分に厚膜印刷したコプレーナ型導波線 路を適用することによりミリ波帯 (2 0〜 1 0 0 G H z ) に対応させたパッ ケージ構造も種々提案されている (例えば、 特開平 10- 303333号公報) 。 し かし、 コプレーナ型導波線路は高周波伝送には適するものの、 一般に設計が 難しく積層セラミックパッケージに用いた場合には構造が複雑になる。 また、 パッケージはパッケージに含まれる配線やボンディングワイヤ等に より寄生容量を不可避的に伴うが、 寄生容量が与えるインピーダンスは周波 数が高くなるほど大きくなり、 その影響も大きくなる。 これは、 キャパシタ 等により補正が可能であるが、 従来の積層パッケージでは、 パッケージごと に寄生容量が異なるためインピーダンスの高精度な補正は困難であり、 また、 補正用キャパシ夕の搭載はパッケージ構造のさらなる複雑化を招く。 さらに、 従来のパッケージ製造方法及びパッケージング方法では、 ミリメ ―トルオーダーのパッケージピースを焼成し、 これに素子を搭載しワイヤボ ンデイングし、 リツドを溶接する。 すなわち、 微小なセラミックパッケージ や半導体チップ等の取扱いが必要であり、 部品の小型化が生産コス卜の増大 をもたらしていた。 また、 素子搭載用の内部電極がパッケージ内の凹部に配 置されているため、 検査には、 個々の製品に応じた治具や検査用パッドの製 造等が必要となる。 さらにまた、 検査の自動化を行うためには微小部品の取 扱いに適した大掛かりな位置決め装置を含む検査装置が必要である。 加え て、 治具の構成ができないために、 個々のパッケージについての温度特性そ の他の精密な検査を行うのは実際上困難であった。 However, it is known that in the package of the conventional structure, the signal characteristic degradation is large in a high frequency region exceeding 10 GHz. For this reason, a package structure that is compatible with the millimeter-wave band (20 to 100 GHz) by applying a thick-film printed coplanar waveguide to the input and output transmission lines in the multilayer ceramic package. Various proposals have been made (for example, JP-A-10-303333). However, although a coplanar waveguide is suitable for high-frequency transmission, it is generally difficult to design, and its structure becomes complicated when used in a multilayer ceramic package. In addition, the package is inevitably accompanied by parasitic capacitance due to wiring and bonding wires included in the package. However, the impedance given by the parasitic capacitance increases as the frequency increases, and the influence increases. This can be corrected by a capacitor or the like, but in a conventional stacked package, it is difficult to correct the impedance with high accuracy because the parasitic capacitance differs for each package. In addition, the mounting of the correction capacity further complicates the package structure. Further, in the conventional package manufacturing method and packaging method, a package piece of a millimeter order is baked, an element is mounted on the package piece, wire-bonded, and a lip is welded. In other words, it was necessary to handle micro ceramic packages and semiconductor chips, etc., and miniaturization of components had increased production costs. In addition, since the internal electrodes for mounting the elements are arranged in recesses in the package, the inspection requires the manufacture of jigs and inspection pads for each product. Furthermore, in order to automate the inspection, an inspection device including a large-scale positioning device suitable for handling minute components is required. In addition, due to the inability to configure the jig, it was practically difficult to perform temperature characteristics and other precise inspections on individual packages.
本発明は、 上述した従来技術による高周波用パッケージにおける問題点の 解消を課題とするものであり、 低コストで製造及び検査が可能であり、 か つ、 ミリ波帯 (2 0〜 1 0 0 G H z ) を含む高周波領域においても使用し得 る高性能パッケージ構造を提供することを目的とする。 また、 本発明は、 か かる高性能な高周波用パッケージの廉価かつ効率的な製造方法及びパッケ一 ジング方法を提供することを目的とする。 発明の開示  An object of the present invention is to solve the above-described problems in the high-frequency package according to the related art, which can be manufactured and inspected at low cost, and has a millimeter wave band (20 to 100 GH). An object of the present invention is to provide a high-performance package structure that can be used even in a high frequency region including z). Another object of the present invention is to provide an inexpensive and efficient manufacturing method and a packaging method for such a high-performance high-frequency package. Disclosure of the invention
本発明者らは、 従来、 高周波素子に必要なレベルの気密封止を行うために 必要と考えられてきた多層基板構造のパッケージにおける上述の問題点につ いて検討し、 これらの多層基板構造では、 電極及び導体線路の焼成による形 成を基板材料の焼成と同時に行うために基板材料の焼成収縮に起因して導体 部分の寸法変動及び不均一化が避けられず、 これが、 高周波帯における信号 劣化の一因となっており、 また、 パッケージごとの寄生容量のばらつき (不 均一性) の主な原因となっているとの結論を得た。 そして、 (1)高周波素子のパッケージにおいて、 焼成済みのセラミック基 板上に、 素子の搭載に必要な電極及び入出力用の導体線路及び Zまたは回路 を設け、 有機高分子材料の硬化体または無機材料からなる封止補助層を介し てキャップ型の蓋体を接着剤を用いて接着することにより、 高水準用の気密 封止がなされ、 かつ、 高周波帯で優れた特性を示すパッケージが実現できる こと、 (2)特に(1)の構造においては導体線路の線路幅及び線路長について高 精度なものが得られるため、 インピーダンス補正用にストリップ線路等を用 いることにより、 高周波でも安定したインピーダンスの微調整が可能とな り、 GaAsFETや MMIC等の高周波用半導体について高特性を実現できることを 見出した。 また、 (3)焼成済みの基板上に複数のパッケージ用領域を設け、 各領域について上記(1)〜(2)によるパッケージ基板構造を形成し、 素子の実 装、 キャップ部材による気密封止を行った後に、 個別のピースに分割する方 法を採ることにより、 製造プロセスが効率化され、 さらに、 かかる集合基板 について、 半導体ゥエー八検査技術を応用することにより、 検査の効率化 - 高度化 (精密検査 ·温度特性検査) が実現できることを見出し、 本発明を完 成するに至った。 The present inventors have studied the above-mentioned problems in a package having a multilayer substrate structure, which has been conventionally considered to be necessary for hermetic sealing at a required level for a high-frequency element. Since the formation of the electrodes and conductor lines by firing is performed simultaneously with the firing of the substrate material, dimensional fluctuations and non-uniformity of the conductors due to shrinkage of firing of the substrate material are inevitable, which causes signal degradation in the high frequency band. It was also concluded that this was one of the main causes of the parasitic capacitance variation (non-uniformity) from package to package. (1) In the package of the high-frequency element, the electrodes necessary for mounting the element, the input / output conductor lines and the Z or circuit are provided on the fired ceramic substrate, and the cured organic polymer material or inorganic material is provided. By bonding the cap-type lid with an adhesive via a sealing auxiliary layer made of a material, a high-level hermetic seal is achieved, and a package exhibiting excellent characteristics in a high frequency band can be realized. (2) In particular, in the structure of (1), a high-precision line width and line length of the conductor line can be obtained. Therefore, by using a strip line for impedance correction, stable impedance can be obtained even at high frequencies. We have found that fine adjustment is possible and that high characteristics can be realized for high-frequency semiconductors such as GaAs FETs and MMICs. (3) A plurality of package regions are provided on the fired substrate, and a package substrate structure according to the above (1) to (2) is formed for each region, and element mounting and hermetic sealing with a cap member are performed. After that, the process of dividing into individual pieces is adopted to improve the efficiency of the manufacturing process. In addition, by applying the semiconductor A8 inspection technology to such an assembled substrate, the inspection efficiency is improved-advanced ( Precision inspection and temperature characteristic inspection), and completed the present invention.
すなわち、 本発明は以下の高周波素子用パッケージ、 その製造方法及び高 周波素子のパッケージング方法を提供する。  That is, the present invention provides the following high-frequency element package, a method of manufacturing the same, and a method of packaging the high-frequency element.
〔1〕 (a)高周波用素子搭載領域を有するセラミック基板と(b)前記基板の 表面に密着させたときに素子を収容するのに十分な大きさの空間を形成する 形状及び高さを有するキャップ部材とを含む高周波素子用パッケージであつ て、 前記セラミック基板が、 基板材料の焼成後に形成された素子搭載用の内 部電極、 外部電極及びその間を接続する導体線路、 並びに、 素子搭載領域と 基板緣部との間において前記キャップ部材の端面と適合する形状に設けられ た有機高分子材料の硬化体または無機材料からなる封止補助層を有し、 素子 を前記領域に搭載し前記内部電極と電気的に接続した後、 前記キャップ部材 を接着剤によつて有機高分子材料硬化層上に接着して気密封止してなること を特徴とする高周波素子用パッケージ。 [1] (a) a ceramic substrate having a high-frequency element mounting area; and (b) a shape and height that form a space large enough to accommodate the element when brought into close contact with the surface of the substrate. A package for a high-frequency element including a cap member, wherein the ceramic substrate includes: an internal electrode for mounting the element formed after firing of the substrate material; an external electrode; a conductor line connecting between the electrodes; and an element mounting area. A sealing auxiliary layer made of a cured body of an organic polymer material or an inorganic material provided in a shape compatible with the end face of the cap member between the substrate and the portion; After being electrically connected to the cap member A package for a high-frequency element, wherein the package is hermetically sealed by adhering to a cured organic polymer material layer with an adhesive.
〔2〕 前記封止補助層が、 紫外線照射またはプラズマ処理により表面が活 性化処理されたものである前記 1に記載の高周波素子用パッケージ。  [2] The high-frequency element package according to [1], wherein the sealing auxiliary layer has a surface activated by ultraviolet irradiation or plasma treatment.
〔 3〕 前記有機高分子材料がエポキシ系樹脂、 フエノール系樹脂またはェ ポキシフエノール系榭脂から選択される樹脂を含む前記 1に記載の高周波素 子用パッケージ。  [3] The package for a high frequency device according to [1], wherein the organic polymer material includes a resin selected from an epoxy resin, a phenol resin, and an epoxy phenol resin.
〔4〕 前記無機材料が結晶化シリカガラスである前記 1に記載の高周波素 子用パッケージ。  [4] The package for a high-frequency device according to the above item 1, wherein the inorganic material is crystallized silica glass.
〔 5〕 パッケージングされた素子のインピーダンスを前記導体線路により 最適化した前記 1に記載の高周波素子用パッケージ。  [5] The high-frequency element package according to the above item 1, wherein the impedance of the packaged element is optimized by the conductor line.
〔 6〕 前記導体線路が薄膜形成により形成された高精度分布定数線路を含 む前記 1に記載の高周波素子用パッケージ。  [6] The high-frequency element package according to [1], wherein the conductor line includes a high-precision distributed constant line formed by forming a thin film.
〔 7〕 前記導体線路がコプレーナ線路を含む前記 1に記載の高周波素子用 パッケージ。  [7] The package for a high-frequency element according to the above item 1, wherein the conductor line includes a coplanar line.
〔 8〕 前記セラミック基板がアルミナまたはアルミナよりも大きな誘電率 を有する誘電体材料から選択される前記 1に記載の高周波素子用パッケ一 ン  [8] The high-frequency element package according to the above item 1, wherein the ceramic substrate is selected from alumina or a dielectric material having a higher dielectric constant than alumina.
〔 9〕 前記キャップ部材がセラミック、 金属または高分子材料から選択さ れる前記 1に記載の高周波素子用パッケージ。  [9] The package for a high-frequency device according to the above item 1, wherein the cap member is selected from a ceramic, a metal, and a polymer material.
〔 1 0〕 前記基板表面にらせんインダク夕及び/またはチップキャパシタ を含む回路を設けた前記 1に記載の高周波素子用パッケージ。  [10] The high-frequency element package according to [1], wherein a circuit including a spiral inductor and / or a chip capacitor is provided on the surface of the substrate.
〔 1 1〕 前記素子が SAWフィル夕、 Ml MMI Cまたは GaAsFETである前記 1 に記載の高周波素子用パッケージ。  [1 1] The package for a high-frequency device according to the above 1, wherein the device is a SAW filter, Ml MMIC or GaAs FET.
〔 1 2〕 前記素子が SAWフィルタであり、 基板上に平衡-不平衡変換回路を 有する前記 1 1に記載の SAWフィル夕用パッケージ。 〔1 3〕 前記素子が GaAsFETであり、 ゲ一卜(G)、 ドレイン(D)に接続す る各導体線路が直線上に、 ソース (s ) に接続する分布定数線路がこれに直 交するように前記基板上に設けられていることを特徴とする前記 1 1に記載 の GaAsFET用パッケージ。 [12] The SAW filter package according to item 11, wherein the element is a SAW filter, and the substrate has a balanced-unbalanced conversion circuit. [13] The element is a GaAs FET, and the conductor lines connected to the gate (G) and the drain (D) are on a straight line, and the distributed constant line connected to the source (s) is orthogonal to this. 11. The GaAs FET package according to the item 11, wherein the GaAs FET is provided on the substrate.
〔1 4〕 導体線路で接続された複数の素子搭載領域を基板上に有し、 これ らの素子を含む全体またはこれらの素子のうち気密封止を要する素子の 1以 上が前記キヤップ部材により前記 1に記載のパッケージ構造によって封止さ れる高周波モジュール用パッケージ。  [14] A plurality of element mounting regions connected by conductor lines are provided on a substrate, and the whole including these elements or one or more of these elements that need to be hermetically sealed by the cap member. 2. A high-frequency module package sealed by the package structure according to 1.
〔 1 5〕 焼成されたセラミック基板に素子搭載用の内部電極、 外部電極及 びその間を接続する導体線路を形成する工程;前記基板の表面に密着させた ときに素子を収容するのに十分な大きさの空間を形成する形状及び高さを有 するキャップ部材を形成する工程;並びに、 少なくとも前記内部電極と基板 緣部との間において前記キャップ部材の端面と適合する形状に、 有機高分子 材料層を印刷し硬化するか、 無機材料層を設ける工程を含む、 前記 1乃至 1 4のいずれかに記載の高周波素子用パッケージを製造する方法。  [15] A step of forming an internal electrode for mounting an element, an external electrode, and a conductor line for connecting between them on a fired ceramic substrate; sufficient contact with the surface of the substrate to accommodate the element Forming a cap member having a shape and a height to form a space having a size; and an organic polymer material having a shape at least between the internal electrode and the substrate portion that is compatible with the end face of the cap member. 15. The method for producing a high-frequency element package according to any one of the above items 1 to 14, comprising a step of printing and curing a layer or providing an inorganic material layer.
〔 1 6〕 前記有機高分子材料硬化層または無機材料層の表面を紫外線照射 またはプラズマ処理により活性化する工程をさらに含む前記 1 5に記載の高 周波素子用パッケージ製造方法。  [16] The method of manufacturing a package for a high-frequency device according to the above [15], further comprising a step of activating the surface of the cured organic polymer material layer or the inorganic material layer by ultraviolet irradiation or plasma treatment.
〔1 7〕 セラミック基板上にスルーホールを含む分割線を縦横に設けるこ とによってパッケージ用基板領域を複数形成する工程;前記スルーホールを 通って基板表裏面を導通する導体路を形成する工程;各基板領域において素 子を搭載する側の面に素子搭載用の内部電極及び内部電極と前記スルーホー ル内導体路とを接続する導体線路を形成する工程:各基板領域において素子 を搭載する面とは反対側の面に前記スルーホール内導体路と電気的に接続す る外部電極を形成する工程;各基板領域において基板表面に密着させたとき に素子を収容するのに十分な大きさの空間を形成する形状及び高さを有する キャップ部材を形成する工程;各基板領域において、 少なくとも前記内部電 極と基板領域縁部との間において前記キャップ部材の端面と適合する形状 に、 有機高分子材料層を印刷し硬化するか、 無機材料層を設ける工程;並び に、 前記基板を前記分割線に沿って分割する工程を含む方法により、 前記基 板領域とキャップ部材とをもって前記 1乃至 1 5のいずれかに記載されたパ ッケージ基板とキヤップ部材とする高周波素子用パッケージの製造方法。[17] a step of forming a plurality of package substrate regions by providing vertical and horizontal dividing lines including a through-hole on a ceramic substrate; a step of forming a conductor path for conducting the front and back surfaces of the substrate through the through-hole; Forming an internal electrode for mounting an element and a conductor line connecting the internal electrode and the conductor path in the through hole on the surface on the side where the element is mounted in each substrate region: a surface on which the element is mounted in each substrate region; Forming an external electrode on the opposite surface to be electrically connected to the conductor path in the through-hole; in each substrate region, a space large enough to accommodate the element when brought into close contact with the substrate surface Having a shape and height to form Forming a cap member; in each substrate region, printing and curing an organic polymer material layer in a shape compatible with the end surface of the cap member at least between the internal electrode and the edge of the substrate region; A package substrate according to any one of the above items 1 to 15, including a step of providing a material layer; and a step of dividing the substrate along the division line. And a method for manufacturing a high-frequency device package as a cap member.
〔1 8〕 接着工程に先立ち、 前記有機高分子材料硬化層または無機材料層 の表面を紫外線照射またはプラズマ処理により活性化する工程をさらに含む 前記 1 7に記載の高周波素子用パッケージ製造方法。 [18] The method for manufacturing a package for a high-frequency element according to [17], further comprising a step of activating the surface of the cured organic polymer material layer or the inorganic material layer by ultraviolet irradiation or plasma treatment prior to the bonding step.
〔1 9〕 前記分割に先立ち、 さらに各基板領域の電気的特性を検査するェ 程を含む前記 1 7または 1 8に記載の高周波素子用パッケージの製造方法。 [19] The method for manufacturing a high-frequency element package according to the item 17 or 18, further comprising a step of inspecting electrical characteristics of each substrate region before the division.
〔2 0〕 前記検査が半導体検査用のゥェ一ハプローバを用いて行われる前 記 1 9に記載の高周波素子用パッケージの製造方法。 [20] The method for manufacturing a high-frequency element package according to item 19, wherein the inspection is performed using a semiconductor prober prober.
〔2 1〕 セラミック基板上にスルーホールを含む分割線を縦横に設けるこ とによってパッケージ用基板領域を複数形成する工程;前記スルーホールを 通って基板表裏面を導通する導体路を形成する工程; 各基板領域において素 子を搭載する側の面に素子搭載用の内部電極及び内部電極と前記スルーホー ル内導体路とを接続する導体線路を形成する工程;各基板領域において素子 を搭載する側とは反対側の面に前記スルーホール内導体路と電気的に接続す る外部電極を形成する工程;各基板領域において基板表面に密着させたとき に素子を収容するのに十分な大きさの空間を形成する形状及び高さを有する キャップ部材を用意する工程;各基板領域において、 少なくとも前記内部電 極と基板領域縁部との間において前記キャップ部材の端面と適合する形状 に、 有機高分子材料層を印刷し硬化するか、 無機材料層を設けて封止補助層 とする工程;各基板領域において、 高周波用素子を搭載し前記内部電極と電 気的に接続した後、 前記キャップ部材を接着剤によって前記封止補助層上に 接着して気密封止する工程;並びに、 前記基板を前記分割線に沿って分割す る工程を含む、 高周波素子のパッケージング方法。 [21] a step of forming a plurality of package substrate regions by providing vertical and horizontal dividing lines including a through hole on a ceramic substrate; a step of forming a conductor path for conducting the front and back surfaces of the substrate through the through hole; Forming an internal electrode for mounting the element and a conductor line connecting the internal electrode and the conductor path in the through-hole on the surface on the side where the element is mounted in each substrate region; Forming an external electrode on the opposite surface to be electrically connected to the conductor path in the through-hole; in each substrate region, a space large enough to accommodate the element when brought into close contact with the substrate surface Preparing a cap member having a shape and a height to form a cap; at each substrate region, at least an end of the cap member between the internal electrode and an edge of the substrate region; A step of printing and curing an organic polymer material layer in a shape compatible with the above, or providing an inorganic material layer as a sealing auxiliary layer; in each substrate region, a high-frequency element is mounted and electrically connected to the internal electrode. After connecting the cap member to the sealing auxiliary layer with an adhesive A method for packaging a high-frequency element, comprising: bonding and hermetically sealing; and dividing the substrate along the division line.
〔2 2〕 接着工程に先立ち、 前記有機高分子材料硬化層または無機材料層 の表面を紫外線照射またはプラズマ処理により活性化する工程をさらに含む 前記 2 1に記載の高周波素子のパッケージング方法。  [22] The method for packaging a high-frequency device according to the item 21, further comprising a step of activating the surface of the cured organic polymer material layer or the inorganic material layer by ultraviolet irradiation or plasma treatment prior to the bonding step.
〔2 3〕 前記分割前のいずれかの段階において、 各基板領域の電気的特性 を検査する工程をさらに含む前記 2 1または 2 2に記載の高周波素子のパッ ケージング方法。  [23] The packaging method for a high-frequency element according to the above item 21 or 22, further comprising a step of inspecting electrical characteristics of each substrate region at any stage before the division.
〔2 4〕 前記検査が半導体検査用のゥェ一ハプローバを用いて行われる前 記 2 3に記載の高周波素子のパッケージング方法。 図面の簡単な説明  [24] The packaging method for a high-frequency device according to the above item 23, wherein the inspection is performed using a semiconductor prober prober. BRIEF DESCRIPTION OF THE FIGURES
第 1図(a)及び (b)は、 それぞれ本発明の高周波素子用パッケージの基板構 造を模式的に表した平面図及び断面図である。  FIGS. 1 (a) and 1 (b) are a plan view and a cross-sectional view, respectively, schematically showing the substrate structure of the high-frequency element package of the present invention.
第 2図(a)及び (b)は、 それぞれ本発明の高周波素子用パッケージの封止構 造を模式的に表した平面図及び断面図。  2 (a) and 2 (b) are a plan view and a cross-sectional view, respectively, which schematically show the sealing structure of the high-frequency element package of the present invention.
第 3図は、 本発明による高周波素子のパッケージングプロセスを模式的に 表した斜視図である。  FIG. 3 is a perspective view schematically showing a packaging process of a high-frequency device according to the present invention.
第 4図は、 ストリップ線路及びコプレーナ線路の構造を模式的に表した平 面図である。  FIG. 4 is a plan view schematically showing the structures of the strip line and the coplanar line.
第 5図は、 従来のマイク口 X構造を模式的に表した平面図である。  FIG. 5 is a plan view schematically showing a conventional microphone opening X structure.
第 6図(a)及び (b)は、 それぞれ本発明によるマイクロ X構造を模式的に表 した平面図及び封止構造の一部を除いて示した側面図である。  6 (a) and 6 (b) are a plan view schematically showing the micro X structure according to the present invention and a side view excluding a part of the sealing structure, respectively.
第 7図(a)は本発明による分布定数型 GaAsFETパッケージの構造を模式的に 表した側面図 (但し、 封止構造の一部を除いて示した。 ) であり、 同図(b) 及び (c)は (a)に対応する 2種類の構造を模式的に示した平面図である。 第 8図は平衡-不平衡変換回路の一例を示す回路図である。 FIG. 7 (a) is a side view schematically showing the structure of the distributed constant type GaAsFET package according to the present invention (however, excluding a part of the sealing structure). FIG. 7 (b) and FIG. (c) is a plan view schematically showing two types of structures corresponding to (a). FIG. 8 is a circuit diagram showing an example of a balanced-unbalanced conversion circuit.
第 9図は、 本発明による平衡-不平衡変換回路内蔵型パッケージの構造を 模式的に表した平面図である。  FIG. 9 is a plan view schematically showing the structure of a package with a built-in balanced-unbalanced conversion circuit according to the present invention.
第 1 0図は、 従来の高周波素子用パッケージの構造を、 外部電極との接続 構造の違いに応じて ω及び (b)として模式的に表した断面図である。  FIG. 10 is a cross-sectional view schematically showing a structure of a conventional high-frequency element package as ω and (b) according to a difference in a connection structure with an external electrode.
第 1 1図は、 本発明による高周波素子の集合基板パッケージングプロセス を模式的に表した説明図である。  FIG. 11 is an explanatory view schematically showing a collective substrate packaging process for a high-frequency device according to the present invention.
第 1 2図は、 第 1 1図に引き続いて本発明による高周波素子の集合基板パ ッケ一ジングプロセスを模式的に表した説明図である。  FIG. 12 is an explanatory view schematically showing a packaging substrate packaging process of the high-frequency device according to the present invention, following FIG.
第 1 3図は、 第 1 2図に引き続いて本発明による高周波素子の集合基板パ ッケ一ジングプロセスを模式的に表した説明図である。  FIG. 13 is an explanatory diagram that schematically shows a packaging substrate packaging process of the high-frequency device according to the present invention, following FIG. 12.
第 1 4図は、 従来技術による 1 0 G H z帯発振器と本発明技術による 1 0 G H z帯発振器の比較模式図である。  FIG. 14 is a schematic diagram showing a comparison between a 10 GHz band oscillator according to the prior art and a 10 GHz band oscillator according to the present invention.
高周波素子用パッケージ High frequency device package
第 1〜2図に、 本発明の高周波素子用パッケージ 1 0の基本的な構造を示 す。 第 1図は封止前のパッケージ基板 1を模式的に示したものであり (第 1 図 ) :素子搭載面を示す平面図。 第 1図(b) :図 1 (a)のパッケージ基板を 図中の A— A ' に沿って切断した断面図) 、 第 2図はキャップ部材 8を用い て素子を封止した状態での平面図と断面図である。 また、 第 3図には、 この パッケージの製造とパッケージングの流れを模式的に示した。  1 and 2 show the basic structure of the high-frequency element package 10 of the present invention. FIG. 1 schematically shows the package substrate 1 before sealing (FIG. 1): a plan view showing an element mounting surface. FIG. 1 (b) is a cross-sectional view of the package substrate of FIG. 1 (a) taken along the line AA ′ in the figure), and FIG. 2 is a state in which the element is sealed using a cap member 8. It is a top view and a sectional view. Fig. 3 schematically shows the flow of manufacturing and packaging of this package.
第 1図 (第 3図(d)に相当する。 ) に示すように、 本発明のパッケージ基 板 1は、 素子搭載領域 2を有する焼成済みセラミック基板上に前記素子への 入出力を行うための電極、 導体線路及び Zまたは回路 (ベアチップ搭載用の 内部電極 3、 パッケージ実装用の外部電極 6及びこの間を接続する導体線路 4と側面電極 5 ) を形成し、 素子搭載領域 2の外周に沿って有機高分子材料 の硬化体または無機材料からなる封止補助層 7を設けたものである。 好まし くは封止補助層には表面活性化処理を施す。 第 1図に示すように内部電極 3 と導体線路 4は一体化されていてもよい。 As shown in FIG. 1 (corresponding to FIG. 3 (d)), the package substrate 1 of the present invention is used for performing input and output to and from the fired ceramic substrate having the element mounting area 2. And electrodes or conductor lines and Z or circuit (inner electrode 3 for mounting bare chip, outer electrode 6 for package mounting and conductor line 4 and side electrode 5 connecting between them) along the outer periphery of element mounting area 2. And a sealing auxiliary layer 7 made of a cured body of an organic polymer material or an inorganic material. Preferred Alternatively, the sealing auxiliary layer is subjected to a surface activation treatment. As shown in FIG. 1, the internal electrode 3 and the conductor line 4 may be integrated.
第 2図に示すように、 高周波素子 1 1は素子搭載領域 2の中央に搭載さ れ、 素子表面の電極 1 3とパッケージ内部電極 3とをボンディングワイヤ 1 2により接続し (第 3図(e)参照) 、 しかる後、 キャップ部材 8を接着剤 9 を用いて基板の封止補助層 7に接着することにより封止する (第 3図(f)に 相当する。 ) 。 なお、 これらの図では、 封止補助層 7と接着剤層 9をキヤッ プ部材の端面と等しい幅に描いてあるが、 封止補助層 7と接着剤層 9からな る封止層は、 高周波特性に影響を及ぼさない限りにおいて基板表面により大 きな広がりを有するものでもよい。  As shown in FIG. 2, the high-frequency element 11 is mounted at the center of the element mounting area 2, and the electrodes 13 on the element surface and the package internal electrodes 3 are connected by bonding wires 12 (see FIG. Thereafter, the cap member 8 is sealed by bonding the cap member 8 to the sealing auxiliary layer 7 of the substrate using an adhesive 9 (corresponding to FIG. 3 (f)). In these figures, the sealing auxiliary layer 7 and the adhesive layer 9 are drawn to have the same width as the end face of the cap member, but the sealing layer composed of the sealing auxiliary layer 7 and the adhesive layer 9 is As long as the high-frequency characteristics are not affected, the substrate may have a larger spread on the substrate surface.
上記の構造とすることにより、 電極及び導体線路が基板材料の焼成収縮に よる寸法変動の影響を受けないため、 ストリップ線路等による高水準のィン ピーダンス調整その他の機能を内蔵することが可能となり、 かつ、 高水準の 封止が実現できる。  With the above structure, the electrodes and conductor lines are not affected by dimensional fluctuations caused by shrinkage of the substrate material due to firing shrinkage, so it is possible to incorporate high-level impedance adjustment and other functions using strip lines, etc. , And a high level of sealing can be realized.
第 1〜2図に示す態様は、 本発明の最も基本的態様を示すものであり、 基 板形状及び導体線路の構造は必要に応じて変更される。 以下、 典型的な応用 例に言及しつつ、 本発明のパッケージの基本的要素である基板構造、 キヤッ プ部材及び接着層につレ ^て詳述する。  The embodiment shown in FIGS. 1 and 2 shows the most basic embodiment of the present invention, and the shape of the substrate and the structure of the conductor line are changed as necessary. Hereinafter, the substrate structure, the cap member, and the adhesive layer, which are basic elements of the package of the present invention, will be described in detail with reference to typical application examples.
(a)基板構造  (a) Substrate structure
本発明のパッケージにおける基板構造には、 焼成済み基板 (なお、 特に注 意を喚起する場合を除き、 焼成済みセラミック基板を単に 「セラミック基 板」 という。 ) とその表面に設けられた前記素子への入出力を行うための電 極、 導体線路及び Zまたは回路が含まれる。  The substrate structure in the package of the present invention includes a fired substrate (a fired ceramic substrate is simply referred to as a “ceramic substrate” unless otherwise noted) and the elements provided on the surface thereof. It includes electrodes, conductor lines, and Z or circuits for input and output of the I / O.
従来の積層セラミックパッケージも、 基板材料としてセラミックを用い、 その上に電極や導体路等 (以下、 単に 「電極」 ともいう。 ) を有する構造を 含む。 しかし、 従来の積層セラミックパッケージは、 上述の通り、 セラミツ クグリーンシート上に導体ペーストを厚膜印刷し、 グリーンシートの焼成と 同時に電極の焼成による形成を行うものであり、 焼成時にはグリーンシート の収縮が避けられないため、 ピースごとにパッケージの寄生容量が異なる。 この不均一性 (ばらつき) は積層セラミックパッケージの生産において同時 焼成される電極の収縮率に均一性が乏しく、 精度の高い電極形成が困難なこ とが主な原因である。 A conventional multilayer ceramic package also includes a structure in which ceramic is used as a substrate material and electrodes, conductor paths, and the like (hereinafter, also simply referred to as “electrodes”) are provided thereon. However, conventional multilayer ceramic packages, as described above, A thick paste of conductive paste is printed on the green sheet and the electrodes are formed by firing the green sheet simultaneously with firing.Since shrinking of the green sheet is inevitable during firing, the parasitic capacitance of the package is reduced for each piece. different. This non-uniformity (variation) is mainly due to poor uniformity in the shrinkage of the electrodes co-fired in the production of the multilayer ceramic package, making it difficult to form electrodes with high precision.
故に積層セラミックパッケージの高性能化には収縮率の均一性を高くする ことが不可欠であり、 一般には成形技術や焼成技術の改善といったセラミツ クスに固有な技術の改善によっている。 しかし、 収縮率の不均一性は 「焼成」 というセラミックスの本質的な特徴に由来しているので解決はできない。 こ れに対して、 本発明では、 グリーンシートからの積層基板形成に代えて焼成 済み基板に導体路を設けることで 「セラミックスと電極の同時焼成」 という 工程を除き、 パッケージ内部の精度の高い電極形成を実現し、 これによつて パッケージごとの寄生容量のばらつきを抑え、 さらにストリップ線路等によ るインピーダンス補正等、 パッケージ特性の改善や高性能化を実現した。 (a - 1 )基板  Therefore, it is essential to increase the uniformity of the shrinkage rate in order to improve the performance of multilayer ceramic packages. Generally, the improvement is due to the improvement of molding technology and firing technology, which are specific to ceramics. However, the non-uniformity of the shrinkage rate cannot be solved because it is derived from the inherent characteristic of ceramics called “baking”. In contrast, in the present invention, a conductor path is provided on a fired substrate instead of forming a laminated substrate from a green sheet, thereby eliminating the process of “simultaneous firing of ceramics and electrodes”. This enabled the formation of the package, thereby suppressing variations in the parasitic capacitance of each package, and further improving the package characteristics and improving the performance, such as impedance correction using a strip line. (a-1) substrate
基板材料は、 各種のセラミック材料を用いることができるが、 特に以下の 条件を満たす材料が好ましい。  As the substrate material, various ceramic materials can be used, but a material satisfying the following conditions is particularly preferable.
•搭載する素子 (ベアチップ) と線膨張係数が一致していること。  • The element (bare chip) to be mounted must have the same coefficient of linear expansion.
·実用を満足する精度の良い電極形成が安価かつ容易にできること。  · It should be possible to form electrodes with high accuracy that satisfies practical use at low cost and easily.
•高周波での有効な絶縁のために誘電損失が小さいこと (Q値が高いこと) 。 •最終検査まで集合基板状態で製造する場合 (後述) にも十分な機械的強度 を有していること。  • Low dielectric loss (high Q value) for effective insulation at high frequencies. • Sufficient mechanical strength even in the case of manufacturing in a collective board state until the final inspection (described later).
以上の条件に適合する基板材料としては、 アルミナ、 特に重量比 9 6 %の アルミナを含有する 9 6アルミナが挙げられる。 アルミナ以上の誘電率及び Q値を有する誘電体材料も用い得る。 目的によっては、 それ以下の無機誘電 体材料も使用可能である。 As a substrate material meeting the above conditions, alumina, particularly 96 alumina containing 96% by weight of alumina can be mentioned. A dielectric material having a dielectric constant and a Q value higher than that of alumina may also be used. Depending on the purpose, lower inorganic dielectric Body materials can also be used.
基板の厚みは、 基板の寸法及び必要とされる強度により選択される。 基板 寸法及び形状は搭載すべき素子の大きさにより決定される。  The thickness of the substrate is selected according to the dimensions of the substrate and the required strength. The dimensions and shape of the substrate are determined by the size of the element to be mounted.
(a-2)電極及び導体線路  (a-2) Electrode and conductor line
基板とその表面に設けられた前記素子への入出力を行うための電極及び導 体線路としては、 第 1〜 2図に示したような、 素子との接続のための内部電 極、 パッケージを表面実装するために設けられる外部電極 (側面電極を含 む) 、 及び内外電極間を接続する導体線路が含まれる。  The electrodes and the conductor lines for inputting and outputting to the substrate and the elements provided on the surface thereof include internal electrodes and packages for connection to the elements as shown in FIGS. 1 and 2. It includes external electrodes (including side electrodes) provided for surface mounting, and conductor lines connecting between the internal and external electrodes.
これらの電極及び導体線路は、 例えば、 厚膜印刷により形成できる。 ま た、 本発明では電極形成後に 「焼成」 という工程がないために、 薄膜形成に よる精度の高い電極形成その他のメタライズ方法を用いることができる。 導 体材料は慣用のものでよく、 例えば、 厚膜印刷では A g、 A g — P t、 A g — P d、 A u、 C u、 N i等の厚膜用導電ペースト、 薄膜形成では A u、 C u、 Aし N i等が等が挙げられるがこれらに限定されるものではない。 これらの手法を組み合わせてもよく、 例えば、 上述の内部電極及び/または 外部電極としては、 厚膜印刷電極上に無電解メツキ (例えば、 無電解金メッ キ) を施したものが好適に用いられる。 無電解金メッキを施すことにより、 ( 1 )ワイヤ ·ボンディング性の改善、 (2)ハンダ付け性の改善、 (3)導体抵抗 の改善という効果がある。  These electrodes and conductor lines can be formed by, for example, thick film printing. Further, in the present invention, since there is no step of “firing” after the formation of the electrode, a highly accurate electrode formation by thin film formation and other metallization methods can be used. The conductor material may be a conventional one. For example, for thick film printing, conductive paste for thick film such as Ag, Ag—Pt, Ag—Pd, Au, Cu, and Ni, and for thin film formation. Examples include, but are not limited to, Au, Cu, A and Ni, and the like. These methods may be combined. For example, as the above-mentioned internal electrode and / or external electrode, a material obtained by applying an electroless plating (for example, an electroless gold plating) on a thick-film printed electrode is preferably used. . Applying electroless gold plating has the effects of (1) improving wire bonding, (2) improving solderability, and (3) improving conductor resistance.
内部 ·外部の電極形状は従来のパッケージにおける電極形状と同様でよ い。 第 1〜 2図では、 ボンディングワイヤにより素子とパッケージとを電気 的に接続する態様を示したが、 バンプ構造等、 他の接続構造でもよく、 内部 電極はそれぞれの接続構造に応じた形状とする。 また、 第 1〜 2図では、 内 部電極-導体線路-側面電極-外部電極と接続する態様を示したが、 側面電極 に代えて充填スルーホールを用いてもよい。  The internal and external electrode shapes may be the same as those of the conventional package. 1 and 2 show the mode of electrically connecting the element and the package by bonding wires, but other connection structures such as a bump structure may be used, and the internal electrodes are shaped according to each connection structure. . In addition, FIGS. 1 and 2 show a mode of connection with the internal electrode-conductor line-side electrode-external electrode, but a filled through hole may be used instead of the side electrode.
導体線路としては、 高周波帯においては平面線路 (ストリップ線路、 マイ クロストリップ線路、 コプレーナ線路) の適用が典型的である。 As a conductor line, in the high frequency band, a flat line (strip line, Cross-trip lines, coplanar lines) are typical applications.
ストリップ線路は、 基板表面に適当な線幅の導体線路を設け、 基板裏面に グラウンド (GND) を設けることで形成できる (第 4図(a)) 。 例えば、 厚さ 0.64 mmの 96アルミナ基板上に線路幅 dが 0.641^01の八8—? t力、 らなる導体線路を設け裏全面に G N Dを設けることにより特性インピーダン スが 50 Ωのストリップ線路が形成できる。 後述のように、 この厚膜印刷ス トリップ線路の伝送特性 (S2 I) 及び反射特性 (SM) からは、 1 0 GHz でも挿入損失は電力で 4% (伝送特性 S =— 0.2 dBより換算) で反射 特性も定在波比で 1.02以下 (反射特性 Su = - 42 d Bより換算) であ り、 伝送特性は無損失かつ無反射で 10 GH z帯での適用に優れる。 A stripline can be formed by providing a conductor line with an appropriate line width on the surface of the substrate and providing ground (GND) on the backside of the substrate (Fig. 4 (a)). For example, on a 0.64 mm thick 96-alumina substrate, the line width d is 0.641 ^ 01. A strip line with a characteristic impedance of 50 Ω can be formed by providing a conductor line consisting of a t-force and GND on the entire back surface. As will be described later, from the transmission characteristics (S 2 I ) and reflection characteristics (S M ) of this thick-film printed strip line, even at 10 GHz, the insertion loss is 4% in power (from transmission characteristics S = —0.2 dB). The reflection characteristics are 1.02 or less in terms of standing wave ratio (converted from the reflection characteristics S u = -42 dB), and the transmission characteristics are lossless and non-reflective, and are excellent for application in the 10 GHz band.
厚膜印刷ストリップ線路では 1 5GHz以上で実用を満足する特性を得る ことは難しレ^ しかし、 本発明ではフォトレジスト法等により高精度の薄膜 電極パターンの形成が容易であるため、 例えばアルミナ基板上に高精度のス トリップ線路を設けることにより 1 00 GHzのミリ波帯まで高い特性を実 現することができる。 後述のように、 コプレーナ線路の利用も可能である 、 コプレーナ線路と比較して構造が単純であり、 設計が容易でノウハウの 蓄積も豊富であるストリップ線路の利用は、 ミリ波帯モジュールの低価格化 と高性能化を両立させるという点で有利である。  It is difficult to obtain practically satisfactory characteristics at 15 GHz or higher with thick-film printed striplines. However, in the present invention, it is easy to form a high-precision thin-film electrode pattern by a photoresist method or the like. By providing a high-precision strip line in this system, it is possible to realize high characteristics up to the millimeter wave band of 100 GHz. As described later, the use of coplanar lines is also possible.The use of strip lines, which have a simpler structure than coplanar lines, are easy to design, and have a wealth of know-how, are available at low cost for millimeter-wave band modules. This is advantageous in achieving both high performance and high performance.
第 4図(b)にはコプレーナ型導波線路の構造を示した。 これは第 4図(a)の 伝送線路の両側に導体層を設けたものである。 図では、 両側の導体層を裏面 の GND層とスル一ホールを介して結合した構造を示したが、 裏面に GND層を有 しない構造、 あるいは、 スルーホールを除いた GND付きコプレーナ線路構造 でもよい。 コプレーナ導波線路は設計が難しいという問題があるが、 1 0G Hz以上で適当であり、 1 00 GHz以上の周波数まで実用を満足する特性 が得られる。  Fig. 4 (b) shows the structure of a coplanar waveguide. This is one in which conductor layers are provided on both sides of the transmission line in Fig. 4 (a). Although the figure shows a structure in which the conductor layers on both sides are connected to the GND layer on the back via a through hole, a structure without a GND layer on the back or a coplanar line structure with GND excluding through holes may be used. . Although the coplanar waveguide has a problem that it is difficult to design, it is suitable at 10 GHz or more, and a characteristic satisfying practical use is obtained up to a frequency of 100 GHz or more.
本発明では、 導体配線の幅や間隔を精密に制御することが可能であるた め、 以下に示すように導体線路による特性改善やパッケージ機能の高度化が 実現できる。 According to the present invention, it is possible to precisely control the width and interval of the conductor wiring. Therefore, as shown below, it is possible to achieve improved characteristics and advanced package functions using conductor lines.
(a-3)インピーダンス調整用線路  (a-3) Impedance adjustment line
例えば、 第 5図には、 マイクロ Xと呼ばれる 1 0 G H z以上で適用される 超高周波用セラミックパッケージ 2 0の従来構造の平面図を模式的に示し た。 中心に搭載される素子 2 1は電子の移動度の高い GaAsFETのベアチップ である。 第 5図では単純化して示してあるが、 ベアチップを搭載する基板 2 2は、 第 1 0図等と同様の多層積層基板である。  For example, FIG. 5 schematically shows a plan view of a conventional structure of an ultra-high frequency ceramic package 20 applied at 10 GHz or more called Micro X. The element 21 mounted in the center is a GaAs FET bare chip with high electron mobility. Although simplified in FIG. 5, the substrate 22 on which the bare chip is mounted is a multilayer laminated substrate similar to that of FIG. 10 and the like.
マイクロ Xでは、 ゲート、 ドレイン及びソースの各端子と接続する導体線 路。、 D、 Sを互いに直交させて配置することにより寄生容量を抑圧してい る。 これらの導体線路は、 基板内においては内層配線であり、 チップ搭載基 板外において別個に形成されたストリップ線路に接続されるのが一般的であ る (図では基板内外で一体のものとして示してある。 ) 。 しかし、 端子を互 いに直交させてマイク口 X構造としても寄生容量 Cはなくならない。 また、 GaAsFETの各電極と導体線路間を接続するボンディングワイヤ 2 3によるィ ンダク夕ンス Lの発生もある。  In Micro X, a conductor line that connects to the gate, drain, and source terminals. , D, and S are arranged perpendicular to each other to suppress the parasitic capacitance. These conductor lines are inner layer wiring inside the substrate and are generally connected to strip lines formed separately outside the chip mounting substrate (in the figure, they are shown as one integrated inside and outside the substrate). There is.) However, the parasitic capacitance C does not disappear even if the terminals are orthogonal to each other to form the microphone opening X structure. In addition, there is an occurrence of inductance L due to the bonding wire 23 connecting each electrode of the GaAsFET and the conductor line.
積層パッケージ技術では焼成時の収縮率がパッケージ毎に均一でないため に寄生容量 Cの均一性は乏しい。 ボンディング精度は高いのでワイヤ ·ボン デイング自体は、 通常、 高い均一性をもって形成できるが、 従来の積層基板 構造では内層配線の焼成収縮による寸法変化が避けられず、 これに起因した 内層配線インダク夕 Lの不均一性 (バラツキ) も問題となる。 1 0 G H z以 上になると C及び Lによるインピーダンスの周波数変化は大きくなり、 半導 体チップには適切な信号波電流が印加されない周波数帯が生じるようにな る。 マイクロ Xでは、 チップ搭載用基板に別個に形成された (マイクロ) ス トリップ線路に接続することによりかかる問題を低減しているが、 この結 果、 素子上の電極とこれら導体線路との接続構造は複雑になる傾向がある。 これに対し、 本発明では、 「セラミックス及び配線用電極の同時焼成」 と いう工程がないため、 寄生容量 Cは各パッケージで均一となるばかりでな く、 精度の高いストリップ線路 (またはコプレーナ型導波線路) をインピー ダンスの補正用としてパッケージに内蔵することができる。 その例を第 6〜 7図に示す。 これらは、 基板上に導体線路を設けたものであり、 ボンディン グワイヤのィンダク夕ンス L及び寄生容量 Cを高い精度で補正できる。 ま た、 特に基板材料として高誘電率材料を用いることで従来型マイクロ より も導体線路長を短縮することが可能であり、 高性能半導体素子の性能を限界 まで引出すとともに、 その実質寸法を大きく低減することができるのである (この構成例については実施例 2において詳述する。 ) 。 In the multilayer package technology, the uniformity of the parasitic capacitance C is poor because the shrinkage rate during firing is not uniform for each package. Since the bonding accuracy is high, the wire bonding itself can usually be formed with high uniformity.However, in the conventional laminated substrate structure, dimensional changes due to shrinkage of the inner wiring due to firing shrinkage are unavoidable. Non-uniformity (variation) also becomes a problem. When the frequency is 10 GHz or more, the frequency change of impedance due to C and L increases, and a frequency band in which an appropriate signal wave current is not applied to the semiconductor chip occurs. In Micro X, this problem is reduced by connecting to (micro) strip lines separately formed on the chip mounting substrate. As a result, the connection structure between the electrodes on the element and these conductor lines is reduced. Tend to be complicated. On the other hand, in the present invention, since there is no step of “simultaneous firing of ceramics and wiring electrodes”, the parasitic capacitance C is not only uniform in each package, but also a highly accurate stripline (or coplanar type conductor). Wave line) can be built into the package for impedance correction. Examples are shown in Figs. These have conductor lines provided on the substrate, and can correct the inductance L and the parasitic capacitance C of the bonding wire with high accuracy. In addition, by using a high dielectric constant material as the substrate material, it is possible to shorten the conductor line length compared to conventional micros, and to bring out the performance of high-performance semiconductor devices to the limit and to substantially reduce their substantial dimensions. (An example of this configuration will be described in detail in Example 2.)
(a - 4)付加回路 (a-4) Additional circuit
また、 本発明では、 導体配線の幅や間隔を精密に制御することが可能であ るため、 基板上に高精度の平面ィンダク夕を併せて設けることが可能であ る。 従って、 このような平面インダク夕及び Zまたは高精度で入手可能なチ ップキャパシ夕等のキャパシ夕要素と基板上で組み合わせることで、 種々の 機能を有する回路を表面に設けることができる。 このような回路の一例とし て、 平衡ー不平衡変換回路が挙げられる。  Further, according to the present invention, since the width and interval of the conductor wiring can be precisely controlled, it is possible to additionally provide a high-precision planar inductor on the substrate. Therefore, circuits having various functions can be provided on the surface by combining such a planar inductor and a capacitance element such as Z or a chip capacitance available at high precision on a substrate. An example of such a circuit is a balanced-unbalanced conversion circuit.
一般に、 2つの高周波線路またはデバイスを接続する場合には、 その接続 点でのインピーダンスが等しくなるように整合させる必要があるが、 電磁界 の分布も同一でなければならない。 このため、 GNDから高周波的に絶縁され た端子 (平衡型入出力構成) と GNDに接地した端子 (不平衡型入出力構成) の接続には平衡ー不平衡変換素子 (バラン) が必要である。  Generally, when two high-frequency lines or devices are connected, they must be matched so that the impedance at the connection point is equal, but the distribution of the electromagnetic field must also be the same. For this reason, a balanced-unbalanced conversion element (balun) is required to connect a terminal (balanced input / output configuration) that is insulated from GND in high frequency and a terminal grounded to GND (unbalanced input / output configuration). .
現在、 低電圧で駆動し広いダイナミックレンジと高いゲインとを実現する 平衡型の電力増幅器、 低雑音増幅器 (LNA=Low Noi se Amp) 及び混合器が実 用化されつつある。 高周波回路の平衡化により、 電源スィッチ卜ランジス 夕、 負電圧発生用 DC/DCコンパ一夕等の MMICが不要となり移動体通信用高周 波回路の大幅な小型化と低価格化が可能となる。 しかし、 アンテナ(ANT)か らアンテナスィツチ(ANT- SW)を経て低雑音増幅器(LNA:)、 更に SAWフィル夕へ と続く携帯電話機受信部の構成例において、 LNAが平衡化されると後段の SAW フィル夕を平衡型に改めるか、 LNAと SAWフィル夕との間には平衡変換器が必 要となる。 ところが、 SAWフィルタを平衡型に改めることは容易でない。 バランは、 第 8図の等価回路に示すようにインダク夕とキャパシ夕の組み 合わせで構成可能であり、 本発明において、 第 9図に示す回路を基板上に設 けることにより平衡変換器内蔵型パッケージとすることができる (この構成 例については実施例 3において詳述する。 ) 。 本発明ではアルミナ基板のよ うな焼成済み基板上にインダク夕を形成するため、 精度の高いインダク夕電 極が形成可能であり、 例えば、 本発明者らによる特願平 1卜 7637号および 特願平 10- 182045号に記載のインダク夕が利用できる。 また、 Q値が高く小 型で大容量のチップキャパシ夕を用いることにより高性能の回路を構成でき る。 必要に応じ、 導体線路により特性インピーダンスを調整してもよい。 Currently, balanced power amplifiers, low-noise amplifiers (LNAs), and mixers that are driven by low voltages to achieve a wide dynamic range and high gain are being commercialized. Equilibration of the high-frequency circuit eliminates the need for MMICs such as power switch transistors and DC / DC converters for negative voltage generation, and eliminates the need for MMICs for mobile communications. The wave circuit can be significantly reduced in size and cost. However, when the LNA is balanced in the example of the configuration of the mobile phone receiver from the antenna (ANT) to the low noise amplifier (LNA :) via the antenna switch (ANT-SW) and then to the SAW filter, the subsequent stage Either upgrade the SAW filter to a balanced type, or use a balanced converter between the LNA and the SAW filter. However, it is not easy to change the SAW filter to a balanced type. The balun can be composed of a combination of an inductor and a capacitor, as shown in the equivalent circuit of FIG. 8, and in the present invention, by mounting the circuit shown in FIG. A package can be used (an example of this configuration will be described in detail in Embodiment 3). In the present invention, an inductor electrode is formed on a fired substrate such as an alumina substrate, so that a highly accurate inductor electrode can be formed. For example, Japanese Patent Application Nos. Indak evening described in Hei 10-182045 can be used. In addition, a high-performance circuit can be constructed by using a small, large-capacity chip capacitor with a high Q value. If necessary, the characteristic impedance may be adjusted using conductor lines.
(a- 5)複合モジュールパッケージ  (a-5) Composite module package
(a - 4)の説明により理解されるように、 本発明は、 気密封止を要する高周 波部品を有する回路全般について適用することができる。 例えば、 GaAsFET や SAWフィル夕あるいは MMICを 1つ以上含む高周波回路において、 これらの高 周波素子の各々若しくはそれらの 2以上または回路全体を上記に従って封止す ることが可能である (この構成例については実施例 5において詳述する。 ) 。 (b)キャップ部材  As understood from the description of (a-4), the present invention can be applied to all circuits having high-frequency components that require hermetic sealing. For example, in a high-frequency circuit including one or more GaAs FETs, SAW filters, or MMICs, it is possible to seal each of these high-frequency elements, two or more of them, or the entire circuit as described above. Is described in detail in Example 5.) (b) Cap member
蓋体として機能するキャップ部材は、 前記基板の表面に密着させたときに 前記素子を収容するのに十分な寸法の空間を形成する形状及び高さを有する ものであればよい。 また、 保護部材として十分な強度を有すればよい。 無機材料製、 有機材料製、 金属製のキャップが封止用として適用できる。 無機材料製としてはアルミナ、 石英ガラス等、 有機材料製としてはプラスチ ック、 エポキシ等、 金属製としてはヨウハク (洋白) 、 リン青銅、 銅等が挙 げられる。 The cap member functioning as a lid may have any shape and height so as to form a space having a size sufficient to accommodate the element when brought into close contact with the surface of the substrate. Also, it is sufficient if the protective member has sufficient strength. Caps made of inorganic material, organic material, and metal can be used for sealing. Alumina, quartz glass, etc. made of inorganic material, plastic made of organic material Metals such as paints, epoxies, and the like include iohaku (Western white), phosphor bronze, and copper.
金属製キャップを適用すれば、 高周波素子は良導性物質で囲まれることに なり、 キヤップを GNDに接地することでほぼ完全なシ一ルド効果が得られ る。 また、 接地しなくても高いシールド効果がある。  If a metal cap is used, the high-frequency device will be surrounded by a conductive material, and almost perfect shielding can be obtained by grounding the cap to GND. Also, there is a high shielding effect without grounding.
金属キャップを用いる場合、 基板表面の導体路との絶縁が必要である。 金 属製キャップと導体線路間の絶縁は、 キャップと導体線路との間に絶縁層を 厚膜印刷等で設ければよいが、 本発明では封止補助層が絶縁層としても機能 する。  If a metal cap is used, it must be insulated from the conductor tracks on the substrate surface. Insulation between the metal cap and the conductor line can be achieved by providing an insulating layer between the cap and the conductor line by thick-film printing or the like. In the present invention, the sealing auxiliary layer also functions as an insulation layer.
(c)接着封止 (c) Adhesive sealing
本発明においては、 上述の基板構造を採ることとともに、 高周波用素子を 搭載するための領域を有するセラミック基板上に封止補助層の硬化体または 無機材料層である封止補助層を設け、 キャップ部材を接着剤によりこの封止 補助層に接着して封止をなすことが大きな特徴である。  In the present invention, in addition to adopting the above-described substrate structure, a sealing auxiliary layer which is a cured body of the sealing auxiliary layer or an inorganic material layer is provided on a ceramic substrate having a region for mounting a high-frequency element, and a cap A major feature is that the member is bonded to the sealing auxiliary layer with an adhesive to perform sealing.
接着剤を用いることにより、 ハンダゃガラスフリットにより封止を行う場 合に必要とされた数百 °Cの加熱処理が不要となる。 また、 接着に先立ち封止 補助層を表面活性化することにより、 素子モジュールを実装した後の熱膨張 の反復等にも耐え得る高信頼性の接着封止が実現できる。  The use of an adhesive eliminates the need for a heat treatment at several hundred degrees Celsius, which is required when sealing with solder-glass frit. Also, by activating the surface of the sealing auxiliary layer prior to bonding, highly reliable bonding and sealing that can withstand repeated thermal expansion after mounting the element module can be realized.
なお、 従来においても、 例えば、 水晶振動子等では、 振動子基板上に直接 キャップ状の封止材を接合する封止方法が採られている。 しかし、 水晶振動 子等では実装使用時における発熱は少なく、 接着界面がパッケージの熱膨張 の反復により劣化する可能性は少ない上、 耐湿性の要求も低く使用帯域も数 十 MH z以下である。 一方、 高周波あるいは超高周波帯域において使用され 発熱量も多く、 なおかつ要求される耐湿性等の水準も高い SAWフィル夕、 GaA sFET、 MMIC電力増幅器等の封止には、 本発明による上記封止方法を採る必要 がある。 封止補助層は、 前記キャップ部材の端面と適合する形状に基板上に形成す る。 具体的には、 基板上におけるキャップ部材との接合部を含む領域に、 高 分子樹脂を印刷し硬化するか、 あるいは、 厚膜印刷その他の方法によって無 機材料層を形成し焼成して封止補助層とする。 Heretofore, for example, in the case of a quartz oscillator or the like, a sealing method in which a cap-shaped sealing material is directly joined to the oscillator substrate has been adopted. However, in the case of crystal oscillators and the like, heat generation during mounting and use is small, and there is little possibility that the bonding interface will be degraded due to repeated thermal expansion of the package. On the other hand, the sealing method according to the present invention is used for sealing SAW filters, GaAs FETs, MMIC power amplifiers, etc., which are used in a high frequency or ultra-high frequency band, generate a large amount of heat, and have a high level of required moisture resistance. Must be adopted. The sealing auxiliary layer is formed on the substrate in a shape compatible with the end surface of the cap member. Specifically, a polymer resin is printed and cured in the area including the joint with the cap member on the substrate, or an inorganic material layer is formed by thick-film printing or other methods and then fired and sealed. An auxiliary layer.
本発明において封止補助層として利用可能な有機高分子材料としては、 耐 熱性、 耐湿性及び絶縁性の性質を有する、 例えば、 エポキシ系、 フエノール 系及びェポキシフエノール系等の樹脂を主成分とした樹脂材料が好ましく、 これらの材料にスクリーン印刷等の塗工性を付与するために硬化剤、 レペリ ング剤、 消泡剤、 無機充填剤等を分散させたものを用いる。 レべリング剤あ るいは消泡剤の例としてはシリコーンオイルを主成分としたものが挙げられ る。 但し、 シリコーン系レべリング剤あるいは消泡剤を使用する場合には、 キヤップ接着に対してマイナスとなる濡れ性の悪化を抑制するためにその添 加量を 0 . 0 1〜2 . O w t %程度として使用することが好ましい。 また、 レ ベリング剤についてはエポキシ変性を行うことが好ましい。 無機充填剤は、 エポキシ接着の際の投錨効果も考慮して添加することが好ましいが、 その場 合は、 平均粒径としてスクリーン印刷に適した 0 . 5〜 1 0 m程度のもの を使用することが好ましい。  The organic polymer material that can be used as the sealing auxiliary layer in the present invention includes, as a main component, a resin having heat resistance, moisture resistance, and insulation properties, such as an epoxy resin, a phenol resin, and an epoxy phenol resin. It is preferable to use resin materials in which a curing agent, a reppelling agent, an antifoaming agent, an inorganic filler, and the like are dispersed in order to impart coatability such as screen printing to these materials. Examples of the leveling agent or the defoaming agent include those containing silicone oil as a main component. However, when a silicone-based leveling agent or antifoaming agent is used, the amount added should be 0.01 to 2.0 wt. % Is preferably used. It is preferable that the leveling agent is modified with epoxy. It is preferable to add the inorganic filler in consideration of the anchoring effect at the time of epoxy bonding, but in this case, use a filler with an average particle size of about 0.5 to 10 m suitable for screen printing. Is preferred.
封止補助層は、 スクリーン印刷等の慣用の方法により基板上に印刷する 力 基板表面の配線等と交差する場合には、 基板表面の導体路による凹凸を 吸収し、 また、 キャップ部材が金属である場合に基板上の配線導体との絶縁 を確保するために、 電極または導体線路の表面を覆うように、 すなわち、 こ れらの導体路の厚みよりも高く、 かつ、 樹脂層表面が全体として均等な高さ となるようにする必要がある。 これは上述の添加物等により適切な粘度に調 整して実現できる。 通常は、 厚み 1 0〜5 0 程度の層とすればよい (後 述の無機材料の場合も同様) 。  When the sealing auxiliary layer intersects with the wiring or the like on the substrate surface, which is printed on the substrate by a common method such as screen printing, the sealing auxiliary layer absorbs irregularities due to the conductive path on the substrate surface, and the cap member is made of metal. In some cases, in order to ensure insulation from the wiring conductors on the board, cover the surfaces of the electrodes or conductor lines, that is, make them thicker than these conductor paths, and make the resin layer surface as a whole. The height must be even. This can be realized by adjusting the viscosity to an appropriate value with the above-mentioned additives and the like. Usually, a layer having a thickness of about 10 to 50 may be used (the same applies to the case of an inorganic material described later).
印刷後、 有機高分子層を硬化させ、 封止補助層とする。 本発明において封止補助層として利用可能な無機材料は特に限定されず、 種々の無機ガラス、 酸化物等が利用できる。 中でも結晶化シリカガラスが好 ましい。 After printing, the organic polymer layer is cured to form a sealing auxiliary layer. In the present invention, the inorganic material that can be used as the sealing auxiliary layer is not particularly limited, and various inorganic glasses and oxides can be used. Among them, crystallized silica glass is preferred.
結晶化シリカガラスとしては、 S i 02— M g〇一 Z n O— A l 23系、 P b O— Z n〇一 B 23— S i 02等が挙げられるが、 以下の説明から理解 されるように、 これ以外の系でも焼結時に微結晶を析出し鉛を含まないガラ スであればよい。 結晶化シリカガラスでは数 m程度のピンホールが発生す ることがあるが、 1 0〜2 0 m程度の膜厚とすれば問題は生じない。 The crystallized silica glass, S i 0 2 - M G_〇 one Z n O- A l 23 system, P b O-Z N_〇 one B 23 - S i 0 2, and the like, As will be understood from the following description, glass other than this may be a glass that precipitates microcrystals during sintering and does not contain lead. Crystallized silica glass may have pinholes of about several meters, but no problem occurs if the thickness is about 10 to 20 m.
結晶化シリカガラスを用いることにより、 素子のパッケージング性能 (耐 湿性等) が改善できる理由の詳細は不明であるが、 一つには、 焼結の際、 表 面に微結晶粒を析出するため、 表面粗度が大きくなり接着剤の投錨効果が高 まることが考えられる。  The reason why the packaging performance (moisture resistance, etc.) of the device can be improved by using crystallized silica glass is unknown, but one of the reasons is that microcrystal grains precipitate on the surface during sintering. Therefore, it is conceivable that the surface roughness increases and the anchoring effect of the adhesive increases.
また、 内部電極と外部電極とを接続する配線導体が基板表面に形成される 場合、 あるいは、 キャップ部材が金属で基板上の配線導体との絶縁を確保す る必要がある場合、 封止補助層は配線導体の一部と重なることになるが、 無 電解メッキで形成されたメッキ層、 特に A uメッキ層表面は化学的に不活性 であり、 導体層一封止補助層間の接着性が低下する。 従って、 メツキ前に封 止補助層を形成する必要がある。 しかし、 ガラス成分が鉛を含む場合、 この A uメツキ時に鉛成分がメツキ液中に溶出し、 触媒毒となる。 結晶化シリカ ガラスでは、 このような事態が生じないため、 A uメツキが円滑に進行して 特性の改善に寄与していると考えられる。  If the wiring conductor connecting the internal electrode and the external electrode is formed on the surface of the substrate, or if the cap member needs to be made of metal to ensure insulation from the wiring conductor on the substrate, the sealing auxiliary layer Will overlap with part of the wiring conductor, but the plating layer formed by electroless plating, especially the Au plating layer surface, is chemically inert, and the adhesion between the conductor layer and the sealing auxiliary layer is reduced. I do. Therefore, it is necessary to form a sealing auxiliary layer before plating. However, when the glass component contains lead, the lead component elutes into the plating solution during the Au plating, and becomes a catalyst poison. In crystallized silica glass, such a situation does not occur, and it is considered that Au plating progresses smoothly and contributes to the improvement of characteristics.
好ましくは、 封止補助層に表面活性化処理を施した後、 上記キャップ部材 との接着を行う。 封止補助層に表面活性化処理は、 接着剤との親和性を高め るための各種の化学的または物理的な処理が含まれる。 中でも、 紫外線処理 及びプラズマ処理が好適である。  Preferably, after performing the surface activation treatment on the sealing auxiliary layer, the sealing auxiliary layer is bonded to the cap member. The surface activation treatment of the sealing auxiliary layer includes various chemical or physical treatments for increasing the affinity with the adhesive. Among them, ultraviolet treatment and plasma treatment are preferred.
紫外線処理は、 封止補助層表面に紫外線を照射して行う。 紫外線照射によ り封止補助層の接着剤に対する化学的親和性が増し、 高度な気密封止が実現 できる。 照射するエネルギーは封止補助層の種類等によるが、 高分子樹脂材 料の場合、 通常は 4 0 0〜 1 6 0 0 m Jの範囲内でよい。 一般に 1 6 0 O m J を超えると接着強度が却って低下する。 また、 導体厚膜の酸化が進行しやす くなる。 一方、 4 0 O m J以下では顕著な効果は得られない。 通常は 4 0 0 〜 1 0 0 O m Jの範囲が好ましい。 照射紫外線の波長は、 高分子樹脂硬化層 中に活性点を形成する波長域を含むように選択する。 無機材料層の場合は、 基板表面の導体層等に悪影響を及ぼさない程度であれば、 エネルギー照射量 はより大きい方が好ましい。 The ultraviolet treatment is performed by irradiating the surface of the sealing auxiliary layer with ultraviolet light. UV irradiation The chemical affinity of the sealing auxiliary layer for the adhesive increases, and a high degree of hermetic sealing can be realized. Irradiation energy depends on the type of the sealing auxiliary layer and the like, but in the case of a polymer resin material, it may be generally within a range of 400 to 160 mJ. In general, if it exceeds 160 OmJ, the adhesive strength is rather lowered. In addition, the oxidation of the conductor thick film proceeds easily. On the other hand, a remarkable effect is not obtained below 40 OmJ. Usually, the range of 400 to 100 OmJ is preferable. The wavelength of the irradiation ultraviolet rays is selected so as to include a wavelength range in which active points are formed in the cured polymer resin layer. In the case of an inorganic material layer, it is preferable that the energy irradiation amount is larger as long as it does not adversely affect the conductor layer and the like on the substrate surface.
このような紫外線照射は例えば低圧水銀灯を用いて行うことができる。 本発明における封止補助層の表面活性化処理としては、 プラズマ処理も好 ましい。  Such ultraviolet irradiation can be performed using, for example, a low-pressure mercury lamp. Plasma treatment is also preferable as the surface activation treatment of the sealing auxiliary layer in the present invention.
プラズマ処理は、 減圧したガスを満たした電極間に高周波の交流電圧を印 加し電極間にグロ一放電を発生させた状態で、 前記ガス成分のプラズマを基 板に接触させることにより行う。 プラズマ処理によって、 汚染層が除去され るとともに、 表面の粗面化及び Zまたは化学的な活性点の形成が進行する。 具体的には、 上述の封止補助層を形成した基板を減圧可能なプラズマ処理 装置内に配置し、 装置内の雰囲気を、 適宜、 プラズマ処理用のガスで置換し た後、 減圧し電圧を印加して行う。 プラズマ処理に用いるガスは、 非酸化性 のものであれば特に限定されない。 このようなガスの例としては、 ヘリウム、 ネオン、 アルゴン等の不活性ガス、 窒素等が挙げられる。 アルゴンが好まし レ^ 処理ガスの圧力は l mTorr〜 1 O Torr、 好ましくは 1 O mTorr〜: L Torr、 より好ましくは 1 0 0〜 3 0 0 mTorr程度である。  The plasma treatment is performed by applying a high-frequency AC voltage between electrodes filled with decompressed gas to generate a glow discharge between the electrodes and bringing the plasma of the gas component into contact with the substrate. The plasma treatment removes the contaminant layer and promotes surface roughening and formation of Z or chemically active sites. Specifically, the substrate on which the above-mentioned sealing auxiliary layer is formed is placed in a plasma processing apparatus capable of reducing pressure, and the atmosphere in the apparatus is appropriately replaced with a plasma processing gas. Perform by applying. The gas used for the plasma treatment is not particularly limited as long as it is non-oxidizing gas. Examples of such a gas include an inert gas such as helium, neon, and argon, and nitrogen. Argon is preferred. The pressure of the processing gas is 1 mTorr to 1 O Torr, preferably 1 O mTorr to: L Torr, and more preferably about 100 to 300 mTorr.
高周波電源は 1〜 1 0 0 MH zの範囲の周波数で、 1 0〜 3 0 0 W程度の ものであればよい。 封止補助層が高分子材料である場合には 5 0〜2 0 0 W 程度が、 無機材料である場合には 2 0 0〜3 0 0 W程度が好ましい。 処理時間は、 封止補助層の種類にもよるが、 通常は、 1 0〜3 0 0秒の範 囲である。 無機材料を用いた場合は 3〜 5分が好ましい。 処理時間が短すぎ ると処理の効果が十分に現れない。 処理時間が長すぎると、 基板表面の電極 や導体層にもプラズマによるエツチング作用が及ぶので好ましくない。 The high-frequency power supply may have a frequency in the range of 1 to 100 MHz and a power of about 10 to 300 W. When the sealing auxiliary layer is a polymer material, it is preferably about 50 to 200 W, and when it is an inorganic material, it is preferably about 200 to 300 W. The processing time depends on the type of the sealing auxiliary layer, but is usually in the range of 10 to 300 seconds. When an inorganic material is used, 3 to 5 minutes is preferable. If the processing time is too short, the effect of the processing will not be sufficiently exhibited. If the treatment time is too long, the etching effect of the plasma is exerted on the electrode and the conductor layer on the substrate surface, which is not preferable.
接着剤としては、 上記硬化面に対して良好な接着性を有し気密封止性に優 れたものであれば限定されない。 このような接着剤の例としては、 エポキシ 系接着剤、 エポキシ 'フエノール系接着剤等が挙げられる。 The adhesive is not limited as long as it has good adhesiveness to the above-mentioned cured surface and excellent airtightness. Examples of such an adhesive include an epoxy-based adhesive and an epoxy-phenol-based adhesive.
in まチ パッゲージの  in Mac
本発明の高周波素子は第 3図に概略を示す方法により製造することができ る。  The high-frequency device of the present invention can be manufactured by a method schematically shown in FIG.
各工程における具体的操作等は上記に説明した通りである。  Specific operations and the like in each step are as described above.
また、 本発明においては、 さらに、 集合基板を用いた製造方法が提供され る。 すなわち、 セラミック基板上にスルーホールを含む分割線を縦横に設け ることによってパッケージ用基板領域を複数形成する工程;前記スルーホー ルを通って基板表裏面を導通する導体路を形成する工程;各基板領域におい て素子を搭載する側の面に素子搭載用の内部電極及び内部電極と前記スルー ホール内導体路とを接続する導体線路を形成する工程;各基板領域において 素子を搭載する面とは反対側の面に前記スルーホール内導体路と電気的に接 続する外部電極を形成する工程;各基板領域において基板表面に密着させた ときに素子を収容するのに十分な大きさの空間を形成する形状及び高さを有 するキャップ部材を形成する工程;各基板領域において、 少なくとも前記内 部電極と基板領域縁部との間において前記キャップ部材の端面と適合する形 状に、 有機高分子材料層を印刷し硬化するか、 無機材料層を設ける工程;並 びに、 前記基板を前記分割線に沿って分割する工程を含む。  Further, the present invention further provides a manufacturing method using a collective substrate. A step of forming a plurality of package substrate regions by providing vertical and horizontal dividing lines including a through hole on a ceramic substrate; a step of forming a conductor path for conducting the front and back surfaces of the substrate through the through hole; Forming an internal electrode for mounting the element and a conductor line connecting the internal electrode and the conductor path in the through-hole on the surface on the side where the element is mounted in the region; opposite to the surface on which the element is mounted in each substrate region Forming external electrodes electrically connected to the conductor paths in the through-holes on the side surface; forming a space large enough to accommodate the element when closely contacting the substrate surface in each substrate region Forming a cap member having a desired shape and height; in each substrate region, at least between the internal electrode and the edge of the substrate region; A compatible shape with the end face, or cured printing the organic polymer material layer, which comprises steps of providing an inorganic material layer; in parallel beauty, comprising the step of dividing along the substrate to the dividing line.
これは、 簡単に言えば、 1枚の基板上に多数のパッケージ基板領域を形成 し、 この集合基板から個別の基板ピースを切り出すものである。 その概要を 第 1 1〜 1 2図に模式的に示す。 In short, this is to form a number of package substrate areas on a single substrate and cut out individual substrate pieces from this collective substrate. An overview This is schematically shown in FIGS.
これらの図面に示す態様では、 無機絶縁体基板 7 1の所定の位置に穿孔 ( スルーホール) 7 2を形成する (第 1 1図(a) ) 。 スルーホールの形成は任 意の方法で可能である。 例えば、 レーザ一ビームによる穿孔、 ドリルによる 穿孔等が挙げられる。 セラミックグリーンシートにパンチングした後に焼成 してもよい。  In the embodiments shown in these drawings, perforations (through holes) 72 are formed at predetermined positions of the inorganic insulator substrate 71 (FIG. 11 (a)). The formation of through-holes is possible in any way. For example, drilling with a single laser beam, drilling with a drill, and the like can be given. It may be fired after punching on a ceramic green sheet.
次いで、 スルーホール 7 2内に導体を印刷、 充填及び Zまたはメツキし、 基板表面に電極及び導体線路 7 3を、 基板裏面 (図示していない。 ) に電極 端子を形成する (第 1 1図(b) ) 。 電極等の形成は個別基板を用いる場合と 同様である。 また、 例えば、 コプレーナ線路を用いる場合は側方の導体層 を、 分布定数型とする場合は裏面の GND層を、 あるいは、 付加回路を搭載す る場合はィンダクタパターンを併せて形成してもよい。  Then, a conductor is printed, filled and Z or plated in the through hole 72 to form electrodes and conductor lines 73 on the surface of the substrate and electrode terminals on the back surface (not shown) of the substrate (FIG. 11). (B)). The formation of the electrodes and the like is similar to the case where the individual substrate is used. Also, for example, when a coplanar line is used, the side conductor layer is formed, when a distributed constant type is used, a GND layer on the back side is formed, or when an additional circuit is mounted, an inductor pattern is also formed. Good.
電極等を形成した後、 個別基板の場合と同様に封止補助層 7 4を形成し ( 第 1 2図(a) ) 、 表面活性化処理する (第 1 2図(b) ) 。  After forming the electrodes and the like, a sealing auxiliary layer 74 is formed as in the case of the individual substrate (FIG. 12 (a)), and the surface is activated (FIG. 12 (b)).
しかる後、 基板表面パッケージングされた個々のモジュールに分離する。 個別チップへの分離は、 例えば、 ソーイング等の慣用の方法により行なうこ とができるが、 基板に分割線を浅く形成しておき、 樹脂封止後に当該分割線 に沿って変形力を加えることによって基板を分割してもよい。 スルーホール に沿って分割する方法が好ましく、 これにより分割されたスルーホールを裏 面への導通部または側面電極として用いることが可能となる。  Thereafter, the module is separated into individual modules packaged on the substrate surface. Separation into individual chips can be performed, for example, by a conventional method such as sawing, but by forming a shallow dividing line on the substrate and applying a deformation force along the dividing line after resin sealing. The substrate may be divided. It is preferable to divide the through hole along the through hole, and the divided through hole can be used as a conductive portion to the back surface or a side electrode.
なお、 上記の説明において、 スルーホールを設けないで集合基板とするこ と、 工程の順番を前後すること、 各工程における操作を慣用の同等の操作に 置き換えること等の様々な修正や変更も本発明の範囲に含まれる。  In the above description, various modifications and changes, such as using a collective substrate without through holes, rearranging the order of the steps, and replacing operations in each step with conventional equivalent operations, are also described in the present description. Included in the scope of the invention.
本発明の製造方法では、 さらに、 集合基板として形成した後、 個別ピース への分割前に検査することにより、 パッケージの製造プロセス全体をさらに 効率化する方法が提供される (この方法については次節のパッケージング方 法の説明において詳述する。 ) 。 The manufacturing method of the present invention further provides a method for further improving the efficiency of the entire package manufacturing process by inspecting the semiconductor device after being formed as a collective substrate and before dividing it into individual pieces (this method is described in the next section). Packaging method This will be described in detail in the description of the method. ).
高周波素子用のパッケ一ジング方法 Packaging method for high frequency devices
本発明による高周波素子用のパッケージング方法は、 上述のパッケージを 用いて実現することができる。  A packaging method for a high-frequency device according to the present invention can be realized using the above-described package.
すなわち、 第 3図に概略を示すように、 封止補助層を有するセラミック基 板上に電子部品を実装し、 これをキャップ部材を接着して封止する。 パッケ ージ構造については上述した通りである。  That is, as schematically shown in FIG. 3, an electronic component is mounted on a ceramic substrate having a sealing auxiliary layer, and the electronic component is sealed by bonding a cap member. The package structure is as described above.
実装方法としては導電性ペーストによる樹脂接着あるいはロウ付け等によ る接合方法が挙げられる。 接合後、 例えば、 代替フロン (H C F C :ハイド 口クロ口フロロ力一ボン) を用いるフラックス洗浄を行い、 さらにワイヤボ ンディング等により電子部品と厚膜基板の電気的接合を施す。 ボンディング ワイヤによるインダク夕ンスを考慮してワイヤ長は極力短く、 ワイヤ太さは 大きくすることが好ましい。 通常は直径 1 0〜 5 0 ; m、 好ましくは 1 5〜 3 0 / mの金線が用いられる。  Examples of the mounting method include a resin bonding method using a conductive paste or a bonding method using brazing or the like. After bonding, for example, flux cleaning is performed using an alternative chlorofluorocarbon (HFCFC), and electrical bonding between the electronic component and the thick film substrate is performed by wire bonding or the like. In consideration of the inductance caused by the bonding wire, it is preferable that the wire length is as short as possible and the wire thickness is large. Usually, a gold wire having a diameter of 10 to 50; m, preferably 15 to 30 / m is used.
封止処理操作時の環境条件 (特に湿度) は重要であり、 例えば、 活性アル ミナ等により露点が一 4 0 °C以下に除湿された空気を吹き込み、 作業領域の 露点が一 2 0で以下に保たれている条件下で封止作業を実施する。 ごのよう して作成したサンプルのセラミックリッド接着強度は、 従来の振動子等に一 般的に用いられている低融点ガラスを被接着面としたものに比較して加湿加 速下での強度ははるかに強くなる。  The environmental conditions (especially humidity) during the sealing process are important. For example, air dehumidified by activated alumina etc. with a dew point of 140 ° C or less is blown, and the dew point of the working area is 120 ° C or less. The sealing operation is carried out under the condition maintained at. The adhesive strength of the ceramic lid of the sample prepared in this way is higher than that of the sample with a low melting point glass that is generally used for conventional oscillators, etc. Will be much stronger.
また、 本発明によれば、 集合基板を用いた素子のパッケージング方法、 す なわち、 セラミック基板上にスルーホールを含む分割線を縦横に設けること によってパッケージ用基板領域を複数形成する工程;前記スルーホールを通 つて基板表裏面を導通する導体路を形成する工程:各基板領域において素子 を搭載する側の面に素子搭載用の内部電極及び内部電極と前記スルーホール 内導体路とを接続する導体線路を形成する工程;各基板領域において素子を 搭載する側とは反対側の面に前記スルーホール内導体路と電気的に接続する 外部電極を形成する工程;各基板領域において基板表面に密着させたときに 素子を収容するのに十分な大きさの空間を形成する形状及び高さを有するキ ヤップ部材を用意する工程;各基板領域において、 少なくとも前記内部電極 と基板領域緣部との間において前記キャップ部材の端面と適合する形状に、 有機高分子材料層を印刷し硬化するか、 無機材料層を設けて封止補助層とす る工程:各基板領域において、 高周波用素子を搭載し前記内部電極と電気的 に接続した後、 前記キャップ部材を接着剤によって前記封止補助層上に接着 して気密封止する工程;並びに、 前記基板を前記分割線に沿って分割するェ 程を含む、 高周波素子のパッケージング方法が提供される。 Further, according to the present invention, there is provided a method of packaging an element using a collective substrate, that is, a step of forming a plurality of package substrate regions by vertically and horizontally providing dividing lines including through holes on a ceramic substrate; Step of forming a conductive path for conducting the front and back surfaces of the substrate through the through hole: connecting the internal electrode for mounting the element and the internal electrode to the conductive path inside the through hole on the surface on the element mounting side in each substrate area. Forming conductor lines; forming elements in each substrate area Forming an external electrode on the surface opposite to the mounting side to be electrically connected to the conductor path in the through-hole; in each of the substrate regions, a large enough to accommodate the element when brought into close contact with the substrate surface; Preparing a cap member having a shape and a height for forming a space of a height; in each substrate region, at least between the internal electrode and the substrate region 緣, a shape adapted to the end face of the cap member; A step of printing and curing a polymer material layer or providing an inorganic material layer as a sealing auxiliary layer: in each substrate region, after mounting a high-frequency element and electrically connecting to the internal electrode, the cap A method for packaging a high-frequency element, comprising: bonding a member onto the sealing auxiliary layer with an adhesive to hermetically seal; and dividing the substrate along the dividing line. It is.
ここで、 素子搭載までの手順は第 1 1〜1 2図に関連して説明した通りで あり、 その後、 素子を搭載し、 ワイヤボンディングによる結線を行なう (第 1 3図 (a) ) 。 ワイヤボンディング後、 基板表面をキャップ部材 7 7で封止して から、 パッケージングされた個々のモジュールに分離する (第 1 3図(c) ) 。 個別チップへの分離は、 基板に分割線を浅く形成しておき、 樹脂封止後に当 該分割線に沿って変形力を加えることによって基板を分割すればよい。 スル 一ホール 7 2に沿って分割することによりスルーホール 7 2内面を裏面への 導通部または側面電極 7 9として用いることが可能となる。  Here, the procedure up to the mounting of the element is the same as that described with reference to FIGS. 11 and 12. Thereafter, the element is mounted and the connection is performed by wire bonding (FIG. 13 (a)). After wire bonding, the substrate surface is sealed with a cap member 77, and then separated into individual packaged modules (FIG. 13 (c)). For separation into individual chips, the substrate may be divided by forming a shallow dividing line on the substrate and applying a deforming force along the dividing line after resin sealing. By dividing along the through hole 72, the inner surface of the through hole 72 can be used as a conductive portion to the back surface or a side electrode 79.
この方法では、 各基板領域の縁部がキャップ部材の接着により構造的に補 強された状態で集合基板を分割するため、 分割時の応力が分割線に集中しや すく、 基板領域毎の分割をより確実に実現できる。  In this method, the aggregate substrate is divided in a state where the edge of each substrate region is structurally reinforced by bonding the cap member, so that the stress at the time of division tends to concentrate on the division line, and the division of each substrate region is performed. Can be realized more reliably.
また、 本発明の製造方法またはパッケージング方法では、 高周波パッケ一 ジあるいはパッケージングされたモジユールの検査方法の効率化が実現でき る。  Further, according to the manufacturing method or the packaging method of the present invention, it is possible to realize an efficient method for inspecting a high-frequency package or a packaged module.
これはパッケージまたはパッケージングされたモジュ一ルの集合体に対 し、 検査手段としてウェハプロ一バを用いることにより行なう。 ウェハプローバは、 半導体製品の精密測定、 中間検査、 出荷検査に広く用 いられている測定機器であり、 テス卜ヘッド、 プローブカード及び X Y方向 及び上下方向に移動自在なステージを含む。 プローブカードはテストへッド に取り付けられる交換可能な部品であり、 複数の配線と当該配線とそれぞれ 電気的に接続された複数のプローブピンとからなる。 ウェハプローバによる 半導体ウェハの検査では、 ダイシングされる前の半導体ウェハをステージ上 に載置し、 ウェハ上に集合的に形成された半導体製品の電極に前記プローブ ピンを接触させて電極間に流れる電流を計測し、 電気特性の検査により不良 品の識別を行なう。 This is done by using a wafer probe as an inspection means for a package or an assembly of packaged modules. Wafer probers are widely used for precision measurement, intermediate inspection, and shipping inspection of semiconductor products, and include a test head, a probe card, and a stage that can be moved in the XY and vertical directions. The probe card is a replaceable part that is attached to the test head and includes a plurality of wires and a plurality of probe pins electrically connected to the wires. In the inspection of a semiconductor wafer by a wafer prober, the semiconductor wafer before being diced is placed on a stage, and the probe pins are brought into contact with the electrodes of the semiconductor products collectively formed on the wafer, so that a current flowing between the electrodes is obtained. Is measured, and defective products are identified by inspection of electrical characteristics.
本発明の検査方法は、 半導体ウェハの検査装置としては既知であるが、 従 来、 高周波パッケ一ジ及び/またはパッケージングされた高周波素子の検査 には用いられることのなかったウェハプロ一バをこれらの検査に用いること を特徴とする。 具体的には、 前述の集合基板を素子搭載領域側を下側にして ウェハプロ一バのステージに載置し、 基板裏面の電極に対してプローブピン を接触させて個別の高周波素子の検査を行なう。 素子の搭載前は基板の表側 について各種の検査を行うこともできる。  Although the inspection method of the present invention is known as an inspection apparatus for a semiconductor wafer, a wafer probe which has not been used for inspection of a high-frequency package and / or a packaged high-frequency element has been disclosed. It is characterized in that it is used for inspection. Specifically, the above-mentioned collective substrate is placed on the stage of a wafer probe with the element mounting area side down, and probe pins are brought into contact with the electrodes on the back surface of the substrate to inspect individual high-frequency elements. . Before mounting the device, various inspections can be performed on the front side of the board.
具体的検査方法は、 ウェハプローバによる半導体ウェハの検査方法をほぼ そのまま利用することが可能である。 例えば、 高周波パッケージの入出力電 極位置を所望の電気特性に応じて変更した場合でも、 プローブカードゃプロ ーブピンの交換、 制御プログラムの変更により行えばよい。 このため、 多様 な製品を低コストで検査することが可能となる。 ウェハプローバの検査処理 能力は精密測定でも 1製品領域当たり 1秒は超えない。 マルチプローバを適 用して複数の高周波素子 (またはパッケージ) を同時に検査してもよい。 こ の場合には 1製品領域当たりの検査時間は 1/2〜1 /3秒に短縮される。  As a specific inspection method, a semiconductor wafer inspection method using a wafer prober can be used almost as it is. For example, even when the input / output electrode position of the high-frequency package is changed according to the desired electrical characteristics, it may be performed by exchanging the probe card / probe pin and changing the control program. Therefore, it is possible to inspect various products at low cost. Wafer prober inspection processing capacity does not exceed 1 second per product area even in precision measurement. Multiple high-frequency devices (or packages) may be inspected simultaneously by applying a multi-prober. In this case, the inspection time per product area is reduced to 1/2 to 1/3 second.
前述のように、 従来の積層型高周波素子 (またはパッケージ) では、 その 構造上、 検査には個別モジュールに対応した専用治具の製作が必要であった 力^ 本発明の方法では、 ウェハプロ一バにおいて集合基板をウェハに代えて 用いるため、 個別モジュール用の専用治具は不要となる。 さらに、 ウェハプ ローバは可動ステージを有しているため、 従来の高周波素子 (またはパッケ —ジ) の自動検査で用いられていた大型の搬送装置も不要であり、 プローブ は半永久的に利用可能である。 As described above, conventional multilayer high-frequency devices (or packages) require the production of special jigs corresponding to individual modules for inspection due to their structure. Force According to the method of the present invention, a collective substrate is used in place of a wafer in a wafer prober, so that a dedicated jig for an individual module is not required. Furthermore, since the wafer probe has a movable stage, there is no need for the large-sized transfer equipment used in the conventional automatic inspection of high-frequency devices (or packages), and the probe can be used semi-permanently. .
さらに、 ウェハプロ一バでは、 校正用基板の利用によりプローブ先端まで の校正が可能となる。 この結果、 製品本来の特性が精密に測定できるように なる。 また、 温度特性の検査も容易である。 温度特性に関する品質保証は、 従来からセラミック製電子部品における大きな問題点であり、 従来の大型の 搬送装置を用いた自動検査装置を用いて室温以外の検査を行おうとすると検 査システム全体を恒温室に保持するなどの大がかりな変更が必要であり現実 的ではなかった。 しかし、 一般にウェハプローバは持ち運びできる程度の小 型の装置であり、 S〇 L T (Shor t -Open-Load-Th rough)校正などのプロ一ブ レベルでの校正が可能であるため、 温度特性の精密な測定を容易に行なうこ とができる。  Furthermore, in the wafer probe, the calibration up to the probe tip can be performed by using the calibration substrate. As a result, the intrinsic characteristics of the product can be accurately measured. It is also easy to inspect temperature characteristics. Quality assurance regarding temperature characteristics has always been a major problem with ceramic electronic components. Major changes, such as maintenance, were necessary and were not realistic. However, in general, a wafer prober is a small device that can be carried around and can be calibrated at the probe level such as S-LT (Short-Open-Load-Through) calibration. Precise measurement can be easily performed.
本発明の高周波素子用パッケージは数十 M H z〜1 0 0 G H zの広い範囲 の高周波素子について適用が可能である。 発明を実施するための最良の形態  The high-frequency element package of the present invention can be applied to a wide range of high-frequency elements of several tens of MHz to 100 GHz. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 実施例により本発明をより具体的に説明する。  Hereinafter, the present invention will be described more specifically with reference to examples.
実施例 1  Example 1
( 1 ) 紫外線処理による接着性改善  (1) Improvement of adhesion by UV treatment
厚さ 0 . 6 4 mmの 5 mm角 9 6アルミナ基板上に A g— P d合金の厚 膜導体ペーストを用いて厚膜印刷により電極及び導体線路を形成し (第 3 図(b) ) 、 さらに、 レべリング剤としてのシリコーンオイル (含量 0 . 6 w t ) 、 無機充填材として平均粒径 5 z mのシリカ微粉末と硬化剤としてェポ キシ付加物を含有するフエノール樹脂剤 (B P A (ビスフエノール A) レゾ —ル型フエノールレジン) を基板表面にその緣部に沿って印刷した (第 3図 (c) ) 。 硬化後、 積算光量計にて照射エネルギーを測定しながら合成石英ガ ラス水銀ランプ (日本電池製) ) を照射した (第 3図(d) ) 。 このようにし て製造された基板に SAWフィル夕を搭載後、 A uワイヤによりボンディング を行い素子と厚膜基板の電気的接合を施した (第 3図(e) ) 。 Electrodes and conductive lines are formed on a 0.64 mm thick 5 mm square 96 alumina substrate by thick film printing using a thick film conductor paste of Ag-Pd alloy (Fig. 3 (b)). In addition, silicone oil (content 0.6 wt) as leveling agent, silica fine powder with an average particle size of 5 zm as inorganic filler, and epoxy as hardener A phenolic resin agent (BPA (bisphenol A) resole type phenolic resin) containing a xy adduct was printed on the surface of the substrate along a part of the surface (Fig. 3 (c)). After curing, a synthetic quartz glass mercury lamp (manufactured by Nippon Battery) was irradiated while measuring the irradiation energy with an integrating photometer (Fig. 3 (d)). After mounting the SAW film on the substrate manufactured in this way, bonding was performed using Au wires to electrically connect the element to the thick film substrate (Fig. 3 (e)).
一方、 ビスフエノール A型エポキシ樹脂を主成分とする接着剤を予め調整 し、 接着前の接着剤と被接着面の樹脂の表面張力が等しくその結果界面張力 が最小化されて、 より良好な接着状態が実現出来るように、 エポキシ付加物 (硬化剤) 、 無機微粒子及びワニスを添加し熟成後、 前記被接着面に塗布 し、 乾燥空気中において厚さ (肉厚) 0. 5mmのアルミナ ·セラミック製キ ヤップを接着して封止を行った (第 3図(Π ) 。  On the other hand, an adhesive containing bisphenol A-type epoxy resin as the main component is adjusted in advance, and the surface tension of the adhesive before bonding is equal to the surface tension of the resin on the surface to be bonded. Epoxy adduct (curing agent), inorganic fine particles, and varnish are added and ripened so that the state can be realized, and the coating is applied to the surface to be bonded. Alumina ceramic with a thickness (wall thickness) of 0.5 mm in dry air Sealing was performed by bonding a cap made of glass (Fig. 3 (Π)).
上記のパッケージを環境試験器内において 1 2 I t:、 2気圧、 湿度 1 0 0 %の環境中に保持し伝送特性 (201 ogMag l S I ) を指標として特性劣化を評 価した。 また、 有機高分子硬化層を有しないほかは上記と同様にして製造し た SAWフィルタモジュールについても同様の試験を行った。  The above package was kept in an environment of 12 It :, 2 atm, and 100% humidity in an environmental tester, and the characteristic degradation was evaluated using the transmission characteristics (201 ogMagl SI) as an index. In addition, the same test was performed on a SAW filter module manufactured in the same manner as above except that the organic polymer cured layer was not provided.
その結果、 本発明の SAWフィル夕モジュールでは 5 0時間経過後でもほぼ 初期の特性を維持しており、 本発明の SAWフィル夕モジュールは優れた気密 性を有することが示された。 また、 比較試験例では 5 0時間経過後には著し い特性劣化が認められ、 本発明の効果は、 単なる接着剤封止では実現できな い水準のものであることが確認された。  As a result, the SAW filter module of the present invention maintained almost the initial characteristics even after the elapse of 50 hours, indicating that the SAW filter module of the present invention has excellent airtightness. Further, in the comparative test example, remarkable deterioration of characteristics was observed after 50 hours, and it was confirmed that the effect of the present invention was at a level that could not be realized by mere sealing with an adhesive.
( 2 ) プラズマ処理による接着性改善  (2) Improvement of adhesion by plasma treatment
(a)予備実験  (a) Preliminary experiment
9 6アルミナ基板上にシリカガラスペースト (下記(b)の試料 Aと同じも の) を厚さ 1 5 mとなるように印刷し、 これを 8 5 0 °Cで焼成した。 焼成 後の表面を電子顕微鏡で観察したところ、 微細結晶が析出しているのが確認 された。 これはアルミノバリウムシリケ一ト系の微結晶だと考えられる。 接触角測角器を適用して、 この結晶化シリカガラス表面上に水滴を垂ら し、 その接触角を測定したところ 8〜 1 5° の結果が得られた。 結晶化シリ 力ガラス被覆層を設けない表面清浄な 96アルミナ基板では接触角は 70〜 80 ° であり結晶化シリカガラス層の付与がぬれ性改善に有用であることが 確認された。 A silica glass paste (same as the sample A in (b) below) was printed on a 96-alumina substrate so as to have a thickness of 15 m, and was fired at 850 ° C. When the surface after firing was observed with an electron microscope, it was confirmed that fine crystals had precipitated. Was done. This is considered to be aluminobarium silicate-based microcrystals. A water drop was dropped on the surface of the crystallized silica glass using a contact angle goniometer, and the contact angle was measured. The result was 8 to 15 °. The contact angle was 70-80 ° on a 96-alumina substrate with a clean surface without a crystallized silica glass coating layer, confirming that the application of the crystallized silica glass layer was useful for improving wettability.
(b)プラズマ処理 (b) Plasma treatment
厚さ 0.64mmの 5mm角 96アルミナ基板上に A g— P d合金の厚膜 導体ペーストを用いて電極及び導体線路を形成し (第 3図(b)) 、 さらに、 無機ガラス材料を基板表面にその縁部に沿って印刷した (第 3図(c) )。 なお、 無機ガラス層を設けない以外は上記と同じ試料も対照として作成し た。  Electrodes and conductor lines are formed on a 0.64 mm thick 5 mm square 96 alumina substrate using an Ag-Pd alloy thick conductor paste (Fig. 3 (b)), and an inorganic glass material is further applied to the substrate surface. It was printed along its edge (Fig. 3 (c)). The same sample as above except that no inorganic glass layer was provided was prepared as a control.
無機材料を 8 50でで焼成後、 基板をプラズマ処理装置 (MARCH社製 PX- 1 000) の高周波電源側に載置し、 1 0— 2Torrに減圧した後、 A r ガスを導入し、 処理室内を 1 8 OmTorrに調整した。 しかる後、 出力 250 Wの条件でプラズマを発生させ、 240秒間処理した。 この処理においては 、 試料表面がプラズマ中の電子により負に帯電し、 一方、 励起されたァルゴ ンガスが陽イオンとなり加速されて試料表面に衝突する。 この結果、 基板表 面の活性化が実現する。 After firing the inorganic material in at 8 50, after placing the substrate on the high-frequency power supply side of the plasma processing apparatus (MARCH Co. PX-1 000), it was reduced to 1 0- 2 Torr, introducing A r gas, The inside of the processing chamber was adjusted to 18 OmTorr. Thereafter, plasma was generated under the condition of an output of 250 W and the treatment was performed for 240 seconds. In this treatment, the sample surface is negatively charged by the electrons in the plasma, while the excited argon gas becomes positive ions and accelerates and collides with the sample surface. As a result, activation of the substrate surface is realized.
このようにして製造した基板に SAWフィル夕を搭載後、 Auワイヤによ りボンディングを行い素子と厚膜基板の電気的接合を施し、 上記 (1) と同 様に接着剤でアルミナ ·セラミック製キャップを接着して封止を行った (第 3図(e) (f)) 。  After mounting the SAW film on the substrate manufactured in this way, bonding with an Au wire is performed to electrically connect the element and the thick film substrate. Sealing was performed by bonding the cap (Fig. 3 (e) (f)).
上記のパッケージを環境試験器内において 1 2 I :、 2気圧、 湿度 100 %の環境中に保持し伝送特性 (201ogMag|S2 l I) を指標として特性劣化を評 価した。 結晶化シリカガラス層を付与したもの、 ホウゲイ酸鉛ガラス層を付 与したもの及び対照それぞれ 1 0サンプルについて行なつた試験結果を次表 に示す。 And evaluate the characteristics deterioration of | (S 2 l I 201ogMag) as an index, 2 atm, holding transmission characteristic in 100% humidity environments: the package in the environmental test chambers 1 2 I. With crystallized silica glass layer, with lead borate glass layer The following table shows the results of tests performed on 10 samples each of which were given.
表 1  table 1
Figure imgf000032_0001
Figure imgf000032_0001
上記の結果に示されるように、 本発明に従って無機材料による封止補助層 を設け、 これをプラズマ処理して用いた場合、 高周波素子の封止パッケージ として極めて優れた結果を示すことが確認された。 なお、 封止補助層に結晶 化シリカガラス層を用いた場合は 1 0時間を越えても優れた封止効果が持続 していた。  As shown in the above results, it was confirmed that when a sealing auxiliary layer made of an inorganic material was provided according to the present invention and this was subjected to plasma treatment and used, an extremely excellent result was obtained as a sealing package for a high-frequency device. . When a crystallized silica glass layer was used as the sealing auxiliary layer, an excellent sealing effect was maintained even after more than 10 hours.
実施例 2 Example 2
GaAsFET用セラミックパッケージの構成例を第 6図及び第 7図に示す。 第 6図は本発明に従い構成されたマイク口 X構造であり、 (a)は平面図 を、 (b)は(a)中の A方向から見た側面図を示す。  6 and 7 show examples of the structure of the ceramic package for GaAs FET. FIG. 6 shows a microphone opening X structure constructed according to the present invention, wherein (a) is a plan view and (b) is a side view as viewed from the direction A in (a).
第 6図に示す本発明のマイク口 X構造パッケージは、 中央に概ね矩形状の 素子搭載領域 (図では GaAsFETベアチップ 3 1を搭載した状態を示す。 ) を 有するセラミック基板 3 2上に導体線路 G、 D、 Sを前記領域から各々直角 に形成し、 封止補助層 3 3を周状に設けた基板構造を有する。 封止補助層 3 3は、 導体線路との交差部では導体線路を覆うに十分な厚みを有する。 封止 補助層 3 3の形成 (有機高分子材料では硬化、 無機材料では焼成。 以下、 同 じ。 ) 後、 接着剤層 3 4を介してキャップ部材 3 5により封止される。 基板材料としては、 9 6アルミナ厚膜印刷基板がコストパフォーマンスに 優れるが、 基板材料としては純度が 99. 3 %のアルミナ基板や 99. 99 %のアル ミナ基板の適用も可能である。 G、 D、 Sを直交させることで寄生容量を抑 圧する。 The microphone opening X structure package of the present invention shown in FIG. 6 has a conductor line G on a ceramic substrate 32 having a substantially rectangular element mounting area (a state where a GaAs FET bare chip 31 is mounted in the figure) in the center. , D, and S are formed at right angles from the region, and a sealing auxiliary layer 33 is provided circumferentially. The sealing auxiliary layer 33 has a thickness sufficient to cover the conductor line at the intersection with the conductor line. After the formation of the sealing auxiliary layer 33 (cured for an organic polymer material and fired for an inorganic material; the same applies hereinafter), the capping member 35 is sealed via an adhesive layer 34. As a substrate material, a 96-alumina thick-film printed circuit board is excellent in cost performance, but as a substrate material, 99.3% purity alumina substrate or 99.99% aluminum substrate is used. Mina substrates can also be used. The parasitic capacitance is suppressed by making G, D, and S orthogonal.
導体線路 G、 D、 Sは、 焼成後基板に形成される平面線路であり、 ベアチ ップとワイヤボンディング等により直接接続される。 導体線路は実施例 1と 同様に厚膜印刷によるものでもよいが、 高特性の要求や超高周波用には高精 度の薄膜電極も適用可能である。  The conductor lines G, D, and S are planar lines formed on the substrate after firing, and are directly connected to the bare chip by wire bonding or the like. The conductor line may be formed by thick-film printing as in the first embodiment, but a high-precision thin-film electrode can also be used for high-performance requirements and ultrahigh-frequency applications.
第 6図に示す構造では、 入出力端子は側面電極 3 6としているが、 第 7図 には、 導体線路は第 4図に示したストリップ線路またはコプレーナ線路とす る構成例を示した。  In the structure shown in FIG. 6, the input / output terminals are the side electrodes 36, but FIG. 7 shows a configuration example in which the conductor lines are the strip lines or coplanar lines shown in FIG.
すなわち、 この GaAsFET用セラミックパッケージは、 中央に概ね矩形状の 素子搭載領域 (図では GaAsFETベアチップ 4 1を搭載した状態を示す。 ) を 有するセラミック基板 4 2上に導体線路 G、 D、 Sを前記領域から各々直角 に形成し、 封止補助層 4 3を周状に設けた基板構造を有する。 封止補助層 4 3は、 導体線路との交差部では導体線路を覆うに十分な厚みを有する。 封止 補助層 4 3の形成後、 接着剤層 4 4を介してキャップ部材 4 5により封止さ れる。 また、 基板裏面にはその実質的に全面を覆う導体層 4 6を有する。 導 体層 4 6は厚膜印刷でもよいし、 金属箔を接着することにより形成してもよ い。  That is, in the GaAsFET ceramic package, the conductor lines G, D, and S are formed on a ceramic substrate 42 having a substantially rectangular element mounting area (a state in which a GaAsFET bare chip 41 is mounted in the figure) in the center. Each substrate has a substrate structure formed at right angles from the region and provided with a sealing auxiliary layer 43 in a circumferential shape. The sealing auxiliary layer 43 has a sufficient thickness to cover the conductor line at the intersection with the conductor line. After the formation of the sealing auxiliary layer 43, the sealing is performed by the cap member 45 via the adhesive layer 44. The back surface of the substrate has a conductor layer 46 that covers substantially the entire surface. The conductor layer 46 may be formed by thick film printing or by bonding a metal foil.
第 7図のパッケージ構造において Sはスルーホールを介して裏面の GND層 4 6に接続される。  In the package structure shown in FIG. 7, S is connected to the GND layer 46 on the back surface through a through hole.
第 7図の態様では、 第 6図と同様に導体線路 G及び Dが直線上の配置なの で寄生容量の抑圧効果が高い上に、 さらに、 分布定数線路の選択の自由度が 高く高周波化が容易である、 Gと Dの分布定数線路化による電極損失及び寄 生容量の抑圧もできる、 Sはスルーホールにより直ちに GNDに接地できるの で GNDインピーダンスを抑圧できる等の特長を有する。  In the embodiment of FIG. 7, the conductor lines G and D are arranged in a straight line, as in FIG. 6, so that the effect of suppressing the parasitic capacitance is high.In addition, the degree of freedom in selecting the distributed constant lines is high and the frequency is increased. It has features that it is easy, it can suppress electrode loss and parasitic capacitance by using G and D distributed constant lines, and S can be grounded immediately to GND by through holes, so that GND impedance can be suppressed.
ま麵 3 第 9図には、 平衡-不平衡変換回路を内蔵した SAWフィル夕パッケージ 5 0 の構成例を示す。 素子 5 1を搭載する基板 5 2上に導体線路を設けた点は実 施例 1〜2と同様であるが、 この例では、 さらにインダク夕及びチップキヤ パシ夕を搭載することにより第 8図に示す平衡ー不平衡変換回路を内蔵し た。 Well 3 Fig. 9 shows an example of the configuration of a SAW filter package 50 incorporating a balanced-unbalanced conversion circuit. The point that the conductor line was provided on the substrate 52 on which the element 51 was mounted was the same as in Examples 1 and 2, but in this example, by further mounting the inductor and chip capacitor, The built-in balance-unbalance conversion circuit shown.
従来の積層技術では、 焼成時の収縮率が一定でないために、 高い精度での インダク夕及びキャパシ夕容量の調整は不可能で、 容量変動を ± 1 0 %以下 に制御することはできない。 しかし、 本発明の製造方法によれば、  With the conventional lamination technology, the shrinkage rate during firing is not constant, so it is impossible to adjust the inductance and capacity with high accuracy, and it is not possible to control the capacity fluctuation to ± 10% or less. However, according to the production method of the present invention,
① 厚膜印刷による高精度ィンダク夕の形成が可能である。  ① High-precision ink can be formed by thick film printing.
② ディスクリートキャパシ夕の容量精度は土 1 . 5 %と高い。  ② The capacity accuracy of discrete capacity is as high as 1.5% on soil.
このため中心周波数の変動はほとんどない。 Therefore, there is almost no change in the center frequency.
インダクタパターンの形成方法としては慣用のいずれの方法も用い得る。 例えば、 導電材料を厚膜印刷もしくは薄膜形成したり、 あるいは、 細線をコ ィル状に載置することにより形成することができる。 厚膜印刷では通常、 6 0〜3 0 0 程度の線幅で直径 0 . 5〜 1 0 mm程度のコイルが形成でき る。 薄膜形成では通常、 1〜 1 0 0 程度の線幅で直径 0 . l〜2 mm程 度のコイルが形成できる。  As a method for forming the inductor pattern, any conventional method can be used. For example, the conductive material can be formed by printing a thick film or a thin film, or by placing a thin wire in a coil shape. In thick-film printing, a coil having a diameter of about 0.5 to 10 mm can usually be formed with a line width of about 60 to 300. In thin film formation, a coil having a line width of about 1 to 100 and a diameter of about 0.1 to 2 mm can be formed.
なお、 この例では矩形状のスパイラルインダク夕 (角型インダク夕) を用 いているが、 その形状は、 基板表面に配置し得るものである限り目的により 変更可能である。 このようなインダク夕には、 スパイラルインダク夕の他 に、 クランク若しくはループまたはその一部をなす導体路で構成される種々 のインダク夕パターンが含まれるが、 高周波領域で用いる場合には、 I n H 以上、 通常 1〜 5 0 n H程度のものが用いられる。  In this example, a rectangular spiral inductor (square-shaped inductor) is used, but the shape can be changed according to the purpose as long as it can be arranged on the substrate surface. Such inductors include various inductor patterns composed of a crank or a loop or a conductor path forming a part thereof, in addition to the spiral inductors. More than H, usually about 1 to 50 nH is used.
第 9図の構成例では、 角型インダクタはインダク夕パターンの導体幅及び 導体線路間スペースをいずれも 1 0 0 i mとし、 以下のインダク夕ンス値を 有するインダク夕とチップキャパシ夕を用いて平衡変換器 (中心周波数 8 5 o In the configuration example shown in Fig. 9, the rectangular inductor has a conductor width of the inductor pattern and a space between conductor lines of 100 im, and is balanced by using an inductor having the following inductance value and a chip capacity. Converter (center frequency 8 5 o
0MHz) を設計した。 インダク夕ンス キャパシタンス 特性インピーダンス 構成例 1 5.62 nH 6.24 p F 30 Ω 0MHz). Inductance capacitance Characteristic impedance Configuration example 1 5.62 nH 6.24 pF 30 Ω
構成例 2 9.36 ηΗ 3.75 p F 50 Ω  Configuration example 2 9.36 ηΗ 3.75 pF 50 Ω
構成例 3 14.42 ηΗ 2.43 p F 77 Ω  Configuration example 3 14.42 ηΗ 2.43 p F 77 Ω
なお、 第 9図では、 平衡変換器は出力端子にのみ配置したが、 入力端子側 にも配置できる。 また、 第 9図では封止構造を図示していないが、 その概略 は実施例 1〜2と同様である。 但し、 インダク夕電極及びチップキャパシ夕 は、 SAWフィル夕チップとワイヤボンディングで直接接続するのでなければ 気密封止部内に含める必要はない。 例えば、 SAWフィル夕のみを実施例 1に 準じて気密封止し、 変換平衡回路はパッケージ基板の表裏面のいずれかに配 置し、 SAWフィル夕から引き出した導体線路とスルーホール等を用いて接続 してもよい。  In FIG. 9, the balanced converter is arranged only at the output terminal, but can be arranged also at the input terminal side. Although the sealing structure is not shown in FIG. 9, the outline is the same as in Examples 1 and 2. However, the inductor electrode and chip capacity need not be included in the hermetic seal unless they are directly connected to the SAW fill chip by wire bonding. For example, only the SAW filter is hermetically sealed according to the first embodiment, and the conversion balance circuit is arranged on one of the front and back surfaces of the package substrate. May be connected.
実施例 4  Example 4
第 1 1〜 1 3図に示すように、 96アルミナ基板 7 1 (95mmX 95m mx 0.64mm) の表面に 1領域当たり横 5 mm、 縦 5 mmの面積を有す る個別基板領域 90個を含むように基板中央部に分割領域を設け、 当該分割 線上にスルーホール 72を形成した。  As shown in Figs. 11 to 13, the surface of a 96-alumina substrate 71 (95 mm x 95 mm mx 0.64 mm) contains 90 individual substrate areas with an area of 5 mm wide and 5 mm long per area As described above, a divided region was provided in the center of the substrate, and a through hole 72 was formed on the divided line.
次いで、 スルーホール側面に導体ペーストを充填印刷し、 また、 各個別基 板領域の表裏面において、 導体パターン 7 3を印刷した。  Next, a conductive paste was filled and printed on the side surfaces of the through holes, and conductive patterns 73 were printed on the front and back surfaces of each individual substrate region.
しかる後、 回路パターンを焼成し、 各個別基板領域において、 素子搭載領 域と基板領域縁部との間に封止補助層 74を周状に印刷し、 これを硬化また は焼成後表面活性化処理した (処理後の封止補助層は 75で示す。 ) 。 次い5 で、 素子搭載領域の中央に SAWフィルタチップ 76を搭載し、 ワイヤボンデ イングを実施した。 これらの操作はいずれも実施例 1と同様である。 基板表 面のすべての個別領域においてワイヤボンディングを完了した後、 基板表面 にキャップ部材 77を接着して封止し、 パッケージ構造 78を形成した。 こ れらの操作も実施例 1と同様である。 Thereafter, the circuit pattern is fired, and in each individual substrate area, a sealing auxiliary layer 74 is printed circumferentially between the element mounting area and the edge of the substrate area, and this is cured or fired to activate the surface. (The sealing auxiliary layer after the treatment is indicated by 75.) Next, in 5, the SAW filter chip 76 was mounted in the center of the element mounting area, and wire bonding was performed. All of these operations are the same as in Example 1. Board table After wire bonding was completed in all the individual regions on the surface, a cap member 77 was adhered to the surface of the substrate and sealed to form a package structure 78. These operations are the same as in the first embodiment.
市販のウェハプローバのステージ上に前記の集合基板を裏面を上側にして 載置し、 予めプログラムした手順に従い、 各高周波素子の特性を検査した。 なお、 ウェハプロ一バは校正用基板を用いて予め SOLT校正し、 20°Cの 条件で測定した。  The above-mentioned collective substrate was placed on the stage of a commercially available wafer prober with its back surface facing upward, and the characteristics of each high-frequency element were inspected according to a previously programmed procedure. The wafer probe was subjected to SOLT calibration in advance using a calibration substrate, and measurement was performed at 20 ° C.
全領域の検査が完了した後、 基板をステージからはずし、 分割線に沿って 力を加えることにより高周波素子をパッケージングした合計 90個の個別モ ジュールを得た。 なお、 検査に要した時間は全体で 90秒であり、 従来法で 同数の個別高周波素子を検査する場合と比べ著しく短縮された。  After the inspection of the entire area was completed, the substrate was removed from the stage, and a total of 90 individual modules packaged with high-frequency devices were obtained by applying force along the dividing line. In addition, the time required for the inspection was 90 seconds in total, which was significantly shorter than the case of inspecting the same number of individual high-frequency elements by the conventional method.
実施例 5 Example 5
厚さ 0.64 mmのアルミナ基板上に誘電体共振器及び低雑音 GaAsFETチッ プ及び受動素子 (TE型誘電体共振器) を搭載してなる 1 0 GHz帯発振器 において、 GaAsFETチップおよび誘電体共振器から成る回路全体を金属製キ ヤップで気密封止する。 なお、 素子間の導体線路はフォトレジスト法により 高精度薄膜電極として形成する。  In a 10 GHz band oscillator with a dielectric resonator and a low-noise GaAsFET chip and passive element (TE-type dielectric resonator) mounted on a 0.64 mm-thick alumina substrate, a GaAsFET chip and a dielectric resonator were used. The entire circuit is hermetically sealed with a metal cap. The conductor lines between the elements are formed as high-precision thin-film electrodes by the photoresist method.
1 0 GHz以上で適用される発振器は、 発振用 G aAs半導体の同調を T E型誘電体共振器 (DRO) で取ることで発振特性を得ている。 1 0 GHz 程度では、 マイクロ X—パッケージの寸法と比較して DR〇寸法は大きく、 DROの共振電磁界は攪乱されない。 しかし、 周波数が高くなると DRO寸 法は小さくなり、 共振電磁界はマイクロ X—パッケージにより攪乱されるよ うになる。 また、 パッケージ自体の共振も発振特性に悪影響を及ぼす。 そこ で、 より高い周波数帯では G a A s半導体をペアチップで搭載する必要が生 じる。 ところが、 DROは適当な大きさの共振用金属筐体に設置する必要が あるために、 従来、 発振用 GaAs半導体をペアチップで搭載するにはハー メチック · シール (気密性金属ケース) を適用せざるを得なかった (第 1 4 図(a) ) 。 しかし、 本発明の技術を適用すれば、 金属製キャップを接着する だけで、 1 0 GH z以上の発振器が制作できる (第 1 4図(b) ) 。 産業上の利用の可能性 Oscillators applied at 10 GHz or higher obtain oscillation characteristics by tuning the GaAs semiconductor for oscillation with a TE-type dielectric resonator (DRO). At about 10 GHz, the DR〇 dimension is large compared to the micro X-package dimensions, and the DRO's resonant electromagnetic field is not disturbed. However, as the frequency increases, the DRO dimensions decrease, and the resonant fields become disturbed by the micro X-package. Also, the resonance of the package itself adversely affects the oscillation characteristics. Therefore, in higher frequency bands, it is necessary to mount GaAs semiconductors on a pair chip. However, since the DRO needs to be installed in an appropriately sized metal housing for resonance, it has conventionally been difficult to mount a GaAs semiconductor for oscillation on a pair chip. A mechanical seal (airtight metal case) had to be applied (Fig. 14 (a)). However, if the technology of the present invention is applied, an oscillator of 10 GHz or more can be produced only by bonding a metal cap (FIG. 14 (b)). Industrial applicability
従来の積層型パッケージでは、 パッケージ構造材料と導体材料の同時焼成 が不可欠であり、 この際、 焼成収縮による導体寸法の変動を不可避的に伴う。 また、 電極及び導体線路の形成法は実質的に厚膜印刷に限定されている。 こ れに対し、 本発明では焼成済みセラミック基板を用いるために、 焼成収縮に よる電極精度の劣化という問題が解消され、 かつ、 薄膜形成による電極形成 も可能であり、 超高周波用の精度の高い電極 (導体線路) をパッケージ構造 上に内蔵することができる。 このような精度の高い電極パターンの実現はパ ッケージ毎の寄生容量のばらつきを実質的に解消するとともに、 導体線路に よるインピーダンスの微調整を可能とする。 このため、 本発明のパッケージ を用いることにより、 小型かつ低コストで高信頼性 '高特性の高周波素子を 製造することが可能となる。  In a conventional stacked package, simultaneous firing of the package structure material and the conductor material is indispensable, and in this case, variations in conductor dimensions due to shrinkage of the firing are inevitable. Also, the method of forming the electrodes and the conductor lines is substantially limited to thick film printing. On the other hand, in the present invention, since the fired ceramic substrate is used, the problem of electrode precision deterioration due to firing shrinkage is solved, and electrode formation by thin film formation is also possible. Electrodes (conductor lines) can be built into the package structure. The realization of such a highly accurate electrode pattern substantially eliminates the variation in the parasitic capacitance of each package and enables fine adjustment of the impedance by the conductor line. Therefore, by using the package of the present invention, it is possible to manufacture a small, low-cost, high-reliability, high-characteristic high-frequency device.
また、 現在、 ミリ波帯を利用した車載レーダが実用化されつつある等、 高 周波機器の民間利用が進んでいるが、 従来、 この帯域の製品は高コストな技 術が躊躇なく用いられていたのが実状である。 しかるに、 本発明によれば、 例えば、 廉価な封止部材の使用や、 技術的蓄積のあるストリップ線路による インピーダンス補正等により、 高性能なミリ波帯モジュールを低コス卜で実 現することができる。 新技術の開発には多額の開発費が必要であり、 先端技 術分野では開発費の削減が製品の低価格化に直結するが、 このように本発明 の封止技術は、 近年、 ミリ波帯モジュールで試みられつつある厚膜コプレー ナ型導波線路等の新技術を必要とせず、 技術的蓄積のあるストリップ線路技 術の応用により特性改善を実現し得るものであるため、 ミリ波帯モジュール の低価格化と高性能化を両立させる。 In addition, the use of high-frequency equipment in the private sector is increasing, for example, in-vehicle radars using the millimeter-wave band are being put into practical use.However, in the past, high-cost technologies for products in this band have been used without hesitation. The truth is. However, according to the present invention, a high-performance millimeter-wave band module can be realized at a low cost, for example, by using an inexpensive sealing member or by performing impedance correction using a strip line with technical accumulation. . The development of new technologies requires a large amount of development costs, and in the advanced technology field, reducing development costs is directly linked to lower product prices. Thus, the sealing technology of the present invention It does not require new technologies such as thick-film coplanar waveguides, which are being tried in band modules, and can achieve improved characteristics by applying stripline technology with accumulated technology to the millimeter-wave band. module To achieve both low price and high performance.
さらにまた、 本発明の方法によれば、 高周波素子パッケージあるいはパッ ケージングされた高周波モジュールを集合基板として製造 ·検査できるた め、 その取扱性が大幅に改善され、 検査の迅速化 '高度化の観点でも極めて 大きな有用性を有する。  Furthermore, according to the method of the present invention, since a high-frequency element package or a packaged high-frequency module can be manufactured and inspected as a collective substrate, the handling property is greatly improved, and the inspection is speeded up. But it has tremendous utility.

Claims

請求の範囲 The scope of the claims
1 . (a)高周波用素子搭載領域を有するセラミック基板と (b)前記基板の 表面に密着させたときに素子を収容するのに十分な大きさの空間を形成する 形状及び高さを有するキャップ部材とを含む高周波素子用パッケージであつ て、 前記セラミック基板が、 基板材料の焼成後に形成された素子搭載用の内 部電極、 外部電極及びその間を接続する導体線路、 並びに、 素子搭載領域と 基板緣部との間において前記キヤップ部材の端面と適合する形状に設けられ た有機高分子材料の硬化体または無機材料からなる封止補助層を有し、 素子 を前記領域に搭載し前記内部電極と電気的に接続した後、 前記キャップ部材 を接着剤によつて前記封止補助層上に接着して気密封止してなることを特徴 とする高周波素子用パッケージ。 1. (a) A ceramic substrate having a high-frequency element mounting area, and (b) a cap having a shape and height that forms a space large enough to accommodate the element when brought into close contact with the surface of the substrate. A high-frequency element package including a member, wherein the ceramic substrate is formed after sintering of a substrate material, an internal electrode for mounting the element, an external electrode, and a conductor line connecting between the electrodes, and an element mounting area and the substrate. A sealing auxiliary layer made of a cured product of an organic polymer material or an inorganic material provided in a shape compatible with the end face of the cap member between the 緣 portion and a device mounted on the region, and After the electrical connection, the cap member is bonded to the sealing auxiliary layer with an adhesive to hermetically seal the package.
2 . 前記封止補助層が、 紫外線照射またはプラズマ処理により表面が活性 化処理されたものである請求の範囲第 1項に記載の高周波素子用パッケ一 ジ。  2. The package for a high-frequency device according to claim 1, wherein the surface of the sealing auxiliary layer is activated by ultraviolet irradiation or plasma treatment.
3 . 前記有機高分子材料がエポキシ系樹脂、 フエノール系樹脂またはェポ キシフエノール系樹脂から選択される樹脂を含む請求の範囲第 1項に記載の 高周波素子用パッケージ。  3. The high-frequency element package according to claim 1, wherein the organic polymer material includes a resin selected from an epoxy resin, a phenol resin, and an epoxy phenol resin.
4 . 前記無機材料が結晶化シリカガラスである請求の範囲第 1項に記載の 高周波素子用パッケージ。  4. The high frequency element package according to claim 1, wherein the inorganic material is crystallized silica glass.
5 . パッケージングされた素子のインピーダンスを前記導体線路により最 適化した請求の範囲第 1項に記載の高周波素子用パッケージ。  5. The high-frequency device package according to claim 1, wherein the impedance of the packaged device is optimized by the conductor line.
6 . 前記導体線路が薄膜形成により形成された高精度分布定数線路を含む 請求の範囲第 1項に記載の高周波素子用パッケージ。  6. The high-frequency element package according to claim 1, wherein the conductor line includes a high-precision distributed constant line formed by forming a thin film.
7 . 前記導体線路がコプレーナ線路を含む請求の範囲第 1項に記載の高 周波素子用パッケージ。 7. The high-frequency element package according to claim 1, wherein the conductor line includes a coplanar line.
8 . 前記セラミック基板がアルミナまたはアルミナよりも大きな誘電率を 有する誘電体材料から選択される請求の範囲第 1項に記載の高周波素子用 パッケーシ。 8. The package for a high-frequency device according to claim 1, wherein the ceramic substrate is selected from alumina or a dielectric material having a higher dielectric constant than alumina.
9 . 前記キャップ部材がセラミック、 金属または高分子材料から選択され る請求の範囲第 1項に記載の高周波素子用パッケージ。  9. The high frequency element package according to claim 1, wherein the cap member is selected from a ceramic, a metal, or a polymer material.
1 0 . 前記基板表面にらせんインダクタ及び/またはチップキャパシ夕を 含む回路を設けた請求の範囲第 1項に記載の高周波素子用パッケージ。 10. The high-frequency element package according to claim 1, wherein a circuit including a spiral inductor and / or a chip capacitor is provided on the surface of the substrate.
1 1 . 前記素子が SAWフィル夕、 MIC、 MMICまたは GaAsFETである請求の範 囲第 1項に記載の高周波素子用パッケージ。 11. The high-frequency element package according to claim 1, wherein the element is a SAW filter, a MIC, an MMIC, or a GaAs FET.
1 2 . 前記素子が SAWフィルタであり、 基板上に平衡-不平衡変換回路を有 する請求の範囲第 1 1項に記載の SAWフィルタ用パッケージ。  12. The SAW filter package according to claim 11, wherein the element is a SAW filter, and the circuit has a balanced-unbalanced conversion circuit on a substrate.
1 3 . 前記素子が GaAsFETであり、 ゲ一卜(G)、 ドレイン(D)に接続する各 導体線路が直線上に、 ソース (S) に接続する分布定数線路がこれに直交す るように前記基板上に設けられていることを特徴とする請求の範囲第 1 1項 に記載の GaAsFET用パッケージ。  13 3. The device is a GaAs FET, and the conductor lines connected to the gate (G) and drain (D) are on a straight line, and the distributed constant line connected to the source (S) is orthogonal to this. The GaAsFET package according to claim 11, wherein the GaAsFET package is provided on the substrate.
1 4 . 導体線路で接続された複数の素子搭載領域を基板上に有し、 これら の素子を含む全体またはこれらの素子のうち気密封止を要する素子の 1以上 が前記キヤップ部材により請求の範囲第 1項に記載のパッケージ構造によ つて封止される高周波モジュール用パッケージ。  14. A plurality of element mounting areas connected by a conductor line on a substrate, and the whole including these elements or one or more of these elements that need to be hermetically sealed by the cap member are claimed. A high-frequency module package sealed by the package structure according to item 1.
1 5 . 焼成されたセラミック基板に素子搭載用の内部電極、 外部電極及び その間を接続する導体線路を形成する工程;前記基板の表面に密着させたと きに素子を収容するのに十分な大きさの空間を形成する形状及び高さを有す るキャップ部材を形成する工程;並びに、 少なくとも前記内部電極と基板縁 部との間において前記キャップ部材の端面と適合する形状に、 有機高分子材 料層を印刷し硬化するか、 無機材料層を設ける工程を含む、 請求の範囲第 1 項乃至第 1 4項のいずれかに記載の高周波素子用パッケージを製造する方 法。 15. The step of forming the internal electrodes for mounting the elements, the external electrodes, and the conductor lines connecting between them on the fired ceramic substrate; large enough to accommodate the elements when brought into close contact with the surface of the substrate Forming a cap member having a shape and a height to form a space for the organic polymer material; and forming a cap member at least between the internal electrode and the edge of the substrate so as to conform to the end face of the cap member. A method for manufacturing a high-frequency element package according to any one of claims 1 to 14, comprising a step of printing and curing a layer or providing an inorganic material layer. Law.
1 6 . 前記有機高分子材料硬化層または無機材料層の表面を紫外線照射ま たはプラズマ処理により活性化する工程をさらに含む請求の範囲第 1 5項に 記載の高周波素子用パッケージ製造方法。  16. The method for manufacturing a package for a high-frequency element according to claim 15, further comprising a step of activating the surface of the cured organic polymer material layer or the inorganic material layer by ultraviolet irradiation or plasma treatment.
1 7 . セラミック基板上にスルーホールを含む分割線を縦横に設けること によってパッケージ用基板領域を複数形成する工程;前記スルーホールを通 つて基板表裏面を導通する導体路を形成する工程;各基板領域において素子 を搭載する側の面に素子搭載用の内部電極及び内部電極と前記スルーホール 内導体路とを接続する導体線路を形成する工程; 各基板領域において素子を 搭載する面とは反対側の面に前記スルーホール内導体路と電気的に接続する 外部電極を形成する工程; 各基板領域において基板表面に密着させたときに 素子を収容するのに十分な大きさの空間を形成する形状及び高さを有するキ ヤップ部材を形成する工程;各基板領域において、 少なくとも前記内部電極 と基板領域緣部との間において前記キャップ部材の端面と適合する形状に、 有機高分子材料層を印刷し硬化するか、 無機材料層を設ける工程;並びに、 前記基板を前記分割線に沿って分割する工程を含む方法により、 前記基板領 域とキャップ部材とをもって請求の範囲第 1項乃至第 1 5項のいずれかに記 載されたパッケージ基板とキャップ部材とする高周波素子用パッケージの製 造方法。  17. A step of forming a plurality of package substrate regions by vertically and horizontally providing dividing lines including a through hole on a ceramic substrate; a step of forming a conductive path for conducting the front and back surfaces of the substrate through the through hole; Forming an internal electrode for mounting an element and a conductor line connecting the internal electrode and the internal conductor path in the through hole on the surface on the side where the element is mounted in the region; the side opposite to the surface on which the element is mounted in each substrate region Forming an external electrode electrically connected to the conductor path in the through hole on the surface of the substrate; a shape that forms a space large enough to accommodate the element when it is brought into close contact with the substrate surface in each substrate region And forming a cap member having a height; and in each substrate region, at least an end surface of the cap member between the internal electrode and the substrate region 緣. A step of printing and curing an organic polymer material layer or providing an inorganic material layer in a suitable shape; and a step of dividing the substrate along the dividing line, the substrate region and the cap member. 16. A method for manufacturing a package for a high-frequency element, wherein the package is a package substrate and a cap member according to any one of claims 1 to 15.
1 8 . 接着工程に先立ち、 前記有機高分子材料硬化層または無機材料層の 表面を紫外線照射またはプラズマ処理により活性化する工程をさらに含む請 求の範囲第 1 7項に記載の高周波素子用パッケージ製造方法。  18. The high frequency element package according to claim 17, further comprising a step of activating the surface of the cured organic polymer material layer or the inorganic material layer by ultraviolet irradiation or plasma treatment prior to the bonding step. Production method.
1 9 . 前記分割に先立ち、 さらに各基板領域の電気的特性を検査する工程 を含む請求の範囲第 1 7項または第 1 8項に記載の高周波素子用パッケージ の製造方法。  19. The method for manufacturing a high-frequency device package according to claim 17, further comprising a step of inspecting electrical characteristics of each substrate region before said division.
2 0 . 前記検査が半導体検査用のゥエーハプローバを用いて行われる請求 の範囲第 1 9項に記載の高周波素子用パッケージの製造方法。 20. The inspection is performed using a semiconductor probe inspection prober. Item 10. The method for manufacturing a high-frequency element package according to Item 19.
2 1 . セラミック基板上にスルーホールを含む分割線を縦横に設けること によってパッケージ用基板領域を複数形成する工程;前記スルーホールを通 つて基板表裏面を導通する導体路を形成する工程;各基板領域において素子 を搭載する側の面に素子搭載用の内部電極及び内部電極と前記スルーホール 内導体路とを接続する導体線路を形成する工程;各基板領域において素子を 搭載する側とは反対側の面に前記スルーホール内導体路と電気的に接続する 外部電極を形成する工程;各基板領域において基板表面に密着させたときに 素子を収容するのに十分な大きさの空間を形成する形状及び高さを有するキ ヤップ部材を用意する工程;各基板領域において、 少なくとも前記内部電極 と基板領域縁部との間において前記キャップ部材の端面と適合する形状に、 有機高分子材料層を印刷し硬化するか、 無機材料層を設けて封止補助層とす る工程;各基板領域において、 高周波用素子を搭載し前記内部電極と電気的 に接続した後、 前記キヤップ部材を接着剤によつて前記封止補助層上に接着 して気密封止する工程;並びに、 前記基板を前記分割線に沿って分割するェ 程を含む、 高周波素子のパッケージング方法。 21. Step of forming a plurality of package substrate regions by providing vertical and horizontal dividing lines including through holes on a ceramic substrate; forming conductor paths that conduct the front and back surfaces of the substrate through the through holes; Forming an internal electrode for mounting an element and a conductor line connecting the internal electrode and the internal conductor path in the through-hole on the surface on the side where the element is mounted in the region; the side opposite to the side where the element is mounted in each substrate region Forming external electrodes that are electrically connected to the conductor paths in the through-holes on the surface of the substrate; a shape that forms a space large enough to accommodate the element when it is brought into close contact with the substrate surface in each substrate region And providing a cap member having a height; and in each substrate region, at least an end surface of the cap member between the internal electrode and an edge of the substrate region. A step of printing and curing an organic polymer material layer to a suitable shape or providing an inorganic material layer as a sealing auxiliary layer; in each substrate region, a high-frequency element is mounted and electrically connected to the internal electrode. After the connection, a step of bonding the cap member to the sealing auxiliary layer with an adhesive to hermetically seal; and a step of dividing the substrate along the dividing line. Packaging method.
2 2 . 接着工程に先立ち、 前記有機高分子材料硬化層または無機材料層の 表面を紫外線照射またはプラズマ処理により活性化する工程をさらに含む請 求の範囲第 2 1項に記載の高周波素子のパッケージング方法。  22. The high frequency element package according to claim 21, further comprising a step of activating the surface of the cured organic polymer material layer or the inorganic material layer by ultraviolet irradiation or plasma treatment prior to the bonding step. Method.
2 3 . 前記分割前のいずれかの段階において、 各基板領域の電気的特性を 検査する工程をさらに含む請求の範囲第 2 1項または第 2 2項に記載の高周 波素子のパッケージング方法。  23. The packaging method for a high-frequency device according to claim 21 or 22, further comprising a step of inspecting electrical characteristics of each substrate region at any stage before the division. .
2 4 . 前記検査が半導体検査用のゥエーハプローバを用いて行われる請求 の範囲第 2 3項に記載の高周波素子のパッケージング方法。  24. The packaging method for a high-frequency device according to claim 23, wherein the inspection is performed using a semiconductor probe A prober.
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