JP2001102469A - Package for semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package for a semiconductor element wherein the size and the weight can be reduced, and a metal lid can be airtightly and stiffly bonded to the insulation substrate. SOLUTION: A package A for a semiconductor element is provided with an insulation substrate 1 having a surface on which a semiconductor element 2 is mounted, and a metal lid 5 which is bonded with solder 10 in order to airtightly seal the semiconductor element 2 on the surface of the insulation substrate 1. In the package A, a ground layer 6 is stuck and formed at least on the surface of the insulation substrate 1 on which the metal lid 5 is bonded. A pair of frame walls 8, 9 which are composed of insulation material and prevent solder material 10 from flowing out are stuck on the surface of the ground layer 6. The ground layer 6 is bonded to the metal lid 5 with solder 10 at a part sandwiched between a part of the walls 8 and 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package in which a semiconductor device is mounted and the semiconductor device is hermetically sealed with a metal cover, and more particularly to an improvement in a package structure.

[0002]

2. Description of the Related Art Conventionally, there has been known a package for housing a semiconductor element on which a semiconductor element is mounted. In particular, since a high-frequency element storage package for mounting a high-frequency element used in a high frequency band is required to have good signal transmission characteristics at high frequencies and hermetic sealing properties, a conventionally known metal wall package is used. Has been used.

However, since the metal wall package is heavy and is not suitable for small size and light weight, low loss metal such as Cu having a small transmission loss in a frequency band of 1 to 30 GHz is used in a field where small size and light weight such as communication is particularly required. Glass ceramic packages having wiring as high frequency wiring are being used.

Conventionally, the structure of a package for accommodating a semiconductor element is, as shown in FIG. 4, for example, provided with a recess 44 for accommodating a semiconductor element 43 in an insulating substrate 42 composed of a multi-layered insulating layer 41 and a semiconductor. The concave portion 44 is hermetically sealed with a metal lid 45 via a brazing material 47 formed on the conductor layer 46 for electromagnetic shielding from the outside of the element 43. Further, for example, a high-frequency signal line such as a microstrip line or a grounded coplanar line including a center conductor 48 in an insulating substrate 42 and ground layers 50 and 51 covering the upper and lower surfaces of the center conductor 48 via the insulating layer 41. Is formed and connected to the semiconductor element 43 by a metal wire, a ribbon, a lead, a TAB tape 49 or the like.
The center conductor 50 is connected to the connection terminal 55 via the via hole conductor 53 and the like, and further connected to an external circuit board (not shown) and the like.

In Japanese Patent Application Laid-Open No. 4-206854, a frame-shaped conductor layer is formed on the surface of an insulating substrate so as to cover the entire periphery of the element, and a metal lid is adhered to the conductor layer.
It has been proposed that the influence of electromagnetic waves from outside the semiconductor element can be prevented by electrically connecting the metal lid and the ground layer on the lower surface of the high-frequency signal line with a large number of through holes.

[0006]

However, in the above-described conventional package for housing a semiconductor element, one or more insulating layers must be further provided on the upper surface of the ground layer on the upper surface, so that the number of manufacturing steps is increased and the package size is increased. It was disadvantageous in terms of miniaturization.

In Japanese Patent Application Laid-Open No. Hei 4-206854, it is possible to prevent the influence of an external electromagnetic wave on a semiconductor element, but to prevent the influence of an external electromagnetic wave on a signal line connected to the semiconductor element. However, there is a problem that transmission loss increases in the signal line.

Further, in any package, the brazing material can be arranged and fixed at a predetermined position by brazing via a conductor layer having a predetermined shape provided on the surface of the insulating substrate. When directly brazing to a conductor layer with a large area such as a ground layer, the brazing material spreads out on the surface of the conductor layer and flows out. There was a problem that the strength was reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device housing package which can solve the above problems and which can be reduced in size and weight, and which can tightly and tightly join a metal lid to an insulating substrate.

[0010]

Means for Solving the Problems As a result of studying the above problems, the present inventors have found that an insulating substrate having a surface on which a semiconductor element is mounted, and a method for hermetically sealing the semiconductor element on the surface of the insulating substrate. A ground layer is formed on at least a surface of the insulating substrate of the semiconductor device housing package having a metal lid joined with a brazing material to join the metal lid, and a ground layer is formed on the surface of the ground layer. By attaching a pair of brazing material outflow preventing walls made of an insulator, and joining the ground layer and the lid with a brazing material at a portion sandwiched between the pair of brazing material outflow preventing walls, the conventional ground layer has an upper surface. The insulating layer that had been arranged can be omitted,
It has been found that the package can be miniaturized, and since the brazing material does not flow out onto the surface of the ground layer, it has good hermetic sealing properties and can be brazed with high adhesive strength.

In this case, the brazing material outflow preventing wall is formed by simultaneous firing with the insulating substrate and the ground layer, the brazing material outflow preventing wall is made of the same component as the insulating substrate, The height of the outflow prevention wall is 3
It is preferable that the width is 0.1 to 5 mm and the interval between the pair of brazing material outflow prevention walls is 0.2 to 5 mm.

Preferably, at least a center conductor is formed inside the insulating substrate opposed to the ground layer, and at least a Ni, Co having a thickness of 1 to 20 μm is formed on a surface of the ground layer to be brazed to the lid. , Cr,
It is desirable to form a plating layer made of at least one metal selected from the group consisting of Au and Cu.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a package for accommodating a semiconductor device according to the present invention will be described with reference to FIG. 1 which is a schematic sectional view and FIG. 2 which is a plan view without a metal cover. According to the semiconductor device housing package A of FIG. 1, the multilayer insulating layer 1a
A concave portion 3 for accommodating the semiconductor element 2 is formed substantially at the center of the upper surface of the insulating substrate 1 composed of the substrate 1a to 1c, and the semiconductor element 2 mounted in the concave portion 3 of the insulating substrate 1 is hermetically closed by the metal lid 5. It is sealed.

The insulating layers 1a to 1c are made of alumina, silicon nitride, aluminum nitride, glass ceramics or the like, but are preferably made of glass ceramics which can be co-fired with a low-resistance metal such as copper or silver, which will be described later.

The metal lid 5 is made of, for example, a metal such as Kovar, 42 alloy, or copper, and can prevent the influence of external electromagnetic waves on the semiconductor element 2 mounted in the recess 3. . The coefficient of thermal expansion of the metal lid 3 is such that stress generated due to a difference in thermal expansion between the insulating substrate 1 and the metal lid 5 when the metal lid 5 is connected is avoided, and the hermetic sealing reliability of the package is improved. In order to increase the thermal expansion coefficient, it is desirable that the thermal expansion coefficient be close to the thermal expansion coefficient of the insulating substrate 1.

Further, according to the present invention, a ground layer 6 is formed around the concave portion 3 on the surface of the insulating substrate 1, and a pair of frame-shaped brazing material outflows covers the concave portion 3 on the surface of the ground layer 6. Prevention walls 8 and 9 are formed, and a portion sandwiched between the brazing material outflow prevention walls 8 and 9 is filled with the brazing material 10 so that the ground layer 6 and the metal lid 5 are interposed through the brazing material 10. And the inside of the concave portion 3 can be hermetically sealed, and high adhesive strength can be maintained.

In such a structure, the brazing material outflow preventing walls 8 and 9 are desirably made of ceramics integrally formed by simultaneous firing with the insulating substrate 1 and the ground layer 6 from the viewpoint of increasing the bonding strength. It is desirable that the material outflow prevention walls 8 and 9 have the same composition or the same components as the insulating substrate 1.

Further, the shapes of the brazing material outflow prevention walls 8 and 9 are as follows.
The amount of brazing material necessary for hermetic sealing can be filled between the brazing material outflow prevention walls 8 and 9, the strength at the brazing portion is increased, and stress is reduced due to a difference in thermal expansion between the brazing material 10 and the insulating substrate 1. In order to prevent the occurrence of cracks or the like due to stress concentration, the height is desirably 3 to 3000 μm, and the strength of the brazing material outflow prevention walls 8 and 9 can be maintained and formed with high accuracy. In order to reduce the size and weight of the package, the width of the brazing material outflow prevention walls 8 and 9 is preferably 0.1 to 5 mm.

In addition, the amount of brazing material necessary for hermetic sealing can be filled, and the brazing material sandwiched between the brazing material outflow prevention walls 8 and 9 in order to maintain strong adhesion between the insulating substrate 1 and the ground layer 6. It is desirable that the width of the 10 filled portions is 0.2 to 5 mm.

A central conductor layer 12 is formed in the insulating substrate 1 at a position facing the ground layer 6 with the insulating layer 1a interposed therebetween, in parallel with the ground layer 6, and one end thereof is
It is electrically connected to the semiconductor element 2 via a metal wire, a ribbon, a lead, a TAB tape 14 and the like. Further, at a position facing the center conductor layer 12, the ground layer 1 extends to the lower surface of the semiconductor element 2 via the insulating layer 1b.
6 are formed.

Here, the line 18 having a strip structure is formed by the center conductor layer 12 and the ground layers 6 and 16, whereby the influence of external electromagnetic waves on the line 18 can be prevented. The line 18 may be provided with a pair of ground layers (not shown) on both sides of the center conductor layer 12 forming surface with the center conductor layer 12 interposed therebetween, and the center conductor layer 12 may have a coplanar structure. A microstrip line without the layer 16 may be used.

The center conductor layer 12 is electrically connected to connection terminals 22 formed on the back surface of the insulating substrate 1 via the through-hole conductors 20, and is connected to an external circuit board (not shown).
Connected to

The conductor layers such as the ground layers 6 and 16, the center conductor layer 12, the through-hole conductor 20, and the connection terminal 22 are made of a metal such as copper, silver, gold, tungsten, and molybdenum. Is desirably made of a low-resistance metal such as copper or silver. The conductor layer may contain a filler component such as ceramics and glass.

In the insulating substrate 1, a line other than the line 18 structure, a thermal via, or the like may be formed, and further, the semiconductor element 2 between the ground layers 6, 16 and / or the center conductor layer 12 are surrounded. A large number of through holes can be formed at positions to further prevent the influence of external electromagnetic waves.

As shown in an enlarged view of the vicinity of the formation portions of the brazing material outflow preventing walls 8 and 9 in FIG. 3, the portion of the surface of the ground layer 6 sandwiched between the brazing material outflow preventing walls 8 and 9 has a thickness of 1 mm. ~
It is desirable to form a plating layer 24 having a thickness of 20 μm, thereby preventing the reaction between the brazing material 10 and the ground layer 6 from forming a low-strength reaction layer.
Can be increased in bonding strength to the ground layer 6. Further, by applying gold plating to the surface of the plating layer 24, the wettability between the plating layer 24 and the brazing material 4 can be enhanced.

Although the package A shown in FIG. 1 is provided with the concave portion 3 in the insulating substrate 1 and the concave portion 3 is sealed by the flat metal lid 5, the present invention is not limited to this. Instead, a semiconductor element may be mounted at a predetermined position on a flat insulating substrate, and the semiconductor element may be sealed with the insulating substrate and a bowl-shaped metal lid.

Next, an example of a method for manufacturing the semiconductor device housing package of the present invention will be described. First, a slurry is prepared by mixing an organic binder and a solvent with ceramic powder, and the slurry is used to form a green sheet by a well-known doctor blade method, a rolling method, or the like. Then, via holes or through holes are formed at predetermined positions of the green sheet.

For example, when glass ceramic is used as the insulating layer, calcium zirconate, strontium silicate, calcium titanate, strontium titanate, barium titanate, alumina, silica, mullite,
A crystalline glass that precipitates a crystalline phase by firing is added to ceramic powders such as forsterite, zirconia, and spinel, and, if desired, heat in a nitrogen atmosphere of an acrylic resin such as methyl methacrylate or isobutyl methacrylate. Organic binder and I excellent in decomposability
It is desirable to add a solvent such as PA and toluene.

On the other hand, fillers such as glass and ceramic powders and organic substances may be added to metal powders such as copper, silver, gold, tungsten and molybdenum, if desired, in terms of controlling the sintering temperature and the shrinkage rate and the coefficient of thermal expansion by sintering. Components are added and kneaded to prepare a conductive paste, the conductive paste is filled in via holes or through holes formed in the green sheet, and the conductive paste is screen-printed at a predetermined position on the surface of the green sheet. Printing is performed by a known printing method such as the above method to form a conductor layer having a thickness of 10 to 30 μm.

The green sheet on which the ground layer serving as the surface of the insulating substrate is formed may be provided with a slurry on which the green sheet is formed or a metal powder and a ceramic powder at a position where the green sheet is bonded to the metal lid. Using a paste obtained by adding and kneading theopineol or the like to at least one selected from the binders and using a kneaded paste, a pair of brazing material outflow preventing wall molded bodies having a predetermined shape is formed by a known printing method such as a screen printing method.

Then, these printed green sheets are aligned, laminated, and pressed. The formation of the brazing material outflow preventing wall molded body may be performed after the green sheets are laminated.

Next, after the above-mentioned laminate is subjected to a binder removal treatment, the laminate is baked in a nitrogen atmosphere at a temperature of 900 to 1050 ° C., thereby producing an insulating substrate having a pair of brazing material outflow preventing walls. Can be.

Then, a plating layer made of at least one of Ni, Co, Cr, Au and Cu is formed in a frame portion between the pair of brazing material outflow prevention walls of the obtained insulating substrate by an electrolytic plating method, 1 ~ 20μ thickness by plating method
m, and more desirably, a plating layer made of Au is applied by the same method.

Then, the semiconductor element is mounted at a predetermined position on the insulating substrate, and electrically connected to the central conductor layer via a wire by a wire bonding method or the like, and then a plating layer is formed between the pair of brazing material outflow prevention walls. By brazing a brazing material to the surface of the part with an Au-Sn alloy, solder, or the like at 150 to 400 ° C, the semiconductor element housing package of the present invention in which the semiconductor element is hermetically sealed can be obtained.

[0035]

Examples: SiO ₂ : 44% by weight, Al ₂ O ₃ : 28% by weight, MgO: 11% by weight, ZnO: 8% by weight, B ₂ O
₃ : 64% by weight of crystalline glass powder having a composition of 9% by weight, 5% by weight of calcium zirconate, 14% by weight of silica, and strontium silicate 17 as ceramic filler
12 parts by weight of isobutyl methacrylate resin as an organic binder and 6 parts by weight of dibutyl phthalate as a plasticizer are added to 100 parts by weight of the glass ceramic raw material powder of 100% by weight, and 40 parts by a ball mill using toluene as a solvent. A slurry was prepared by mixing for a time, and formed into a green sheet having a thickness of 0.25 mm by a doctor blade method.

On the other hand, 100 parts by weight of copper powder and a softening point of 80
2 parts by weight of zinc borosilicate glass at 0 ° C., 3 parts by weight of isobutyl methacrylate, 5 parts by weight of dibutyl phthalate, and 10 parts by weight of terpionel were kneaded to prepare a conductive paste for forming a conductive layer. Then, three green sheets described above were prepared, holes were formed in predetermined positions, the above-described conductive paste was filled into the through holes by printing, and a predetermined conductive layer was formed.

The above-mentioned glass ceramic composition 10
0 parts by weight, 5 parts by weight of isobutyl methacrylate, 13 parts by weight of dibutyl phthalate, and 38 parts by weight of terpionel are mixed to form a paste for a brazing material outflow preventing wall, and the ground layer disposed on the surface of the insulating substrate is A pair of brazing material outflow preventing wall molded bodies are formed on the surface of the formed green sheet by screen printing so that the shape of the brazing material outflow preventing wall after firing is as shown in Table 1, and these green sheets are aligned. Then, they were pressed and pressed under a pressure of 50 kg / cm ² .

Thereafter, this laminate was subjected to a heat treatment at 750 ° C. for 3 hours in a nitrogen atmosphere containing steam to reduce the residual carbon content in the compact to 200 ppm or less.
C. for 1 hour to obtain a glass-ceramic insulating substrate 1 having a copper conductor layer and an outer dimension of 30.times.40 mm.

Then, the surface of the ground layer between the pair of brazing material outflow prevention walls is formed by electroless plating to have a thickness of N shown in Table 1.
After forming the i-th plating layer and the 0.2 μm-thick gold plating layer, the semiconductor element was mounted at a predetermined position on the surface of the insulating substrate, and a 20 × 25 × 0.5 mm metal lid made of 42 alloy was joined thereto, The surface of the gold plating layer was filled with a brazing material made of an Au-Sn alloy by brazing at 250 ° C. to hermetically seal the semiconductor element.

The sample prepared as described above was held at -65 ° C. for 5 minutes, and held at 150 ° C. for 5 minutes as one cycle, with a maximum of 5 cycles.
A thermal shock test was performed up to 00 cycles, and the number of cycles in which the hermetic sealing property was impaired was measured.

Note that the hermetic sealing property is based on MIL-STD88.
Evaluation was carried out according to the method 3 (sealing). Specifically, the sample was held for 2 hours in a He pressurized atmosphere of 4.2 kgf / cm ² , taken out, and the amount of He gas detected in a vacuum atmosphere was measured. A fine leak test and a gross leak test using fluorocarbon to be measured were performed, and when either one did not satisfy the acceptance criteria, the number of cycles was described in Table 1 assuming that the hermetic sealing property was impaired. In addition, the samples whose hermetic sealing properties were impaired in less than 500 cycles were observed with a microscope, and the causes are shown in Table 1.

[0042]

[Table 1]

As is clear from Table 1, the sample No. having no wall for preventing the brazing material from flowing out was formed. In No. 1, the brazing material flowed off during brazing, and the package could not be hermetically sealed.

On the other hand, the sample No. having the wall for preventing the brazing material from flowing out according to the present invention was prepared. In Nos. 2 to 24, good brazing was possible, and no problems such as cracks were observed 200 times or more in the thermal shock test. Above all, the height of the brazing material flow prevention wall is 3 to 3000 μm, and the width is 0.1 to
10mm, spacing between brazing material loss prevention walls 0.2-5m
m, sample N having a plating layer thickness of 1 to 20 μm
o. In 4, 5, 9 to 13, 15 to 18, and 20 to 22,
No problems such as cracks were observed 500 times or more in the thermal shock test.

[0045]

As described in detail above, according to the present invention,
Form a ground layer on the surface where the lid of the insulating substrate is joined,
By omitting the insulating layer on the upper surface of the ground layer, which has been conventionally formed, the package can be reduced in size and weight. In addition, since a predetermined shape can be brazed in a desired shape, strong brazing can be performed, the package can be hermetically sealed, and a semiconductor element and a center connected to the semiconductor element are connected by a ground layer and a metal lid. The effect of electromagnetic waves from the outside on the conductor can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an example of a package for housing a semiconductor element according to the present invention.

FIG. 2 is a plan view of the package of FIG. 1 from which a metal lid is omitted.

FIG. 3 is an enlarged cross-sectional view of a joint between a metal lid 3 and a ground layer 6 in the package of FIG.

FIG. 4 is a schematic sectional view showing an example of a conventional package for housing a semiconductor element.

[Explanation of symbols]

 A Package for storing semiconductor element 1 Insulating substrate 1a to 1c Insulating layer 2 Semiconductor element 3 Concave part 5 Metal lid 6, 16 Ground layer 8, 9 Soldering material prevention layer 10 Soldering material 12 Central conductor layer 14 Wire 18 Line 20 Through Hall conductor 22 Connection terminal

Claims (6)

[Claims] 1. A semiconductor comprising: an insulating substrate having a surface on which a semiconductor element is mounted; and a metal lid joined to the insulating substrate surface by a brazing material to hermetically seal the semiconductor element. An element storage package, wherein a ground layer is formed on at least a surface of the insulating substrate to which the metal lid is joined, and a pair of brazing material outflow prevention walls made of an insulator is formed on the ground layer surface. Wherein the ground layer and the lid are joined by a brazing material at a portion sandwiched between the pair of brazing material outflow preventing walls. 2. The package for accommodating a semiconductor element according to claim 1, wherein said brazing material outflow preventing wall is formed by simultaneous firing with said insulating substrate and said ground layer. 3. The package for accommodating a semiconductor element according to claim 1, wherein the brazing material outflow prevention wall is made of the same component as the insulating substrate. 4. The height of the brazing material outflow preventing wall is 3 to 300.
4. The semiconductor device housing according to claim 1, wherein the width is 0.1 to 10 mm, and the interval between the pair of brazing material outflow prevention walls is 0.2 to 5 mm. For package. 5. A center conductor is formed inside an insulating substrate facing the ground layer.
5. The package for accommodating a semiconductor element according to any one of items 4 to 4. 6. Ni, Co, Cr, A having a thickness of 1 to 20 μm on at least the surface of a ground layer brazed to the lid.
6. The package for housing a semiconductor element according to claim 1, wherein a plating layer made of at least one metal selected from the group consisting of u and Cu is formed.