JP3618063B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements Download PDF

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Publication number
JP3618063B2
JP3618063B2 JP27687099A JP27687099A JP3618063B2 JP 3618063 B2 JP3618063 B2 JP 3618063B2 JP 27687099 A JP27687099 A JP 27687099A JP 27687099 A JP27687099 A JP 27687099A JP 3618063 B2 JP3618063 B2 JP 3618063B2
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semiconductor element
brazing material
package
insulating substrate
layer
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JP2001102469A (en
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俊昭 重岡
智 濱野
正浩 冨迫
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子が搭載され、半導体素子を金属製蓋体によって気密に封止する半導体素子収納用パッケージに関し、特に、パッケージ構造の改良に関するものである。
【０００２】
【従来技術】
従来から、半導体素子を搭載した半導体素子収納用パッケージが知られている。特に、高い周波数帯で使用される高周波素子などを搭載する高周波素子収納用パッケージには、高周波での良好な信号伝送特性及び気密封止性が要求されることから、従来より周知のメタルウォールパッケージが使用されてきた。
【０００３】
しかし、メタルウォールパッケージは重く、小型軽量に不向きであることから、通信などの小型軽量が特に要求される分野では、１〜３０ＧＨｚの周波数帯で伝送損失の小さいＣｕ等の低損失金属配線を高周波用配線として具備するガラスセラミックパッケージが使用されつつある。
【０００４】
従来、半導体素子収納用のパッケージの構造は、例えば図４に示すように、多層の絶縁層４１からなる絶縁基板４２内に半導体素子４３を収納するための凹部４４を設けるとともに、半導体素子４３の外部からの電磁的遮蔽のため凹部４４を金属製の蓋体４５にて導体層４６上に被着形成されたロウ材４７を介して気密に封止される。また、例えば、絶縁基板４２内に中心導体４８と、絶縁層４１を介して中心導体４８の上下面を覆うグランド層５０、５１と、からなるマイクロストリップ線路やグランド付コプレーナ線路等の高周波信号線路が形成され、金属製ワイヤ、リボン、リード、ＴＡＢテープ４９等によって半導体素子４３と接続されている。なお、中心導体５０はビアホール導体５３等を経由して接続用端子５５に接続され、さらに外部回路基板（図示せず。）等と接続される。
【０００５】
また、特開平４−２０６８５４号では、絶縁基板表面に素子の全周を覆うように枠状の導体層を形成し、この導体層に金属製の蓋体を接着するとともに、金属製蓋体と高周波信号線路下面のグランド層とを多数のスルーホールによって電気的に接続することによって、半導体素子の外部からの電磁波の影響を防止できることが提案されている。
【０００６】
【発明が解決しようとする課題】
しかしながら、前述した従来の半導体素子収納用パッケージでは、上面のグランド層の上面に絶縁層をさらに１層以上設けなければならず、製造工程が増すとともに、パッケージの小型化の点で不利であった。
【０００７】
また、特開平４−２０６８５４号では、外部からの電磁波の半導体素子への影響を防止することはできるものの、半導体素子と接続された信号線路への外部からの電磁波の影響を防止することができず、信号線路にて伝送損失が増大するという問題があった。
【０００８】
さらに、いずれのパッケージにおいても絶縁基板表面に設けられた所定の形状からなる導体層を介してロウ付けすることにより所定の位置にロウ材を配設、固定することができるものであり、グランド層等の面積の広い導体層に直接ロウ付けすると、ロウ材が導体層表面に広がって流出してしまい、過剰なロウ材が必要となるばかりか導体層と金属製蓋体との接合強度が低下するという問題があった。
【０００９】
本発明は上記問題点を解決するもので、小型軽量化できるとともに、金属製蓋体を絶縁基板に気密かつ強固に接合可能な半導体素子収納用パッケージを提供することを目的とする。
【００１０】
【課題を解決するための手段】
本発明者らは、上記課題について検討した結果、半導体素子が搭載される表面を有する絶縁基板と、該絶縁基板表面に前記半導体素子を気密に封止するためにロウ材によって接合される金属製蓋体とを具備する半導体素子収納用パッケージの前記絶縁基板の少なくとも前記金属製蓋体を接合する表面にグランド層を、前記絶縁基板内部に中心導体層とを形成してストリップ構造の線路を具備してなるとともに、前記グランド層表面に絶縁体からなる一対のロウ材流出防止壁を被着し、前記ロウ材流出防止壁の高さを３〜３０００μｍ、幅を０．１〜１０ｍｍ、かつ前記一対のロウ材流出防止壁間の間隔を０．２〜５ｍｍとし、前記一対のロウ材流出防止壁に挟まれた部分でグランド層と蓋体とをロウ材によって接合することによって、従来グランド層上面に配設していた絶縁層を省くことができ、パッケージの小型化が可能であるとともに、ロウ材がグランド層表面上に流出することないために、気密封止性がよく、高い接着強度でロウ付けできることを知見した。
【００１１】
ここで、前記ロウ材流出防止壁が前記絶縁基板および前記グランド層と同時焼成によって形成されてなること、前記ロウ材流出防止壁が前記絶縁基板と同じ成分からなることが望ましい。
【００１２】
また、前記グランド層を対向する絶縁基板内部に少なくとも中心導体が形成されてなることが望ましく、さらに、少なくとも前記蓋体とロウ付けされるグランド層表面に厚み１〜２０μｍのＮｉ、Ｃｏ、Ｃｒ、ＡｕおよびＣｕの群から選ばれる少なくとも１種の金属からなるメッキ層を形成してなることが望ましい。
【００１３】
【発明の実施の形態】
本発明の半導体素子収納用パッケージの一例を概略断面図である図１および金属製蓋体を省略した平面図である図２を基に説明する。
図１の半導体素子収納用パッケージＡによれば、多層の絶縁層１ａ〜１ｃからなる絶縁基板１の上面略中央部に半導体素子２を収容するための凹部３が形成され、絶縁基板１の凹部３に搭載された半導体素子２は金属製蓋体５をによって気密に封止されている。
【００１４】
絶縁層１ａ〜１ｃは、アルミナ、窒化ケイ素、窒化アルミニウム、ガラスセラミックス等からなるが、後述する低抵抗金属の銅または銀等との同時焼成が可能なガラスセラミックスからなることが望ましい。
【００１５】
また、金属製蓋体５は、例えば、コバール、４２アロイ、銅等の金属からなり、凹部３内に搭載される半導体素子２への外部からの電磁波の影響を防止することができる。なお、金属製蓋体３の熱膨張係数は、金属製蓋体５接続時に絶縁基板１と金属製蓋体５との熱膨張差により発生する応力発生を避け、パッケージの気密封止信頼性を高める上で、絶縁基板１の熱膨張係数と近似していることが望ましい。
【００１６】
また、本発明によれば、絶縁基板１表面の凹部３の周囲部にはグランド層６が形成され、グランド層６表面には凹部３を覆うように一対の枠状のロウ材流出防止壁８、９が形成されており、両ロウ材流出防止壁８、９に挟まれた部分にロウ材１０を充填することによって、グランド層６と金属製蓋体５がロウ材１０を介して電気的に接続され、凹部３内を気密に封止できるとともに、高接着強度を維持できる。
【００１７】
かかる構造において、ロウ材流出防止壁８、９は、絶縁基板１およびグランド層６と同時焼成によって一体的に形成されたセラミックスからなることが接合強度を高める点で望ましく、また、ロウ材流出防止壁８、９は絶縁基板１と同一組成もしくは同一成分からなることが望ましい。
【００１８】
さらにロウ材流出防止壁８、９の形状は、気密封止に必要なロウ材量をロウ材流出防止壁８、９間に充填できるとともに、ロウ付け部での強度を高め、ロウ材１０と絶縁基板１との間で熱膨張差によって応力が発生し、応力集中によってクラック等が生じることを防止するために、高さが３〜３０００μm であることが必要であり、また、ロウ材流出防止壁８、９の強度を維持し、精度良く形成できるとともに、パッケージの小型化、軽量化のために、ロウ材流出防止壁８、９の幅が０．１〜５ｍｍであることが必要である。
【００１９】
また、気密封止に必要なロウ材量を充填できるとともに、絶縁基板１とグランド層６との強固な接着を維持するためにロウ材流出防止壁８、９によって挟まれたロウ材１０充填部の幅は０．２〜５ｍｍであることが必要である。
【００２０】
また、絶縁基板１内の絶縁層１ａを介してグランド層６と対向する位置にはこのグランド層６と平行して中心導体層１２が形成されており、その一端は、金属製ワイヤ、リボン、リード、ＴＡＢテープ１４等を介して半導体素子２と電気的に接続されている。さらに、中心導体層１２と対向する位置には、絶縁層１ｂを介して半導体素子２の下面にまでわたってグランド層１６が形成されている。
【００２１】
ここで、中心導体層１２およびグランド層６、１６によってストリップ構造の線路１８が形成され、これによって、線路１８への外部からの電磁波の影響を防止できる。なお、線路１８は、中心導体層１２形成面の中心導体層１２を挟んで対峙する両側に一対のグランド層（図示せず。）を設け、中心導体層１２をコプレーナ構造としてもよく、またはグランド層１６を形成しないマイクロストリップ線路であってもよい。
【００２２】
また、中心導体層１２は、スルーホール導体２０を経由して絶縁基板１の裏面に形成された接続端子２２に電気的に接続され、外部回路基板（図示せず）と接続される。
【００２３】
なお、上記グランド層６、１６、中心導体層１２、スルーホール導体２０、接続端子２２等の導体層は、銅、銀、金、タングステン、モリブデン等の金属からなるが、特に高周波信号を伝送する線路については、低抵抗金属である銅または銀からなることが望ましい。また、導体層内には、セラミックスやガラス等のフィラー成分を含有してもよい。
【００２４】
また、絶縁基板１内には、線路１８構造以外の線路やサーマルビア等が形成されてもよく、さらに、グランド層６、１６間の半導体素子２および／または中心導体層１２を囲む位置に多数のスルーホールを形成して外部からの電磁波の影響をさらに防止することもできる。
【００２５】
また、図３のロウ材流出防止壁８、９形成部付近の拡大図に示されるとおり、グランド層６表面の両ロウ材流出防止壁８、９に挟まれた部分には厚み１〜２０μｍ のメッキ層２４を形成することが望ましく、これによってロウ材１０とグランド層６との反応により強度の低い反応層が形成されることを防止し、ロウ材１０のグランド層６への接着強度を高めることができる。さらに、メッキ層２４表面に金メッキを施すことに、メッキ層２４とロウ材４との濡れ性を高めることができる。
【００２６】
なお、図１のパッケージＡは絶縁基板１に凹部３を設け、凹部３を平板状の金属製蓋体５によって封止するものであったが、本発明はこれに限られるものではなく、平板形状の絶縁基板の所定位置に半導体素子を搭載し、該半導体素子を前記絶縁基板と椀状の金属製蓋体によって封止する構造であってもよい。
【００２７】
次に、本発明の半導体素子収納用パッケージの製造方法の一例について説明する。
まず、セラミックス粉末に有機バインダおよび溶剤を混合してスラリーを調製し、このスラリーを用いて、周知のドクターブレード法、圧延法等によって、シート状に成形してグリーンシートを作製する。そして、このグリーンシートの所定の位置にビアホールまたはスルーホールを形成する。
【００２８】
例えば、絶縁層としてガラスセラミックスを使用した場合、ジルコン酸カルシウム、珪酸ストロンチウム、チタン酸カルシウム、チタン酸ストロンチウム、チタン酸バリウム、アルミナ、シリカ、ムライト、フォルステライト、ジルコニア、スピネル等のセラミックス粉末に焼成によって結晶相を析出する結晶性ガラスを添加し、さらに、所望により、アクリル系樹脂、例えばメタクリル酸メチル、メタクリル酸イソブチル等の窒素雰囲気中での熱分解性に優れた有機バインダおよびＩＰＡ、トルエン等の溶剤を添加することが望ましい。
【００２９】
一方、銅、銀、金、タングステン、モリブデン等の金属粉末に、焼結温度および焼成による収縮率、熱膨張係数の制御の点で、所望により、ガラスやセラミック粉末等のフィラーおよび有機物成分を添加、混練して導電性ペーストを作製し、前記グリーンシートに形成したビアホールまたはスルーホール内に前記導体ペーストを充填し、さらに前記グリーンシート表面の所定の位置に上記導体ペーストをスクリーン印刷法等の公知の印刷法により印刷して、厚み１０〜３０μｍの導体層を形成する。
【００３０】
また、絶縁基板表面となるグランド層を形成した前記グリーンシートには、金属製蓋体と接合する位置に、前記グリーンシートを形成したスラリー、もしくは前記金属粉末と前記セラミック粉末に対して前記バインダから選ばれる少なくとも１種にテオピネオール等を添加、混練したペーストを用いてスクリーン印刷法等の公知の印刷法により、所定形状の一対のロウ材流出防止壁用成形体を形成する。
【００３１】
そして、これらの印刷したグリーンシートの位置を合わせて、積層し圧着する。なお、ロウ材流出防止壁用成形体の形成は、グリーンシート積層後であってもよい。
【００３２】
次に、上記積層体を脱バインダ処理した後、例えば、窒素雰囲気中、９００〜１０５０℃の温度で焼成することにより、一対のロウ材流出防止壁を具備した絶縁基板を作製することができる。
【００３３】
そして、得られた絶縁基板の一対のロウ材流出防止壁間の枠状部内にＮｉ、Ｃｏ、Ｃｒ、ＡｕおよびＣｕのうち少なくとも１種からなるメッキ層を、電解メッキ法、無電解メッキ法等により、厚みが１〜２０μｍとなるように形成し、さらに望ましくは、同じ手法により、Ａｕからなるメッキ層を施す。
【００３４】
そして、絶縁基板の所定の位置に半導体素子を実装し、ワイヤボンディング法などにより中心導体層とワイヤを介して電気的に接続した後、一対のロウ材流出防止壁間のメッキ層形成部表面にＡｕ−Ｓｎ合金や半田等によってロウ材を１５０〜４００℃にてロウ付けすることにより、半導体素子が気密に封止された本発明の半導体素子収納用パッケージを得ることができる。
【００３５】
【実施例】
ＳｉＯ２ ：４４重量％、Ａｌ２ Ｏ３ ：２８重量％、ＭｇＯ：１１重量％、ＺｎＯ：８重量％、Ｂ２ Ｏ３ ：９重量％の組成を有する結晶性ガラス粉末６４重量％と、セラミックフィラーとしてジルコン酸カルシウム５重量％、シリカ１４重量％、珪酸ストロンチウム１７重量％からなるガラスセラミック原料粉末１００重量部に対して、有機バインダとしてメタクリル酸イソブチル樹脂を固形分で１２重量部、可塑剤としてフタル酸ジブチルを６重量部添加し、トルエンを溶媒としてボールミルにより４０時間混合しスラリーを調製し、ドクターブレード法により厚み０．２５ｍｍのグリーンシートに成形した。
【００３６】
一方、銅粉末１００重量部と、軟化点８００℃のホウケイ酸亜鉛ガラス２重量部、メタクリル酸イソブチル３重量部、フタル酸ジブチル５重量部、テルピオネール１０重量部を混練して導体層形成用の導体ペーストを作製した。そして、前述のグリーンシートを３枚数用意し、所定の位置に穴加工を行い、前述の導体ペーストを印刷によってスルーホール内に充填するとともに、所定の導体層を成形した。
【００３７】
また、上述のガラスセラミック組成物１００重量部に、メタクリル酸イソブチル５重量部、フタル酸ジブチル１３重量部、テルピオネール３８重量部を混合してロウ材流出防止壁用ペーストを形成し、絶縁基板表面に配設されるグランド層を形成したグリーンシート表面にスクリーン印刷によって、焼成後のロウ材流出防止壁の形状が表１となるように一対のロウ材流出防止壁成形体を被着形成し、これらのグリーンシートを位置合わせして積層し、５０ｋｇ／ｃｍ２ の圧力で加圧し圧着した。
【００３８】
その後、この積層体を水蒸気を含んだ窒素雰囲気中、７５０℃、３時間の熱処理を行い、成形体中の残留炭素量を２００ｐｐｍ以下に低減した後、９３０℃で１時間の焼成を行い、銅導体層を施した外形寸法が３０×４０ｍｍのガラスセラミックスの絶縁基板１を得た。
【００３９】
そして、一対のロウ材流出防止壁間のグランド層表面に無電解メッキによって表１に示す厚みのＮｉのメッキ層および厚み０．２μｍ金メッキ層を形成した後、半導体素子を絶縁基板表面の所定の位置に実装し、４２アロイからなる２０×２５×０．５ｍｍの金属製蓋体を接合し、前記金メッキ層の表面にＡｕ−Ｓｎ合金からなるロウ材を２５０℃にてロウ付け充填して、半導体素子を気密に封止した。
【００４０】
上記のように作製した試料を−６５℃にて５分、１５０℃にて５分保持を１サイクルとして最高５００サイクルまでの熱衝撃試験を行い、気密封止性が損なわれたサイクル数を測定した。
【００４１】
なお、気密封止性は、ＭＩＬ−ＳＴＤ８８３の方法（封止）に準じて評価し、具体的には試料を４．２ｋｇｆ／ｃｍ２ のＨｅ加圧雰囲気中に２時間保持した後取り出し、真空雰囲気中で検出されるＨｅガス量を測定するファインリーク試験およびフロロカーボンによるグロスリーク試験を行いいずれか一方でも合格基準を満たさなかった場合に気密封止性が損なわれたとして表１にそのサイクル数を表記した。また５００サイクル未満で気密封止性が損なわれた試料については顕微鏡にて観察を行い、その原因を表１に示した。
【００４２】
【表１】

Figure 0003618063
【００４３】
表１から明らかなとおり、ロウ材流失防止壁を形成しない試料Ｎｏ．１では、ロウ付け時にロウ材が流失してパッケージを気密に封止することができなかった。
【００４４】
これに対し、本発明に従いロウ材流失防止壁を形成した試料Ｎｏ．２〜２４では、良好なロウ付けが可能であり、また、熱衝撃試験においても２００回以上クラック等の不具合はみられなかった。中でも、ロウ材流失防止壁の高さが３〜３０００μｍ、幅が０．１〜１０ｍｍ、ロウ材流失防止壁間の間隔が０．２〜５ｍｍ、メッキ層の厚みが１〜２０μｍを満足する試料Ｎｏ．４、５、９〜１３、１５〜１８、２０〜２２では、熱衝撃試験においても５００回以上クラック等の不具合はみられなかった。
【００４５】
【発明の効果】
以上詳述したように、本発明によれば、絶縁基板の蓋体を接合する表面にグランド層を形成し、従来形成していたグランド層上面の絶縁層を省いたことによってパッケージの小型、軽量化ができる。また、所定の位置に所望の形状でロウ付けができるために強固なロウ付けができ、パッケージを気密に封止することができるとともにグランド層と金属製蓋体とによって半導体素子とそれに接続した中心導体とを外部からの電磁波の影響を低減することができる。
【図面の簡単な説明】
【図１】本発明の半導体素子収納用パッケージの一例を示す概略断面図である。
【図２】図１のパッケージの金属製蓋体を省略した平面図である。
【図３】図１のパッケージにおける金属製蓋体３とグランド層６との接合部の拡大断面図である。
【図４】従来の半導体素子収納用パッケージの一例を示す概略断面図である。
【符号の説明】
Ａ 半導体素子収納用パッケージ
１ 絶縁基板
１ａ〜１ｃ 絶縁層
２ 半導体素子
３ 凹部
５ 金属製蓋体
６、１６ グランド層
８、９ ロウ材流失防止層
１０ ロウ材
１２ 中心導体層
１４ ワイヤ
１８ 線路
２０ スルーホール導体
２２ 接続端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a package for housing a semiconductor element in which a semiconductor element is mounted and the semiconductor element is hermetically sealed with a metal lid, and more particularly to an improvement in the package structure.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor element storage package on which a semiconductor element is mounted is known. In particular, a high-frequency element storage package mounting a high-frequency element used in a high frequency band is required to have good signal transmission characteristics and hermetic sealing at high frequencies. Has been used.
[0003]
However, since the metal wall package is heavy and unsuitable for small size and light weight, low loss metal wiring such as Cu having a low transmission loss in a frequency band of 1 to 30 GHz is used for high frequency in a field where small size and light weight such as communication is particularly required. A glass-ceramic package provided as a wiring for use is being used.
[0004]
Conventionally, as shown in FIG. 4, for example, a package structure for housing a semiconductor element is provided with a recess 44 for housing a semiconductor element 43 in an insulating substrate 42 formed of a multilayer insulating layer 41. The concave portion 44 is hermetically sealed through a brazing material 47 formed on the conductor layer 46 by a metal lid 45 for electromagnetic shielding from the outside. Further, for example, a high-frequency signal line such as a microstrip line or a grounded coplanar line comprising a central conductor 48 in the insulating substrate 42 and ground layers 50 and 51 covering the upper and lower surfaces of the central conductor 48 via the insulating layer 41. And is connected to the semiconductor element 43 by a metal wire, ribbon, lead, TAB tape 49 or the like. The center conductor 50 is connected to the connection terminal 55 via the via-hole conductor 53 and the like, and further connected to an external circuit board (not shown) and the like.
[0005]
In JP-A-4-206854, a frame-like conductor layer is formed on the surface of the insulating substrate so as to cover the entire circumference of the element, and a metal lid is bonded to the conductor layer. It has been proposed that the influence of electromagnetic waves from the outside of the semiconductor element can be prevented by electrically connecting the ground layer on the lower surface of the high-frequency signal line with a large number of through holes.
[0006]
[Problems to be solved by the invention]
However, in the conventional package for housing a semiconductor element described above, it is necessary to provide one or more insulating layers on the upper surface of the ground layer on the upper surface, which is disadvantageous in terms of an increase in manufacturing steps and miniaturization of the package. .
[0007]
Japanese Patent Laid-Open No. 4-206854 can prevent the influence of external electromagnetic waves on a semiconductor element, but can prevent the influence of external electromagnetic waves on a signal line connected to the semiconductor element. However, there was a problem that transmission loss increased in the signal line.
[0008]
Further, in any package, a brazing material can be disposed and fixed at a predetermined position by brazing via a conductor layer having a predetermined shape provided on the surface of the insulating substrate. When brazing directly to a conductor layer with a large area, etc., the brazing material spreads on the surface of the conductor layer and flows out, so that excessive brazing material is required and the bonding strength between the conductor layer and the metal lid decreases. There was a problem to do.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a package for housing a semiconductor element that can be reduced in size and weight, and can tightly and firmly bond a metal lid to an insulating substrate.
[0010]
[Means for Solving the Problems]
As a result of studying the above problems, the present inventors have found that an insulating substrate having a surface on which a semiconductor element is mounted and a metal bonded to the surface of the insulating substrate by a brazing material to hermetically seal the semiconductor element. A semiconductor element housing package having a lid, and having a strip structure line formed by forming a ground layer on a surface of the insulating substrate to which the metal lid is bonded and a central conductor layer inside the insulating substrate. In addition, a pair of brazing material outflow prevention walls made of an insulator are attached to the surface of the ground layer, the brazing material outflow prevention wall has a height of 3 to 3000 μm, a width of 0.1 to 10 mm, and the above the distance between the pair of brazing material outflow preventing walls and 0.2 to 5 mm, by joining the ground layer and the lid member by brazing material in a portion sandwiched between the pair of brazing material outflow prevention wall, conventional grayed The insulating layer provided on the upper surface of the solder layer can be omitted, the package can be reduced in size, and the brazing material does not flow out on the surface of the ground layer. It was found that it can be brazed with adhesive strength.
[0011]
Here, the brazing material outflow prevention wall is preferably formed by simultaneous firing with the insulating substrate and the ground layer, and the brazing material outflow prevention wall is preferably made of the same component as the insulating substrate.
[0012]
In addition, it is desirable that at least a central conductor is formed inside the insulating substrate facing the ground layer, and further, Ni, Co, Cr having a thickness of 1 to 20 μm on the surface of the ground layer brazed to the lid body. It is desirable to form a plating layer made of at least one metal selected from the group consisting of Au and Cu.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An example of a package for housing a semiconductor element of the present invention will be described with reference to FIG. 1 which is a schematic sectional view and FIG. 2 which is a plan view from which a metal lid is omitted.
According to the semiconductor element storage package A of FIG. 1, the concave portion 3 for accommodating the semiconductor element 2 is formed in the substantially central portion of the upper surface of the insulating substrate 1 composed of the multilayer insulating layers 1 a to 1 c, and the concave portion of the insulating substrate 1 is formed. The semiconductor element 2 mounted on 3 is hermetically sealed with a metal lid 5.
[0014]
The insulating layers 1a to 1c are made of alumina, silicon nitride, aluminum nitride, glass ceramics, or the like, and are preferably made of glass ceramics that can be co-fired with a low-resistance metal such as copper or silver.
[0015]
The metal lid 5 is made of, for example, a metal such as Kovar, 42 alloy, or copper, and can prevent the influence of an external electromagnetic wave on the semiconductor element 2 mounted in the recess 3. Note that the thermal expansion coefficient of the metal lid 3 avoids the generation of stress due to the difference in thermal expansion between the insulating substrate 1 and the metal lid 5 when the metal lid 5 is connected, and improves the hermetic sealing reliability of the package. In terms of enhancement, it is desirable to approximate the thermal expansion coefficient of the insulating substrate 1.
[0016]
Further, according to the present invention, the ground layer 6 is formed around the recess 3 on the surface of the insulating substrate 1, and the pair of frame-shaped brazing material outflow prevention walls 8 so as to cover the recess 3 on the surface of the ground layer 6. , 9 is formed and the brazing material 10 is filled in the portion sandwiched between the brazing material outflow prevention walls 8, 9, so that the ground layer 6 and the metal lid 5 are electrically connected via the brazing material 10. The inside of the recess 3 can be hermetically sealed and high adhesive strength can be maintained.
[0017]
In this structure, it is desirable that the brazing material outflow prevention walls 8 and 9 are made of ceramics integrally formed by simultaneous firing with the insulating substrate 1 and the ground layer 6 from the viewpoint of increasing the bonding strength. The walls 8 and 9 are preferably made of the same composition or the same component as the insulating substrate 1.
[0018]
Further, the shape of the brazing material outflow prevention walls 8 and 9 can fill the brazing material outflow prevention walls 8 and 9 with the amount of brazing material necessary for hermetic sealing and increase the strength at the brazing portion. In order to prevent a stress from being generated due to a difference in thermal expansion with the insulating substrate 1 and a crack or the like due to the stress concentration, it is necessary that the height be 3 to 3000 μm , and also prevent the brazing material from flowing out. The strength of the walls 8 and 9 can be maintained and formed with high accuracy, and the width of the brazing material outflow prevention walls 8 and 9 needs to be 0.1 to 5 mm in order to reduce the size and weight of the package. .
[0019]
In addition, the amount of brazing material necessary for hermetic sealing can be filled, and a brazing material 10 filling portion sandwiched between brazing material outflow prevention walls 8 and 9 in order to maintain strong adhesion between the insulating substrate 1 and the ground layer 6. The width needs to be 0.2 to 5 mm.
[0020]
In addition, a central conductor layer 12 is formed in parallel to the ground layer 6 at a position facing the ground layer 6 through the insulating layer 1a in the insulating substrate 1, and one end thereof is made of a metal wire, ribbon, It is electrically connected to the semiconductor element 2 via a lead, a TAB tape 14 and the like. Further, a ground layer 16 is formed at a position facing the central conductor layer 12 so as to extend to the lower surface of the semiconductor element 2 via the insulating layer 1b.
[0021]
Here, a strip-shaped line 18 is formed by the central conductor layer 12 and the ground layers 6 and 16, thereby preventing the influence of electromagnetic waves from the outside on the line 18. The line 18 may be provided with a pair of ground layers (not shown) on opposite sides of the center conductor layer 12 on the surface where the center conductor layer 12 is formed, and the center conductor layer 12 may have a coplanar structure. A microstrip line that does not form the layer 16 may be used.
[0022]
The central conductor layer 12 is electrically connected to a connection terminal 22 formed on the back surface of the insulating substrate 1 via the through-hole conductor 20 and is connected to an external circuit board (not shown).
[0023]
The conductor layers such as the ground layers 6 and 16, the central conductor layer 12, the through-hole conductor 20, and the connection terminal 22 are made of metal such as copper, silver, gold, tungsten, and molybdenum, and particularly transmit high-frequency signals. The line is preferably made of a low resistance metal such as copper or silver. Moreover, you may contain filler components, such as ceramics and glass, in a conductor layer.
[0024]
Further, in the insulating substrate 1, lines other than the line 18 structure, thermal vias, and the like may be formed, and a large number of them are disposed at positions surrounding the semiconductor element 2 and / or the central conductor layer 12 between the ground layers 6 and 16. It is also possible to further prevent the influence of electromagnetic waves from the outside by forming through holes.
[0025]
Further, as shown in the enlarged view in the vicinity of the portions where the brazing material outflow prevention walls 8 and 9 are formed in FIG. 3, the portion sandwiched between the brazing material outflow prevention walls 8 and 9 on the surface of the ground layer 6 has a thickness of 1 to 20 μm. It is desirable to form the plating layer 24, thereby preventing a reaction layer having a low strength from being formed due to the reaction between the brazing material 10 and the ground layer 6, and increasing the adhesive strength of the brazing material 10 to the ground layer 6. be able to. Furthermore, wettability between the plating layer 24 and the brazing material 4 can be enhanced by applying gold plating to the surface of the plating layer 24.
[0026]
Note that the package A of FIG. 1 is provided with the recess 3 in the insulating substrate 1 and the recess 3 is sealed by the flat metal lid 5, but the present invention is not limited to this, and the flat plate A structure in which a semiconductor element is mounted at a predetermined position of a shaped insulating substrate, and the semiconductor element is sealed with the insulating substrate and a bowl-shaped metal lid.
[0027]
Next, an example of a method for manufacturing a semiconductor element storage package according to the present invention will be described.
First, a ceramic powder is mixed with an organic binder and a solvent to prepare a slurry, and this slurry is used to form a green sheet by forming into a sheet by a known doctor blade method, rolling method or the like. Then, a via hole or a through hole is formed at a predetermined position of the green sheet.
[0028]
For example, when glass ceramic is used as the insulating layer, it is fired into ceramic powders such as calcium zirconate, strontium silicate, calcium titanate, strontium titanate, barium titanate, alumina, silica, mullite, forsterite, zirconia, spinel, etc. Crystalline glass for precipitating the crystal phase is added, and if desired, an acrylic resin, for example, an organic binder excellent in thermal decomposability in a nitrogen atmosphere such as methyl methacrylate and isobutyl methacrylate, and IPA, toluene, etc. It is desirable to add a solvent.
[0029]
On the other hand, fillers such as glass and ceramic powder and organic components are added to metal powders such as copper, silver, gold, tungsten, molybdenum, etc., as required, in terms of controlling the sintering temperature, shrinkage ratio by firing, and thermal expansion coefficient. Kneading to produce a conductive paste, filling the via paste or through hole formed in the green sheet with the conductive paste, and further applying the conductive paste to a predetermined position on the surface of the green sheet, such as a screen printing method To form a conductor layer having a thickness of 10 to 30 μm.
[0030]
Further, the green sheet on which the ground layer serving as the surface of the insulating substrate is formed has a position where the green sheet is formed at a position to be joined to the metal lid, or the binder from the metal powder and the ceramic powder. A pair of molded parts for a brazing material outflow prevention wall having a predetermined shape is formed by a known printing method such as a screen printing method using a paste obtained by adding and kneading theopineol or the like to at least one selected.
[0031]
Then, the positions of these printed green sheets are matched, stacked and pressed. The molded body for the brazing material outflow prevention wall may be formed after the green sheets are laminated.
[0032]
Next, after the binder is removed from the laminate, for example, by baking in a nitrogen atmosphere at a temperature of 900 to 1050 ° C., an insulating substrate having a pair of brazing material outflow prevention walls can be manufactured.
[0033]
Then, a plating layer made of at least one of Ni, Co, Cr, Au, and Cu is formed in a frame-like portion between the pair of brazing material outflow prevention walls of the obtained insulating substrate, an electrolytic plating method, an electroless plating method, or the like Then, a thickness of 1 to 20 μm is formed, and more preferably, a plating layer made of Au is applied by the same method.
[0034]
Then, a semiconductor element is mounted at a predetermined position on the insulating substrate and electrically connected to the central conductor layer via a wire by a wire bonding method or the like, and then on the surface of the plating layer forming portion between the pair of brazing material outflow prevention walls. By brazing the brazing material at 150 to 400 ° C. with an Au—Sn alloy, solder or the like, the semiconductor element housing package of the present invention in which the semiconductor element is hermetically sealed can be obtained.
[0035]
【Example】
64% by weight of crystalline glass powder having a composition of SiO 2 : 44% by weight, Al 2 O 3 : 28% by weight, MgO: 11% by weight, ZnO: 8% by weight, B 2 O 3 : 9% by weight, ceramic As a filler, 100 parts by weight of glass ceramic raw material powder consisting of 5% by weight of calcium zirconate, 14% by weight of silica, and 17% by weight of strontium silicate, 12 parts by weight of isobutyl methacrylate resin as an organic binder, and as a plasticizer 6 parts by weight of dibutyl phthalate was added, and toluene was used as a solvent to mix for 40 hours by a ball mill to prepare a slurry, which was formed into a green sheet having a thickness of 0.25 mm by a doctor blade method.
[0036]
On the other hand, 100 parts by weight of copper powder, 2 parts by weight of zinc borosilicate glass having a softening point of 800 ° C., 3 parts by weight of isobutyl methacrylate, 5 parts by weight of dibutyl phthalate, and 10 parts by weight of terpioneel are kneaded to form a conductor layer. A conductor paste was prepared. Then, three sheets of the above-described green sheets were prepared, holes were formed at predetermined positions, the above-described conductor paste was filled into the through holes by printing, and a predetermined conductor layer was formed.
[0037]
In addition, 5 parts by weight of isobutyl methacrylate, 13 parts by weight of dibutyl phthalate, and 38 parts by weight of terpione are mixed with 100 parts by weight of the glass ceramic composition described above to form a brazing material outflow prevention wall paste. A pair of brazing material outflow prevention wall moldings are adhered and formed so that the shape of the brazing material outflow prevention wall after firing is as shown in Table 1 by screen printing on the green sheet surface on which the ground layer is formed. These green sheets were aligned and laminated, and pressed and pressed with a pressure of 50 kg / cm 2 .
[0038]
Thereafter, this laminate was heat-treated in a nitrogen atmosphere containing water vapor at 750 ° C. for 3 hours to reduce the residual carbon content in the molded body to 200 ppm or less, and then fired at 930 ° C. for 1 hour. An insulating substrate 1 made of glass ceramics having an outer dimension of 30 × 40 mm provided with a conductor layer was obtained.
[0039]
Then, after forming a Ni plating layer having a thickness shown in Table 1 and a gold plating layer having a thickness of 0.2 μm on the surface of the ground layer between the pair of brazing material outflow prevention walls, a semiconductor element is formed on the surface of the insulating substrate. Mounted at a position, joined a metal lid of 20 × 25 × 0.5 mm made of 42 alloy, brazed with a brazing material made of Au—Sn alloy at 250 ° C. on the surface of the gold plating layer, The semiconductor element was hermetically sealed.
[0040]
The sample produced as described above was subjected to a thermal shock test up to 500 cycles with 5 minutes held at -65 ° C and 5 minutes held at 150 ° C as one cycle, and the number of cycles in which hermetic sealing was impaired was measured. did.
[0041]
The hermetic sealing performance was evaluated according to the method (sealing) of MIL-STD 883. Specifically, the sample was held in a pressurized atmosphere of 4.2 kgf / cm 2 for 2 hours, taken out, and then vacuumed. The number of cycles is shown in Table 1 as the airtight sealing performance was impaired when either the fine leak test for measuring the amount of He gas detected in the atmosphere or the gross leak test with fluorocarbon was performed and the acceptance criteria were not satisfied. Was written. Moreover, about the sample in which the airtight sealing property was impaired in less than 500 cycles, it observed with the microscope and the cause was shown in Table 1.
[0042]
[Table 1]
Figure 0003618063
[0043]
As is apparent from Table 1, the sample No. In No. 1, the brazing material was lost during brazing, and the package could not be hermetically sealed.
[0044]
On the other hand, sample no. In Nos. 2 to 24, good brazing was possible, and no defects such as cracks were observed 200 times or more in the thermal shock test. Among them, a sample satisfying a brazing material loss prevention wall height of 3 to 3000 μm, a width of 0.1 to 10 mm, a distance between brazing material loss prevention walls of 0.2 to 5 mm, and a plating layer thickness of 1 to 20 μm. No. In 4, 5, 9 to 13, 15 to 18, and 20 to 22, no defects such as cracks were observed 500 times or more in the thermal shock test.
[0045]
【The invention's effect】
As described above in detail, according to the present invention, the ground layer is formed on the surface to which the lid of the insulating substrate is joined, and the insulating layer on the upper surface of the ground layer that has been conventionally formed is omitted. Can be made. In addition, since a desired shape can be brazed to a predetermined position, the brazing can be performed firmly, the package can be hermetically sealed, and the semiconductor element and the center connected to the semiconductor layer by a ground layer and a metal lid The influence of electromagnetic waves from the outside can be reduced with the conductor.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing an example of a package for housing a semiconductor element of the present invention.
FIG. 2 is a plan view in which a metal lid of the package of FIG. 1 is omitted.
3 is an enlarged cross-sectional view of a joint portion between a metal lid 3 and a ground layer 6 in the package of FIG.
FIG. 4 is a schematic cross-sectional view showing an example of a conventional package for housing semiconductor elements.
[Explanation of symbols]
A Package for housing semiconductor element 1 Insulating substrate 1a to 1c Insulating layer 2 Semiconductor element 3 Recess 5 Metal lid 6, 16 Ground layer 8, 9 Brazing material loss prevention layer 10 Brazing material 12 Central conductor layer 14 Wire 18 Line 20 Through Hall conductor 22 connection terminal

Claims (5)

半導体素子が搭載される表面を有する絶縁基板と、該絶縁基板表面に前記半導体素子を気密に封止するためにロウ材によって接合される金属製蓋体と、を具備する半導体素子収納用パッケージであって、
前記絶縁基板の少なくとも前記金属製蓋体を接合する表面にグランド層を、前記絶縁基板内部に中心導体層とを形成してストリップ構造の線路を具備してなるとともに、前記グランド層表面に絶縁体からなる一対のロウ材流出防止壁を被着し、該一対のロウ材流出防止壁に挟まれた部分で前記グランド層と前記蓋体とをロウ材によって接合してなり、前記ロウ材流出防止壁の高さが３〜３０００μｍ、幅が０．１〜１０ｍｍであり、かつ前記一対のロウ材流出防止壁間の間隔が０．２〜５ｍｍであることを特徴とする半導体素子収納用パッケージ。A semiconductor element storage package comprising: an insulating substrate having a surface on which a semiconductor element is mounted; and a metal lid bonded to the insulating substrate surface by a brazing material to hermetically seal the semiconductor element. There,
A ground layer is formed on at least a surface of the insulating substrate to which the metal lid is bonded, a central conductor layer is formed inside the insulating substrate, and a strip-structured line is provided, and an insulator is formed on the surface of the ground layer. a pair of brazing material outflow prevention wall formed of deposited, the pair of Ri at a portion held braze outflow prevention wall and the ground layer name and the lid body are joined by brazing material, the brazing material outflow A package for housing a semiconductor element , wherein the height of the prevention wall is 3 to 3000 μm, the width is 0.1 to 10 mm, and the distance between the pair of brazing material outflow prevention walls is 0.2 to 5 mm. . 前記ロウ材流出防止壁が、前記絶縁基板および前記グランド層と同時焼成によって形成されたことを特徴とする請求項１記載の半導体素子収納用パッケージ。2. The package for housing a semiconductor element according to claim 1, wherein the brazing material outflow prevention wall is formed by simultaneous firing with the insulating substrate and the ground layer. 前記ロウ材流出防止壁が、前記絶縁基板と同じ成分からなることを特徴とする請求項１または２記載の半導体素子収納用パッケージ。3. The package for housing a semiconductor element according to claim 1, wherein the brazing material outflow prevention wall is made of the same component as the insulating substrate. 前記グランド層と対向する絶縁基板内部に、中心導体を形成してなることを特徴とする請求項１乃至３のいずれか記載の半導体素子収納用パッケージ。4. The package for housing a semiconductor element according to claim 1, wherein a central conductor is formed inside the insulating substrate facing the ground layer. 少なくとも前記金属製蓋体とロウ付けされるグランド層表面に厚み１〜２０μｍのＮｉ、Ｃｏ、Ｃｒ、ＡｕおよびＣｕの群から選ばれる少なくとも１種の金属からなるメッキ層を形成してなることを特徴とする請求項１乃至４のいずれか記載の半導体素子収納用パッケージ。A plating layer made of at least one metal selected from the group consisting of Ni, Co, Cr, Au and Cu having a thickness of 1 to 20 μm is formed on at least the ground layer surface to be brazed with the metal lid. 5. The package for housing a semiconductor element according to claim 1, wherein the package is for storing a semiconductor element.
JP27687099A 1999-09-29 1999-09-29 Package for storing semiconductor elements Expired - Fee Related JP3618063B2 (en)

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US7434305B2 (en) 2000-11-28 2008-10-14 Knowles Electronics, Llc. Method of manufacturing a microphone
US8617934B1 (en) 2000-11-28 2013-12-31 Knowles Electronics, Llc Methods of manufacture of top port multi-part surface mount silicon condenser microphone packages
JP4807098B2 (en) * 2006-02-21 2011-11-02 三菱電機株式会社 Package for semiconductor devices
EP2774390A4 (en) 2011-11-04 2015-07-22 Knowles Electronics Llc Embedded dielectric as a barrier in an acoustic device and method of manufacture
US9078063B2 (en) 2012-08-10 2015-07-07 Knowles Electronics, Llc Microphone assembly with barrier to prevent contaminant infiltration
JP6164538B2 (en) 2014-10-30 2017-07-19 日立金属株式会社 Lid for hermetic sealing, manufacturing method thereof, and electronic component storage package using the same
JP2016096300A (en) * 2014-11-17 2016-05-26 三菱電機株式会社 Printed circuit board
US9794661B2 (en) 2015-08-07 2017-10-17 Knowles Electronics, Llc Ingress protection for reducing particle infiltration into acoustic chamber of a MEMS microphone package

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