JP3847236B2 - Semiconductor element storage package and semiconductor device using the same - Google Patents

Semiconductor element storage package and semiconductor device using the same Download PDF

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JP3847236B2
JP3847236B2 JP2002277120A JP2002277120A JP3847236B2 JP 3847236 B2 JP3847236 B2 JP 3847236B2 JP 2002277120 A JP2002277120 A JP 2002277120A JP 2002277120 A JP2002277120 A JP 2002277120A JP 3847236 B2 JP3847236 B2 JP 3847236B2
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semiconductor element
wiring conductor
base
connector
package
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JP2004119436A (en
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哲生 平川
伸 松田
義信 澤
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Description

【０００１】
【発明の属する技術分野】
本発明は高周波の電気信号を送受信する半導体素子を収納する半導体素子収納用パッケージ、およびその半導体素子収納用パッケージを用いて成る半導体装置に関するものである。
【０００２】
【従来の技術】
従来、電気信号を送受信する半導体素子を収容するための半導体素子収納用パッケージは、一般に、酸化アルミニウム質焼結体等の電気絶縁材料から成り、上面に半導体素子の搭載部が形成された基体と、タングステン、モリブデン、マンガン、銅、銀等の金属材料から成り、基体の半導体素子搭載部から下面にかけて被着導出された複数の入出力用配線導体（第１配線導体）およびグランド用配線導体と、この配線導体と電気的に接続するようにして基体の下面に形成された複数個のグランド用パッドおよび入出力用パッドと、基体の搭載部より上面もしくは側面にかけて導出されている出入力用配線導体（第２配線導体）と、この出入力用配線導体（第２配線導体）に一端が接続されるとともに他端が外部に導出されているコネクターとにより構成されている。
【０００３】
かかる半導体素子収納用パッケージは、その搭載部に電気信号を送受信する半導体素子がＡｕ−Ｓｎろう材あるいは半田等の接合材を介して搭載固定されるとともに、半導体素子の電極が入出力用配線導体（第１配線導体）、グランド用配線導体および出入力用配線導体（第２配線導体）にボンディングワイヤや接続用リボン、半田等の導電性接続材を介して接続され、その後、必要に応じて蓋体等で半導体素子を封止することによって半導体装置となる。
【０００４】
また前記半導体装置は基体の下面に形成されているグランド用パッドおよび入出力用パッドを外部電気回路基板の回路導体に半田バンプ等を介し接続させることによって内部に収容する半導体素子が外部電気回路に接続され、同時にコネクターに同軸ケーブル等を介し外部の通信装置等の外部機器を接続させることによって半導体素子と外部機器とが接続するようになっている。
【０００５】
なお、前記半導体装置に使用されている半導体素子は複数の電気信号を合成して一つの電気信号に変換する、或いは一つの電気信号を分離して複数の電気信号に変換する機能を有しており、第１配線導体を介して入力される複数の周波数帯域が低い電気信号は半導体素子で合成されて一つの周波数帯域が高い電気信号となり、この周波数帯域の高い電気信号は第２配線導体を介してコネクターに伝送されるとともにコネクターより外部の通信装置等の外部機器に伝送され、またコネクターを介して外部機器より伝送された周波数帯域の高い電気信号は半導体素子で複数の周波数帯域が低い電気信号に変換され、各々の周波数帯域の低い電気信号は第１配線導体を介して外部電気回路に伝送されることとなる。
【０００６】
【特許文献１】
特開２００２−１６４４６６号公報
【０００７】
【発明が解決しようとする課題】
しかしながら、近年、光通信や無線通信等の機器は電気信号が高周波領域に達するとともに、高速で伝送させることが要求されるようになってきており、従来の半導体素子収納用パッケージは基体を形成する酸化アルミニウム質焼結体の比誘電率が約１０（室温、１ＭＨｚ）と高いことから、基体に設けた第１配線導体、第２配線導体を伝わる電気信号の伝送速度が遅く、高周波の電気信号を高速で伝送させるという要求を満足させることができなかった。
【０００８】
またこの酸化アルミニウム質焼結体から成る基体はその線熱膨張係数が４×１０-6／℃〜７．５×１０-6／℃であるのに対し、外部電気回路基板は一般にガラスエポキシ樹脂等の樹脂材で形成されており、その熱膨張係数が約１５×１０-6／℃程度であり、大きく相違することから、この熱膨張係数の相異に起因する熱応力が、基体下面の入出力用パッドと外部電気回路基板の回路導体とを接続している半田バンプ等に作用した場合、半田バンプ等に破断が生じ、半導体素子と外部電気回路との間で電気信号を正常に入出力させることができなくなってしまうという欠点もあった。
【０００９】
本発明は上記欠点に鑑み案出されたもので、その目的は配線導体に電気信号を高速で伝送させることを可能とするとともに内部に収容する半導体素子を外部電気回路に確実に接続することができる半導体素子収納用パッケージおよびそれを用いた半導体装置を提供することにある。
【００１０】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第１配線導体と、前記基体の下面に形成され、前記グランド配線導体および第１配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面にかけて導出されている第２配線導体と、前記基体に取着され、前記第２配線導体に電気的に接続されるコネクターと、を含んで構成される半導体素子収納用パッケージにおいて、前記基体がＬｉ２Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成され、前記基体の第２配線導体が形成された面と側面の間の角部には、前記コネクターの一部を収容する切欠きが設けられ、前記コネクターは、下面が前記基体に取着されるとともに該下面に対向する上面が外部に露出するように前記切欠きに収容されることを特徴とするものである。
【００１１】
また本発明の半導体装置は、上記構成の半導体素子収納用パッケージと４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子とを有し、前記基体の搭載部に前記半導体素子を固定するとともに該半導体素子の各電極を前記第１配線導体および第２配線導体に電気的に接続し、該半導体素子を気密封止して成る半導体装置において、前記コネクターは金属の線材及び該線材の周囲を取り囲む絶縁体から成り、前記第２配線導体は前記半導体素子の気密封止領域の外部へ導出される導出部を有し、前記コネクターの線材の一端部を絶縁体より露出させるとともに、該線材の露出部と前記第２配線導体の導出部とを接続したことを特徴とするものである。
【００１２】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、基体をＬｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成し、かかるガラスセラミック焼結体の比誘電率が約５（室温、１ＭＨｚ）と低いことから、基体に形成される第１配線導体、第２配線導体を伝わる電気信号の伝送速度を極めて速いものとなすことができる。
【００１３】
また本発明の半導体素子収納用パッケージおよび半導体装置によれば、基体を形成するＬｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体の線熱膨張係数が約１２×１０-6／℃であり、ガラスエポキシ樹脂等の樹脂材で形成されている外部電気回路基板の線熱膨張係数に近似することから外部電気回路基板に半導体装置を実装させた後、熱が作用したとしても外部電気回路基板と半導体装置の基体との間には大きな熱応力が発生することはなく、その結果、半導体装置の基体下面の入出力パッドと外部電気回路基板の回路導体とを半田バンプ等を介して確実、強固に接続することができ、半導体素子を外部電気回路基板に高い信頼性をもって接続することが可能となる。
【００１４】
【発明の実施の形態】
次に、本発明を添付図面に基づき詳細に説明する。
図１は本発明の半導体素子収納用パッケージの一実施例を示し、１は基体、２ａは第１配線導体、２ｂはグランド配線導体、３ａは入出力用パッド、３ｂはグランド用パッド、４は第２配線導体、５はコネクターである。これら基体１、第１配線導体２ａ、グランド配線導体２ｂ、入出力用パッド３ａ、グランド用パッド３ｂ、第２配線導体４およびコネクター５により半導体素子６を収納するための半導体素子収納用パッケージ７が基本的に構成される。
【００１５】
前記基体１は、Ｌｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成されており、その上面に半導体素子６を搭載するための搭載部１ａを有し、該搭載部１aに半導体素子６がガラス、樹脂、ロウ材等の接着剤を介して接着固定される。
【００１６】
前記基体１は、例えば、リチウム珪酸ガラスとクォーツ、クリストバライトなどのフィラー成分にアクリル樹脂を主成分とするバインダー及び分散剤、可塑剤、有機溶媒を加えて泥漿物を作るとともに該泥漿物をドクターブレード法やカレンダーロール法を採用することによってグリーンシート（生シート）となし、しかる後、前記グリーンシートに適当な打ち抜き加工を施すとともにこれを複数枚積層し、約８５０℃〜１１００℃の温度で焼成することによって製作される。
【００１７】
また前記基体１は、半導体素子の搭載部１ａから下面にかけて複数個の第１配線導体２ａおよびグランド用配線導体２ｂが形成されており、該各配線導体２ａ、２ｂは半導体素子の電気信号入出力用、接地用の各電極を、入出力用パッド３ａやグランド用パッド３ｂに接続するための導電路として作用し、搭載部１ａ側の一端には半導体素子６の電気信号入出力用、接地用の各電極が導電性接続材を介して電気的に接続される。
【００１８】
前記第１配線導体２ａおよびグランド用配線導体２ｂ、入出力用パッド３ａおよびグランド用パッド３ｂは、銅、銀、金、パラジウム等の金属材料から成り、例えば銅から成る場合であれば、銅粉末に有機溶剤等を添加して成る金属ペーストを基体１となるセラミックグリーンシートの表面に所定パターンに印刷しておくことによって形成される。
【００１９】
この第１配線導体２ａおよびグランド用配線導体２ｂの基体１下面側の一端は、それぞれ対応する入出力用パッド３ａおよびグランド用パッド３ｂと電気的に接続しており、これらの入出力用パッド３ａ、グランド用パッド３ｂを外部電気回路の所定の信号用や接地用等の回路導体に接続することにより、半導体素子６の電気信号入出力用、接地用の各電極が外部電気回路と電気的に接続される。
【００２０】
また前記基体１は、半導体素子の搭載部１ａから上面や側面等にかけて第２配線導体４が形成されており、該第２配線導体４は半導体素子６の電極をコネクター５に接続するための導電路として作用し、搭載部１ａ側の一端には半導体素子６の電極が導電性接続材８を介して電気的に接続される。
【００２１】
前記第２配線導体４は、上述の第１配線導体２ａ等と同様に、銅、銀、金、パラジウム等の金属材料から成り、例えば銅から成る場合であれば、銅粉末に有機溶剤等を添加して成る金属ペーストを基体１となるセラミックグリーンシートの表面に所定パターンに印刷しておくことにより形成される。
【００２２】
この第２配線導体４の基体１外表面側の一端はコネクター５と電気的に接続しており、このコネクター５を同軸ケーブル等を介して通信装置等の外部機器に接続することにより半導体素子６と外部機器との間で高周波信号の送受信が行われる。
【００２３】
前記コネクター５は、半導体素子収納用パッケージ７の第２配線導体４を同軸ケーブル等を介して外部機器に接続するための接続体として作用し、例えば、銅のリード線等の金属の線材の周囲を、酸化アルミニウム質焼結体等の絶縁体で取り囲んだ構造である。
【００２４】
かくして上述の半導体素子収納用パッケージによれば、基体１の搭載部１ａに半導体素子６を搭載するとともに、ガラス、樹脂、ロウ材等の接着剤を介して固定し、しかる後、半導体素子６の各電極を第１配線導体２ａおよびグランド配線導体２ｂに例えばボンディングワイヤ８を介して接続し、最後に蓋体１０を基体１上面に封止材を介して接合させ、半導体素子６を気密に封止することによって半導体装置１１となる。
【００２５】
この半導体装置１１は、基体１下面の入出力用パッド３ａおよびグランド用パッド３ｂが外部電気回路基板の所定の信号用や接地用等の回路導体に半田バンプ等の外部端子を介して接続され、これによって半導体素子６の信号用、接地用の各電極は外部電気回路と電気的に接続される。
【００２６】
また、この半導体装置１１に取着されているコネクター５に同軸ケーブル等の外部接続用の導線を接続することにより、半導体素子６の電極が通信装置等の外部機器に接続される。
【００２７】
そしてかかる半導体装置１１は、外部電気回路から供給される複数の周波数帯域が低い（５〜１０ＧＨｚ）電気信号を第１配線導体２ａを介して半導体素子６に入力させ、半導体素子６でこれら入力された電気信号を合成して、一つの周波数帯域が高い（４０〜８０ＧＨｚ）電気信号とするとともにこれを第２配線導体４を介してコネクター５に出力し、該コネクター５を介して外部の通信装置等の外部機器に伝送する、或いは、外部の通信装置等の外部機器から伝送された一つの周波数帯域が高い（４０〜８０ＧＨｚ）電気信号をコネクター５及び第２配線導体４を介して半導体素子６に入力し、半導体素子６で入力された周波数帯域が高い（４０〜８０ＧＨｚ）電気信号を複数の周波数帯域が低い（５〜１０ＧＨｚ）電気信号に変換するとともに、これらの個々の周波数帯域が低い電気信号を第１配線導体２ａを介して外部電気回路に供給することとなる。
【００２８】
本発明の半導体素子収納用パッケージおよびこれを用いた半導体装置においては、基体１をＬｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成しておくことが重要である。
【００２９】
前記基体１を、Ｌｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成すると、かかる焼結体の比誘電率が約５（室温、１ＭＨｚ）と低いことから基体１に形成される第１配線導体２ａ、第２配線導体４を伝わる電気信号の伝送速度を極めて速いものとなすことができる。
【００３０】
また前記基体１を、Ｌｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成すると、かかる焼結体の線熱膨張係数が約１２×１０-6／℃であり、ガラスエポキシ樹脂等の樹脂材で形成されている外部電気回路基板の線熱膨張係数に近似することから外部電気回路基板に半導体装置を実装させた後、熱が作用したとしても外部電気回路基板と半導体装置の基体１との間には大きな熱応力が発生することはなく、その結果、半導体装置の基体１下面の入出力パッド３ａと外部電気回路基板の回路導体とを半田バンプ等を介して確実、強固に接続することができ、半導体素子を外部電気回路に高い信頼性をもって接続することが可能となる。
【００３１】
また上述のガラスセラミック焼結体はその焼成温度が８５０〜１１００℃と低いことから、基体１と同時焼成により形成される第１配線導体２ａ等を比抵抗が２．５Ω・ｃｍ（２０℃）以下と低い銅や銀、金で形成することができ、その結果、第１配線導体２ａ等に電気信号を伝搬させた場合、電気信号に大きな減衰が生じることはなく、電気信号を正確かつ確実に伝搬させることも可能となる。
【００３２】
前記基体１は、Ｌｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を８５０〜１１００℃の温度で焼成し、フィラー成分であるクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの結晶相をそのまま生成させる、或いはリチウム珪酸ガラスのシリカとフォルステライトとを反応させてエンスタタイトの結晶相を生成させた焼結体となすことによって製作される。
【００３３】
なお、前記基体１を形成する焼結体は、リチウム珪酸ガラスを２０〜８０体積％、フィラー成分を２０〜８０体積％の割合とするのは、リチウム珪酸ガラスの量が２０体積％より少ない、言い換えればフィラー成分が８０体積％より多いと液相焼結することができずに高温で焼成する必要があり、その場合、第1配線導体２ａ等を銅や銀、金等の融点が低い金属材料で形成しようとしてもかかる金属材料は融点が低いことから焼成時に溶融してしまって第１配線導体２ａ等を基体１と同時焼成により形成することができなくなり、またリチウム珪酸ガラスの量が８０体積％を超える、言い換えればフィラー成分が２０体積％より少ないと焼結体の特性がリチウム珪酸ガラスの特性に大きく依存し、材料特性の制御が困難となるとともに焼結開始温度が低くなるため第１配線導体２ａ等との同時焼成が困難となってしまうためである。
【００３４】
また前記基体１に使用するＬｉ2Ｏを５〜３０質量％、好適には５〜２０質量％の割合で含有するリチウム珪酸ガラスを用いることが重要であり、このようなリチウム珪酸ガラスを用いることによりリチウム珪酸を析出させることができる。なおＬｉ2Ｏの含有量が５質量％より少ないと、焼結時にリチウム珪酸の結晶の生成量が少なくなって高強度化が達成できず、３０質量％より多いと誘電正接が１００×１０-4を超えるため配線基板用の基体１としての特性が劣化する。
【００３５】
また、この焼結体中にはＰｂを実質的に含まないことが望ましい。これはＰｂが毒性を有するため、Ｐｂを含有すると製造工程中での被毒を防止するための格別な装置及び管理を必要とするために焼結体を安価に製造することができないためである。なお、Ｐｂが不純物として不可避的に混入する場合を考慮すると、Ｐｂの量は０．０５質量％以下であることが望ましい。
【００３６】
更に前記焼結体の屈伏点が４００〜８００℃、特に４００〜６５０℃であることも、リチウム珪酸ガラス及びフィラー成分から成る混合物を形成する場合に添加する有機バインダー、溶剤の焼成時における効率的な除去及び基体１と同時に焼成される第１配線導体２ａ等との焼成条件のマッチングを図るために重要である。屈伏点が４００℃より低いとリチウム珪酸ガラスが低い温度で焼結を開始するために、例えば、銅や銀等の焼結開始温度が６００〜８００℃の金属材料を用いた第１配線導体２ａ等との同時焼成ができず、また成形体の緻密化が低温で開始するために有機バインダー、溶媒が分解揮散できなくなって、焼結体中に残留し、焼結体の特性に悪影響を及ぼす結果になるためである。一方、屈伏点が８００℃より高いと、リチウム珪酸ガラスを多くしないと焼結しにくくなるためであり、高価なリチウム珪酸ガラスを大量に必要とするために焼結体のコストを高めることにもなるためである。上記特性を満足するリチウム珪酸ガラスとしては、例えば、ＳｉＯ2−Ｌｉ2Ｏ−Ａｌ2Ｏ3、ＳｉＯ2−Ｌｉ2Ｏ−Ａｌ2Ｏ3−ＭｇＯ−ＴｉＯ2、ＳｉＯ2−Ｌｉ2Ｏ−Ａｌ2Ｏ3−ＭｇＯ−Ｎａ2Ｏ−Ｆ、ＳｉＯ2−Ｌｉ2Ｏ−Ａｌ2Ｏ3−ＭｇＯ−Ｎａ2Ｏ−ＺｎＯ、ＳｉＯ2−Ｌｉ2Ｏ−Ａｌ2Ｏ3−Ｋ2Ｏ−Ｐ2Ｏ5、ＳｉＯ2−Ｌｉ2Ｏ−Ａｌ2Ｏ3−Ｋ2Ｏ−Ｐ2Ｏ5−ＺｎＯ−Ｎａ2Ｏ3、ＳｉＯ2−Ｌｉ2Ｏ−ＭｇＯ、ＳｉＯ2−Ｌｉ2Ｏ−ＺｎＯ等の組成物が挙げられ、このうち、ＳｉＯ2はリチウム珪酸を形成するために必須の成分であり、ガラス全量中６０〜８５質量％の割合で存在し、ＳｉＯ2とＬｉ2Ｏとの合量がガラス全量中６５〜９５質量％であることがリチウム珪酸結晶を析出させるうえで望ましい。
【００３７】
一方、フィラー成分としては、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種を２０〜８０体積％、特に３０〜７０体積％の割合で配合することが望ましい。このようなフィラー成分の組み合わせにより焼結体の焼結を促進することができ、中でもクォーツ／フォルステライト比が０．４２７以上であれば、比誘電率が高いフォルステライトを焼結中の比誘電率の低いエンスタタイトに変えることができる。
【００３８】
上記のリチウム珪酸ガラス及びフィラー成分は、リチウム珪酸ガラスの屈伏点に応じ、その量を適宜調整することが望ましい。即ち、リチウム珪酸ガラスの屈伏点が４００〜６００℃と低い場合、低温での焼結性が高まるためフィラー成分の含有量は５０〜８０体積％と比確定多く配合できる。これに対して、リチウム珪酸ガラスの屈伏点が６５０〜８００℃と高い場合、焼結性が低下するためフィラー成分の含有量は２０〜５０体積％と比較的少なく配合することが望ましい。このリチウム珪酸ガラスの屈伏点は第１配線導体２ａ等の焼成条件に合わせて制御することが望ましい。
【００３９】
更にリチウム珪酸ガラスは、フィラー成分が無添加では収縮開始温度は７００℃以下で、８５０℃以上では溶融してしまい、第１配線導体２ａ等を基体１に同時焼成により被着形成することができない。しかし、フィラー成分を２０〜８０体積％の割合で混合しておくと、焼成温度を上昇させ、結晶の析出とフィラー成分を液相焼結させるための液相を形成させることができる。このフィラー成分の含有量の調整により基体１と第１配線導体２ａ等との同時焼成条件をマッチングさせることができる。更に、原料コストを下げるために高価なリチウム珪酸ガラスの含有量を減少させることができる。
【００４０】
例えば、第１配線導体２ａ等として銅を主成分とする金属材料により構成する場合、配線層６の焼成は６００〜１１００℃で行われるため、同時焼成を行うには、リチウム珪酸ガラスの屈伏点は４００〜６５０℃で、フィラー成分の含有量は５０〜８０体積％であるのが好ましい。また、このように高価なリチウム珪酸ガラスの配合量を低減することにより焼結体のコストも低減できる。
【００４１】
このリチウム珪酸ガラスとフィラー成分との混合物は、適当な成形用の有機バインダー、溶剤等を添加した後、所望の成形手段、例えばドクターブレード法、圧延法、金型プレス法等によりシート状等の任意の形状に成形後、焼成する。
【００４２】
焼成にあたっては、まず、成形のために添加した有機バインダー、溶剤成分を除去する。有機バインダー、溶剤成分の除去は通常７００℃前後の大気雰囲気中で行われるが、第１配線導体２ａ等として銅を用いる場合には、水蒸気を含有する１００〜７００℃の窒素雰囲気中で行われる。この時、成形体の収縮開始温度は７００〜８５０℃程度であることことが望ましく、かかる収縮開始温度がこれより低いと有機バインダー、溶剤成分の除去が困難となるため、成形体中のリチウム珪酸ガラスの特性、特に屈伏点を前述したように制御することが必要となる。
【００４３】
焼成は８５０〜１１００℃の酸化雰囲気中で、あるいは第１配線導体２ａ等と同時焼成する場合には非酸化性雰囲気中で行われ、これにより相対密度９０％以上まで緻密化される。この時の焼成温度が８５０℃より低いと緻密化することができず、一方１１００℃を超えると第１配線導体２ａ等との同時焼成で第１配線導体２ａ等が溶融してしまう。なお、第１配線導体２ａ等として銅を用いる場合には、８５０℃〜１０５０℃の非酸化性雰囲気で行われる。
【００４４】
なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。
【００４５】
【発明の効果】
本発明の半導体素子収納用パッケージおよび半導体装置によれば、基体をＬｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成し、かかるガラスセラミック焼結体の比誘電率が約５（室温、１ＭＨｚ）と低いことから、基体に形成さる第１配線導体、第２配線導体を伝わる電気信号の伝送速度を極めて速いものとなすことができる。
【００４６】
また本発明の半導体素子収納用パッケージおよび半導体装置によれば、基体を形成するＬｉ2Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体の線熱膨張係数が約１２×１０-6／℃であり、ガラスエポキシ樹脂等の樹脂材で形成されている外部電気回路基板の線熱膨張係数に近似することから外部電気回路基板に半導体装置を実装させた後、熱が作用したとしても外部電気回路基板と半導体装置の基体との間には大きな熱応力が発生することはなく、その結果、半導体装置の基体下面の入出力パッドと外部電気回路基板の回路導体とを半田バンプ等を介して確実、強固に接続することができ、半導体素子を外部電気回路基板に高い信頼性をもって接続することが可能となる。
【図面の簡単な説明】
【図１】本発明の半導体素子収納用パッケージおよびこの半導体素子収納用パッケージを用いた半導体装置の一実施例を示す断面図である。
【符号の説明】
１・・・・・基体
１ａ・・・・搭載部
２ａ・・・・入出力配線導体
２ｂ・・・・グランド配線導体
３ａ・・・・入出力用パッド
３ｂ・・・・グランド用パッド
４・・・・・出入力配線導体
５・・・・・コネクター
６・・・・・半導体素子
７・・・・・半導体素子収納用パッケージ
８・・・・・ボンディングワイヤ
１０・・・・蓋体
１１・・・・半導体装置[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element storage package for storing a semiconductor element that transmits and receives a high-frequency electrical signal, and a semiconductor device using the semiconductor element storage package.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a package for housing a semiconductor element for housing a semiconductor element that transmits and receives an electrical signal is generally made of an electrically insulating material such as an aluminum oxide sintered body, and a base having a semiconductor element mounting portion formed on an upper surface thereof. A plurality of input / output wiring conductors (first wiring conductors) and ground wiring conductors that are made of a metal material such as tungsten, molybdenum, manganese, copper, silver, etc. , A plurality of ground pads and input / output pads formed on the lower surface of the base so as to be electrically connected to the wiring conductor, and input / output wiring led out from the mounting portion of the base to the upper surface or the side surface A conductor (second wiring conductor) and a connector having one end connected to the input / output wiring conductor (second wiring conductor) and the other end led to the outside; It is more configuration.
[0003]
In such a package for housing a semiconductor element, a semiconductor element that transmits and receives an electrical signal is mounted and fixed to the mounting portion via a bonding material such as an Au—Sn brazing material or solder, and the electrode of the semiconductor element is an input / output wiring conductor. (First wiring conductor), ground wiring conductor and input / output wiring conductor (second wiring conductor) are connected via a conductive connecting material such as a bonding wire, a connecting ribbon, and solder, and then as necessary. A semiconductor device is obtained by sealing the semiconductor element with a lid or the like.
[0004]
In the semiconductor device, a ground pad and an input / output pad formed on the lower surface of the base are connected to a circuit conductor of an external electric circuit board through a solder bump or the like, so that a semiconductor element accommodated in the semiconductor device is an external electric circuit. At the same time, an external device such as an external communication device is connected to the connector via a coaxial cable or the like, so that the semiconductor element and the external device are connected.
[0005]
The semiconductor element used in the semiconductor device has a function of synthesizing and converting a plurality of electric signals into one electric signal, or separating one electric signal into a plurality of electric signals. In addition, a plurality of low frequency band electrical signals input through the first wiring conductor are combined by the semiconductor element to become one high frequency frequency electrical signal. The high frequency band electrical signal passes through the second wiring conductor. The high frequency signal transmitted from the connector to the external device such as an external communication device is transmitted from the connector to the external device such as a communication device. The signals are converted into signals, and the electric signals having low frequency bands are transmitted to the external electric circuit via the first wiring conductor.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-164466
[Problems to be solved by the invention]
However, in recent years, devices such as optical communication and wireless communication have come to be required to transmit electric signals at high speed and reach high frequencies, and conventional semiconductor element storage packages form a base. Since the relative permittivity of the aluminum oxide sintered body is as high as about 10 (room temperature, 1 MHz), the transmission speed of the electrical signal transmitted through the first wiring conductor and the second wiring conductor provided on the substrate is low, and the high-frequency electrical signal It was not possible to satisfy the demand for transmission at a high speed.
[0008]
To Also base made of aluminum oxide sintered body whose coefficient of linear thermal expansion is 4 × 10 -6 /℃~7.5×10 -6 / ℃ , external electric circuit board is generally glass epoxy resin Since the thermal expansion coefficient is about 15 × 10 −6 / ° C. and greatly different, the thermal stress caused by the difference in the thermal expansion coefficient is If it acts on a solder bump that connects the input / output pad and the circuit conductor of the external electric circuit board, the solder bump will break, and an electric signal is normally input between the semiconductor element and the external electric circuit. There was also a drawback that it was impossible to output.
[0009]
The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to enable an electrical signal to be transmitted at high speed to a wiring conductor and to securely connect a semiconductor element accommodated in an external electrical circuit. An object of the present invention is to provide a semiconductor element storage package and a semiconductor device using the same.
[0010]
[Means for Solving the Problems]
A package for housing a semiconductor element according to the present invention includes a base having a mounting portion on which a semiconductor element for transmitting and receiving an electrical signal of 40 GHz to 80 GHz is mounted, and a plurality of ground wirings extending from the mounting portion to the lower surface of the base A plurality of ground pads and input / output pads formed on a lower surface of the base body and electrically connected to the ground wiring conductor and the first wiring conductor; and mounting the base body In a package for housing a semiconductor element, comprising: a second wiring conductor led out from a portion to an upper surface; and a connector attached to the base and electrically connected to the second wiring conductor. substrate and 20 to 80 vol% deformation point is 400 to 800 ° C. a lithium silicate glass containing 5 to 30 mass% of Li 2 O, quartz, Chris At least one of quartz, cristobalite, tridymite, enstatite and forsterite obtained by firing a formed body containing 20 to 80% by volume of a filler component comprising at least one of barite, tridymite, enstatite and forsterite. Formed with a sintered body containing a seed crystal phase, a corner between the side surface of the substrate on which the second wiring conductor is formed is provided with a notch for accommodating a part of the connector, The connector is accommodated in the notch so that a lower surface is attached to the base and an upper surface facing the lower surface is exposed to the outside .
[0011]
The semiconductor device of the present invention includes a semiconductor element storage package having the above-described configuration and a semiconductor element that transmits and receives an electrical signal of 40 GHz to 80 GHz. The semiconductor element is fixed to the mounting portion of the base body, and In the semiconductor device in which each electrode is electrically connected to the first wiring conductor and the second wiring conductor and the semiconductor element is hermetically sealed, the connector includes a metal wire and an insulator surrounding the wire. And the second wiring conductor has a lead-out portion led out to the outside of the hermetic sealing region of the semiconductor element, and exposes one end portion of the wire of the connector from the insulator, and the exposed portion of the wire and the The second wiring conductor is connected to the lead-out portion .
[0012]
According to the semiconductor element storage package and the semiconductor device of the present invention, the base material contains 20-30% by volume of lithium silicate glass containing 5-30% by mass of Li 2 O and having a yield point of 400-800 ° C., quartz, cristobalite. At least one of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing 20 to 80% by volume of a filler component consisting of at least one of tridymite, enstatite, and forsterite Since the glass ceramic sintered body has a low relative dielectric constant of about 5 (room temperature, 1 MHz), the first wiring conductor and the second wiring conductor formed on the base body. The transmission speed of the electric signal transmitted through can be made extremely fast.
[0013]
Moreover, according to the semiconductor element storage package and the semiconductor device of the present invention, 20 to 80% by volume of lithium silicate glass having a yield point of 400 to 800 ° C. containing 5 to 30% by mass of Li 2 O forming the base body, Of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing 20 to 80% by volume of a filler component composed of at least one of quartz, cristobalite, tridymite, enstatite, and forsterite The sintered body containing at least one crystalline phase has a linear thermal expansion coefficient of about 12 × 10 −6 / ° C., and the linear thermal expansion coefficient of the external electric circuit board formed of a resin material such as glass epoxy resin. After mounting the semiconductor device on the external electric circuit board, even if heat is applied, Large thermal stress is not generated between the semiconductor device and the base of the semiconductor device, and as a result, the input / output pads on the bottom surface of the base of the semiconductor device and the circuit conductor of the external electric circuit board are securely connected via solder bumps, It is possible to connect firmly and the semiconductor element can be connected to the external electric circuit board with high reliability.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 shows an embodiment of a package for housing a semiconductor device according to the present invention. Reference numeral 1 denotes a base, 2a denotes a first wiring conductor, 2b denotes a ground wiring conductor, 3a denotes an input / output pad, 3b denotes a ground pad, The second wiring conductor 5 is a connector. A semiconductor element housing package 7 for housing the semiconductor element 6 by the substrate 1, the first wiring conductor 2a, the ground wiring conductor 2b, the input / output pad 3a, the ground pad 3b, the second wiring conductor 4 and the connector 5 is provided. Basically composed.
[0015]
The base body 1 contains 20-30% by volume of lithium silicate glass containing 5-30% by mass of Li 2 O and having a yield point of 400-800 ° C., and is at least one of quartz, cristobalite, tridymite, enstatite, forsterite. It is formed of a sintered body containing at least one crystal phase of quartz, cristobalite, tridymite, enstatite, and forsterite obtained by firing a formed body containing a filler component of 20 to 80% by volume. It has a mounting portion 1a for mounting the semiconductor element 6 on its upper surface, and the semiconductor element 6 is bonded and fixed to the mounting portion 1a via an adhesive such as glass, resin, or brazing material.
[0016]
The substrate 1 is made of, for example, lithium silicate glass and a filler component such as quartz, cristobalite, etc. by adding a binder mainly composed of an acrylic resin, a dispersant, a plasticizer, and an organic solvent. The green sheet (raw sheet) is formed by adopting the method and the calender roll method. After that, the green sheet is appropriately punched and laminated, and fired at a temperature of about 850 ° C. to 1100 ° C. It is manufactured by doing.
[0017]
The base 1 is formed with a plurality of first wiring conductors 2a and ground wiring conductors 2b from the semiconductor element mounting portion 1a to the lower surface, and the wiring conductors 2a and 2b are input / output electric signals of the semiconductor elements. Each of the electrodes for grounding and grounding acts as a conductive path for connecting to the input / output pad 3a and the grounding pad 3b, and one end on the mounting portion 1a side is for electrical signal input / output of the semiconductor element 6 and grounding These electrodes are electrically connected through a conductive connecting material.
[0018]
The first wiring conductor 2a, the ground wiring conductor 2b, the input / output pad 3a, and the ground pad 3b are made of a metal material such as copper, silver, gold, or palladium. It is formed by printing a metal paste formed by adding an organic solvent or the like on the surface of the ceramic green sheet serving as the substrate 1 in a predetermined pattern.
[0019]
One end of the first wiring conductor 2a and the ground wiring conductor 2b on the lower surface side of the base body 1 is electrically connected to the corresponding input / output pad 3a and ground pad 3b, respectively, and these input / output pads 3a. By connecting the ground pad 3b to a predetermined signal or ground circuit conductor of the external electric circuit, the electric signal input / output and ground electrodes of the semiconductor element 6 are electrically connected to the external electric circuit. Connected.
[0020]
The base 1 has a second wiring conductor 4 formed from the semiconductor element mounting portion 1 a to the upper surface, side surface, and the like. The second wiring conductor 4 is a conductive material for connecting the electrode of the semiconductor element 6 to the connector 5. The electrode of the semiconductor element 6 acts as a path, and is electrically connected to one end on the mounting portion 1a side via the conductive connecting material 8.
[0021]
The second wiring conductor 4 is made of a metal material such as copper, silver, gold, or palladium, like the first wiring conductor 2a described above. For example, if the second wiring conductor 4 is made of copper, an organic solvent or the like is added to the copper powder. The added metal paste is formed by printing a predetermined pattern on the surface of the ceramic green sheet to be the base 1.
[0022]
One end of the second wiring conductor 4 on the outer surface side of the base body 1 is electrically connected to a connector 5, and the semiconductor element 6 is obtained by connecting the connector 5 to an external device such as a communication device via a coaxial cable or the like. High-frequency signals are transmitted and received between the device and the external device.
[0023]
The connector 5 acts as a connection body for connecting the second wiring conductor 4 of the semiconductor element storage package 7 to an external device via a coaxial cable or the like, for example, around a metal wire such as a copper lead wire. Is surrounded by an insulator such as an aluminum oxide sintered body.
[0024]
Thus, according to the above-described package for housing a semiconductor element, the semiconductor element 6 is mounted on the mounting portion 1a of the base body 1 and fixed through an adhesive such as glass, resin, brazing material, and then the semiconductor element 6 is mounted. Each electrode is connected to the first wiring conductor 2a and the ground wiring conductor 2b via, for example, a bonding wire 8. Finally, the lid 10 is bonded to the upper surface of the base body 1 with a sealing material, and the semiconductor element 6 is hermetically sealed. By stopping, the semiconductor device 11 is obtained.
[0025]
In this semiconductor device 11, input / output pads 3a and ground pads 3b on the lower surface of the substrate 1 are connected to predetermined signal or ground circuit conductors of an external electric circuit board via external terminals such as solder bumps. As a result, the signal and ground electrodes of the semiconductor element 6 are electrically connected to the external electric circuit.
[0026]
Further, by connecting an external connection conductor such as a coaxial cable to the connector 5 attached to the semiconductor device 11, the electrode of the semiconductor element 6 is connected to an external device such as a communication device.
[0027]
The semiconductor device 11 inputs a plurality of low frequency band (5 to 10 GHz) electric signals supplied from an external electric circuit to the semiconductor element 6 through the first wiring conductor 2a, and these are input by the semiconductor element 6. The electrical signal is synthesized into an electrical signal having a high frequency band (40 to 80 GHz) and output to the connector 5 via the second wiring conductor 4, and an external communication device via the connector 5. The semiconductor element 6 transmits an electrical signal having a high frequency band (40 to 80 GHz) transmitted from an external device such as an external communication device via the connector 5 and the second wiring conductor 4. Is converted into an electrical signal having a high frequency band (40 to 80 GHz) and a plurality of low frequency bands (5 to 10 GHz). Both, so that these individual frequency band is supplied to an external electrical circuit through the first wiring conductor 2a low electrical signal.
[0028]
In the package for housing a semiconductor element of the present invention and the semiconductor device using the same, 20 to 80% by volume of lithium silicate glass containing a base 1 containing 5 to 30% by mass of Li 2 O and having a yield point of 400 to 800 ° C. Quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing 20 to 80% by volume of a filler component consisting of at least one of quartz, cristobalite, tridymite, enstatite, and forsterite It is important to form the sintered body containing at least one crystal phase.
[0029]
The base 1 contains 20 to 80% by volume of lithium silicate glass containing 5 to 30% by mass of Li 2 O and having a yield point of 400 to 800 ° C., and at least one of quartz, cristobalite, tridymite, enstatite, and forsterite. And forming a sintered body containing at least one crystal phase of quartz, cristobalite, tridymite, enstatite, and forsterite obtained by firing a formed body containing a filler component of 20 to 80% by volume. Since the relative dielectric constant of such a sintered body is as low as about 5 (room temperature, 1 MHz), the transmission speed of the electrical signal transmitted through the first wiring conductor 2a and the second wiring conductor 4 formed on the substrate 1 is extremely high. Can be made.
[0030]
Further, the substrate 1 is composed of 20 to 80% by volume of lithium silicate glass containing 5 to 30% by mass of Li 2 O and having a yield point of 400 to 800 ° C., and at least one of quartz, cristobalite, tridymite, enstatite and forsterite. Formed with a sintered body containing at least one crystal phase of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing a filler component of 20 to 80% by volume Then, the linear thermal expansion coefficient of the sintered body is about 12 × 10 −6 / ° C., which approximates the linear thermal expansion coefficient of an external electric circuit board formed of a resin material such as glass epoxy resin. Even if heat is applied after the semiconductor device is mounted on the electric circuit board, there is a large gap between the external electric circuit board and the base 1 of the semiconductor device. As a result, the input / output pad 3a on the lower surface of the substrate 1 of the semiconductor device and the circuit conductor of the external electric circuit board can be reliably and firmly connected via the solder bumps, The semiconductor element can be connected to the external electric circuit with high reliability.
[0031]
In addition, since the sintering temperature of the glass ceramic sintered body is as low as 850 to 1100 ° C., the specific resistance of the first wiring conductor 2a and the like formed by simultaneous firing with the substrate 1 is 2.5 Ω · cm (20 ° C.). As a result, when an electric signal is propagated to the first wiring conductor 2a or the like, the electric signal is not greatly attenuated, and the electric signal is accurately and reliably formed. It is also possible to propagate to.
[0032]
The base body 1 contains 20-30% by volume of lithium silicate glass containing 5-30% by mass of Li 2 O and having a yield point of 400-800 ° C., and is at least one of quartz, cristobalite, tridymite, enstatite, forsterite. The formed body containing 20 to 80% by volume of the filler component is fired at a temperature of 850 to 1100 ° C., and the crystal phases of the filler components quartz, cristobalite, tridymite, enstatite, and forsterite are generated as they are. Alternatively, it is produced by reacting lithium silicate glass silica and forsterite to produce a sintered body in which an enstatite crystal phase is generated.
[0033]
In addition, the sintered compact which forms the said base | substrate 1 makes lithium silicate glass 20 to 80 volume%, and makes a filler component into the ratio of 20 to 80 volume%. The quantity of lithium silicate glass is less than 20 volume%, In other words, if the filler component is more than 80% by volume, liquid phase sintering cannot be performed and it is necessary to fire at a high temperature. In this case, the first wiring conductor 2a is a metal having a low melting point such as copper, silver, or gold. Even if it is going to form with a material, since such a metal material has a low melting point, it melts at the time of firing, so that the first wiring conductor 2a and the like cannot be formed simultaneously with the base 1, and the amount of lithium silicate glass is 80 If the volume percentage exceeds, in other words, the filler component is less than 20 volume%, the characteristics of the sintered body greatly depend on the characteristics of the lithium silicate glass, making it difficult to control the material characteristics and starting sintering. This is because simultaneous firing with the first wiring conductor 2a and the like becomes difficult because the temperature becomes low.
[0034]
In addition, it is important to use a lithium silicate glass containing 5 to 30% by mass, preferably 5 to 20% by mass of Li 2 O used for the substrate 1, and such a lithium silicate glass is used. Can precipitate lithium silicic acid. If the Li 2 O content is less than 5% by mass, the amount of lithium silicic acid crystals produced during sintering is reduced and high strength cannot be achieved. If it exceeds 30% by mass, the dielectric loss tangent is 100 × 10 − Since it exceeds 4 , the characteristic as the base | substrate 1 for wiring boards deteriorates.
[0035]
Further, it is desirable that this sintered body does not substantially contain Pb. This is because Pb has toxicity, and if it contains Pb, it requires special equipment and control for preventing poisoning during the manufacturing process, and thus a sintered body cannot be manufactured at low cost. . In consideration of the case where Pb is inevitably mixed as an impurity, the amount of Pb is desirably 0.05% by mass or less.
[0036]
Furthermore, the fact that the yield point of the sintered body is 400 to 800 ° C., particularly 400 to 650 ° C., indicates that the organic binder added when forming a mixture composed of lithium silicate glass and a filler component and the efficiency during firing of the solvent This is important in order to match the firing conditions with the first wiring conductor 2a and the like that are fired at the same time as the substrate 1 is removed. When the yield point is lower than 400 ° C, the lithium silicate glass starts sintering at a low temperature. For example, the first wiring conductor 2a using a metal material having a sintering start temperature of 600 to 800 ° C such as copper or silver is used. Cannot be fired simultaneously, and the densification of the molded body starts at a low temperature, so the organic binder and solvent cannot be decomposed and volatilized and remain in the sintered body, adversely affecting the properties of the sintered body. It is because it becomes a result. On the other hand, if the yield point is higher than 800 ° C., it is difficult to sinter unless the amount of lithium silicate glass is increased, and it is necessary to increase the cost of the sintered body because a large amount of expensive lithium silicate glass is required. It is to become. Examples of the lithium silicate glass that satisfies the above characteristics include SiO 2 —Li 2 O—Al 2 O 3 , SiO 2 —Li 2 O—Al 2 O 3 —MgO—TiO 2 , and SiO 2 —Li 2 O—Al. 2 O 3 —MgO—Na 2 O—F, SiO 2 —Li 2 O—Al 2 O 3 —MgO—Na 2 O—ZnO, SiO 2 —Li 2 O—Al 2 O 3 —K 2 O—P 2 O 5 , SiO 2 —Li 2 O—Al 2 O 3 —K 2 O—P 2 O 5 —ZnO—Na 2 O 3 , SiO 2 —Li 2 O—MgO, SiO 2 —Li 2 O—ZnO, etc. Among them, SiO 2 is an essential component for forming lithium silicic acid, and is present in a proportion of 60 to 85% by mass in the total amount of glass, and the total amount of SiO 2 and Li 2 O is It is desirable that it is 65 to 95% by mass in the total amount of glass in order to precipitate lithium silicate crystals.
[0037]
On the other hand, as a filler component, it is desirable to mix at least one of quartz, cristobalite, tridymite, enstatite, and forsterite in a proportion of 20 to 80% by volume, particularly 30 to 70% by volume. Sintering of the sintered body can be promoted by such a combination of filler components. In particular, if the quartz / forsterite ratio is 0.427 or more, the relative dielectric constant during sintering of forsterite having a high relative dielectric constant is obtained. It can be changed to low enstatite.
[0038]
It is desirable that the amount of the lithium silicate glass and filler component is appropriately adjusted according to the yield point of the lithium silicate glass. That is, when the yield point of lithium silicate glass is as low as 400 to 600 ° C., the sinterability at low temperatures is enhanced, so the content of the filler component can be blended with a certain amount of 50 to 80% by volume. On the other hand, when the yield point of lithium silicate glass is as high as 650 to 800 ° C., the sinterability is lowered, so the content of the filler component is desirably 20 to 50% by volume, which is relatively small. It is desirable to control the yield point of this lithium silicate glass according to the firing conditions of the first wiring conductor 2a and the like.
[0039]
Furthermore, the lithium silicate glass has a shrinkage start temperature of 700 ° C. or lower when no filler component is added, and melts at 850 ° C. or higher, and the first wiring conductor 2 a and the like cannot be deposited on the substrate 1 by simultaneous firing. . However, if the filler component is mixed at a ratio of 20 to 80% by volume, the firing temperature can be increased, and a liquid phase for crystal precipitation and liquid phase sintering of the filler component can be formed. By adjusting the content of the filler component, the simultaneous firing conditions of the substrate 1 and the first wiring conductor 2a can be matched. Furthermore, the content of expensive lithium silicate glass can be reduced in order to reduce the raw material cost.
[0040]
For example, when the first wiring conductor 2a or the like is made of a metal material mainly composed of copper, the wiring layer 6 is baked at 600 to 1100 ° C. Therefore, in order to perform simultaneous baking, the yield point of lithium silicate glass is used. Is 400 to 650 ° C., and the filler component content is preferably 50 to 80% by volume. Moreover, the cost of a sintered compact can also be reduced by reducing the compounding quantity of such expensive lithium silicate glass.
[0041]
The mixture of the lithium silicate glass and the filler component is added to an appropriate organic binder for molding, a solvent, etc., and then formed into a sheet or the like by a desired molding means such as a doctor blade method, a rolling method, a die pressing method, etc. After forming into an arbitrary shape, firing.
[0042]
In firing, first, the organic binder and solvent component added for molding are removed. The removal of the organic binder and the solvent component is usually performed in an air atmosphere at around 700 ° C., but when copper is used as the first wiring conductor 2a or the like, it is performed in a nitrogen atmosphere at 100 to 700 ° C. containing water vapor. . At this time, the shrinkage start temperature of the molded body is preferably about 700 to 850 ° C. If the shrinkage start temperature is lower than this, it becomes difficult to remove the organic binder and the solvent component. It is necessary to control the properties of the glass, particularly the yield point, as described above.
[0043]
Firing is performed in an oxidizing atmosphere of 850 to 1100 ° C., or in a non-oxidizing atmosphere when cofiring with the first wiring conductor 2a and the like, thereby densifying to a relative density of 90% or more. If the firing temperature at this time is lower than 850 ° C., it cannot be densified. On the other hand, if it exceeds 1100 ° C., the first wiring conductor 2a and the like are melted by simultaneous firing with the first wiring conductor 2a and the like. In addition, when using copper as the 1st wiring conductor 2a etc., it carries out in non-oxidizing atmosphere of 850 degreeC-1050 degreeC.
[0044]
In addition, this invention is not limited to the above-mentioned Example, A various change is possible if it is a range which does not deviate from the summary of this invention.
[0045]
【The invention's effect】
According to the semiconductor element storage package and the semiconductor device of the present invention, the base material contains 20-30% by volume of lithium silicate glass containing 5-30% by mass of Li 2 O and having a yield point of 400-800 ° C., quartz, cristobalite. At least one of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing 20 to 80% by volume of a filler component consisting of at least one of tridymite, enstatite, and forsterite Since the glass ceramic sintered body has a low dielectric constant of about 5 (room temperature, 1 MHz), the first wiring conductor and the second wiring conductor formed on the substrate are The transmission speed of the transmitted electric signal can be made extremely fast.
[0046]
Moreover, according to the semiconductor element storage package and the semiconductor device of the present invention, 20 to 80% by volume of lithium silicate glass having a yield point of 400 to 800 ° C. containing 5 to 30% by mass of Li 2 O forming the base body, Of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing 20 to 80% by volume of a filler component composed of at least one of quartz, cristobalite, tridymite, enstatite, and forsterite The sintered body containing at least one crystalline phase has a linear thermal expansion coefficient of about 12 × 10 −6 / ° C., and the linear thermal expansion coefficient of the external electric circuit board formed of a resin material such as glass epoxy resin. After mounting the semiconductor device on the external electric circuit board, even if heat is applied, Large thermal stress is not generated between the semiconductor device and the base of the semiconductor device, and as a result, the input / output pads on the bottom surface of the base of the semiconductor device and the circuit conductor of the external electric circuit board are securely connected via solder bumps, It is possible to connect firmly and the semiconductor element can be connected to the external electric circuit board with high reliability.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package and a semiconductor device using the semiconductor element housing package of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base | substrate 1a ... Mounting part 2a ... Input / output wiring conductor 2b ... Ground wiring conductor 3a ... Input / output pad 3b ... Ground pad 4 ··· I / O conductor 5 ··· Connector 6 ··· Semiconductor element 7 · · · Semiconductor element storage package 8 · · · Bonding wire 10 ··· Cover 11 .... Semiconductor devices

Claims (2)

４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子が搭載される搭載部を有する基体と、該基体の前記搭載部より下面にかけて導出されている複数個のグランド配線導体および第１配線導体と、前記基体の下面に形成され、前記グランド配線導体および第１配線導体に電気的に接続している複数個のグランド用パッドおよび入出力用パッドと、前記基体の搭載部より上面にかけて導出されている第２配線導体と、前記基体に取着され、前記第２配線導体に電気的に接続されるコネクターと、を含んで構成される半導体素子収納用パッケージにおいて、
前記基体がＬｉ２Ｏを５〜３０質量％含有する屈伏点が４００〜８００℃のリチウム珪酸ガラスを２０〜８０体積％と、クォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種から成るフィラー成分を２０〜８０体積％の割合で含む形成体を焼成して得られたクォーツ、クリストバライト、トリジマイト、エンスタタイト、フォルステライトの少なくとも１種の結晶相を含有する焼結体で形成され、前記基体の第２配線導体が形成された面と側面の間の角部には、前記コネクターの一部を収容する切欠きが設けられ、前記コネクターは、下面が前記基体に取着されるとともに該下面に対向する上面が外部に露出するように前記切欠きに収容されることを特徴とする半導体素子収納用パッケージ。A base having a mounting portion on which a semiconductor element for transmitting and receiving electrical signals of 40 GHz to 80 GHz is mounted; a plurality of ground wiring conductors and first wiring conductors extending from the mounting portion to a lower surface of the base; and the base A plurality of ground pads and input / output pads electrically connected to the ground wiring conductor and the first wiring conductor, and a second lead extending from the mounting portion of the base to the upper surface. In a package for housing a semiconductor element comprising a wiring conductor and a connector attached to the base and electrically connected to the second wiring conductor,
The substrate contains 20-80% by volume of lithium silicate glass containing 5-30% by mass of Li 2 O and having a yield point of 400-800 ° C., and is composed of at least one of quartz, cristobalite, tridymite, enstatite, and forsterite. Formed of a sintered body containing at least one crystal phase of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing a filler component in a proportion of 20 to 80% by volume, A notch for accommodating a part of the connector is provided at a corner between the surface of the substrate where the second wiring conductor is formed and the side surface, and the lower surface of the connector is attached to the substrate and the A package for housing a semiconductor element, wherein the package is housed in the notch so that an upper surface facing the lower surface is exposed to the outside . 請求項１に記載の半導体素子収納用パッケージと４０ＧＨｚ〜８０ＧＨｚの電気信号を送受信する半導体素子とを有し、前記基体の搭載部に前記半導体素子を固定するとともに該半導体素子の各電極を前記第１配線導体および第２配線導体に電気的に接続し、該半導体素子を気密封止して成る半導体装置において、
前記コネクターは金属の線材及び該線材の周囲を取り囲む絶縁体から成り、前記第２配線導体は前記半導体素子の気密封止領域の外部へ導出される導出部を有し、前記コネクターの線材の一端部を絶縁体より露出させるとともに、該線材の露出部と前記第２配線導体の導出部とを接続したことを特徴とする半導体装置。A package for housing a semiconductor element according to claim 1 and a semiconductor element for transmitting and receiving an electrical signal of 40 GHz to 80 GHz. The semiconductor element is fixed to a mounting portion of the base and each electrode of the semiconductor element is connected to the first electrode. In a semiconductor device that is electrically connected to one wiring conductor and a second wiring conductor and hermetically sealing the semiconductor element,
The connector is composed of a metal wire and an insulator surrounding the wire, and the second wiring conductor has a lead-out portion led out to the outside of the hermetic sealing region of the semiconductor element, and one end of the wire of the connector A semiconductor device, wherein the exposed portion of the wire is connected to the lead-out portion of the second wiring conductor.
JP2002277120A 2002-09-24 2002-09-24 Semiconductor element storage package and semiconductor device using the same Expired - Fee Related JP3847236B2 (en)

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