WO2001024154A1 - Dispositif d'affichage a cristaux liquides avec commande de correction de tension pour reduire les effets negatifs du couplage capacitif entre des electrodes de pixels adjacentes - Google Patents

Dispositif d'affichage a cristaux liquides avec commande de correction de tension pour reduire les effets negatifs du couplage capacitif entre des electrodes de pixels adjacentes Download PDF

Info

Publication number
WO2001024154A1
WO2001024154A1 PCT/EP2000/009674 EP0009674W WO0124154A1 WO 2001024154 A1 WO2001024154 A1 WO 2001024154A1 EP 0009674 W EP0009674 W EP 0009674W WO 0124154 A1 WO0124154 A1 WO 0124154A1
Authority
WO
WIPO (PCT)
Prior art keywords
potential
sub
pixel electrode
potentials
liquid crystal
Prior art date
Application number
PCT/EP2000/009674
Other languages
English (en)
Inventor
Shuji Hagino
Yuko Furui
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2001024154A1 publication Critical patent/WO2001024154A1/fr

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the invention relates to a liquid crystal display device comprising a first substrate provided with plural pixel electrodes and a second substrate provided with a common electrode.
  • a voltage is applied on a liquid crystal to drive the liquid crystal.
  • an alternating voltage is applied to the liquid crystal.
  • a frame-alternating drive has been known as one of the methods for driving a liquid crystal.
  • flicker is easily occurred.
  • other methods have been used for driving a liquid crystal by applying a voltage on the liquid crystal so that the polarities of the neighboring pixels becomes opposite with respect to each other, including a line-alternating drive method, a row-altemating method, and a pixel-alternating drive method.
  • each frame as shown in Fig. 8, the polarities of the respective pixels placed in a row direction are defined so that two adjacent pixels have the same polarity and the polarities of the pixels are varied every two pixels.
  • the polarity of each pixel in the odd- numbered frame is opposite to the corresponding pixel of the even-numbered frame.
  • the 2 column- 1 row method causes less troubles such as crosstalk and flicker in comparison with the other methods such as line-, row-, and pixel-altemating drive.
  • the 2 column- 1 row method there is another problem to be caused. If a liquid crystal display shows an image filled with a substantially constant lightness of color, such as an image of blue sky, the display would be expected to show an image having evenly distributed lightness of color. Nevertheless, in some cases, there is a problem that a phenomenon where light column and dark column occur alternately (hereinafter referred to as horizontal stripes) is recognized.
  • the object of the present invention is to provide a liquid crystal display device that hardly displays horizontal stripes, even though the liquid crystal display device displays an image filled with a substantially constant lightness.
  • a liquid crystal display device which is comprising a first substrate provided with plural pixel electrodes to which a potential is applied via a same data line, a second substrate provided with a common electrode, said second substrate for sandwiching liquid crystal between the first substrate and the second substrate, and potential application means for applying the potential to the plural pixel electrodes on the basis of plural pixel data, wherein the potential application means corrects the potential to be applied to the plural pixel electrodes on the basis of coupling capacitance formed between mutually adjacent pixel electrodes.
  • the term "pixel electrode” denotes not only a pixel electrode which is formed so as to be correspond to each dot in a black-and- white image where one pixel is constructed of one dot but also a sub-pixel electrode which is formed so as to be correspond to each dot in a color image where one pixel is constructed of two or more dots, for example one pixel is constructed of three dots.
  • the term "pixel data” denotes not only a pixel data which is correspond to each dot in the case that one pixel is constructed of one dot but also a sub-pixel data which is correspond to each dot in the case that one pixel is constructed of two or more dots.
  • a coupling capacitance formed between pixel electrodes adjacent to each other may become a cause of horizontal stripes. Therefore, an image can be shown without causing horizontal stripes thereon if a voltage is applied on each pixel electrode on the basis of a coupling capacitance, as described above.
  • the potential application means has reference potential generation means for generating reference potentials and reference potential correction means for correcting the reference potentials generated by the reference potential generation means on the basis of the coupling capacitance
  • the potential application means generates a plural potentials from the corrected reference potentials, selects each of potentials corresponding to each of the plural pixel data from the plural potentials, and applies these selected potentials to the plural pixel electrodes.
  • the generation of horizontal stripes may be avoided by correcting a potential to be generated from the reference potential generation means on the basis of the coupling capacitance.
  • the reference potential generation means generates plural reference potentials by ladder resistance.
  • a plural reference potentials can be easily obtained by the use of a ladder resistance.
  • the reference potential correction means corrects the potential generated by the reference potential generation means at an intermediate position of the ladder resistance.
  • the extent of variations in the light transmission with respect to the extent of variations in voltage is large at a region corresponding to a halftone.
  • the extent is small at a region close to the side of white or black. Therefore, even if a signal to be generated from the reference potential generation means is corrected at an intermediate position of the ladder resistance, the voltage of a pixel electrode can be corrected with a high degree of precision as long as the intermediate position is near the end of the ladder resistance.
  • the potential application means has reference potential generation means for generating reference potentials and data correction means for correcting the plural pixel data on the basis of the coupling capacitance
  • the potential application means generates a plural potentials from the corrected reference potentials, selects each of potentials corresponding to each of the corrected plural pixel data from the plural potentials, and applies these selected potentials to the plural pixel electrodes.
  • the potential to be applied on the pixel electrode can be corrected by correcting pixel data itself instead of the potential to be generated from the reference potential generation means.
  • Fig. 1 is a block diagram that illustrates the configuration of a liquid crystal display device as one mode for carrying out the invention.
  • the liquid crystal display device has a liquid crystal panel 1.
  • the liquid crystal panel 1 comprises a thin-film transistor (TFT) substrate (not shown) provided with pixel electrodes and a color filter substrate (not shown) provided with common electrode. Liquid crystal is sandwiched between these substrates.
  • the liquid crystal panel 1 has (3072 x 768) sub-pixels, each of sub pixel electrodes is constructed of three sub-pixels R(Red), G(Green)and B(Blue). That is to say,
  • Fig. 2 is an enlarged view of a part of the TFT substrate of the liquid crystal panel 1 shown in Fig. 1.
  • a portion of the TFT substrate which correspond to the sub- pixels R(red) of the pixels n, n + 1, and n + 2 is shown.
  • a gate bass extends between the sub-pixels adjacent to each other.
  • four gate buses Gn - 1, Gn, Gn + 1 , and Gn + 2 are shown.
  • source bus S (which corresponds to data line in the present invention) extends across those gate buses in a vertical direction.
  • sub- pixel electrodes (which correspond to pixel electrodes in the present invention) En, En + 1 , and En + 2 are formed in the area which correspond to the sub-pixels R of the pixels n, n + 1, and n + 2, respectively.
  • TFT Thin Film Transistor
  • TFT (n), TFT (n + 1), and TFT (n + 2) enters the ON state, the signals passed through the source bus S are transmitted to the sub-pixel electrodes En, En + 1 , and En + 2, respectively. If each of TFT (n), TFT (n + 1), and TFT (n + 2) enters the OFF state, the signals passed through the source bus S are not transmitted to the sub-pixel electrodes En, En + 1 , and En + 2, respectively.
  • Fig. 2 shows the structure of the portion corresponding to the sub-pixels R.
  • the sub-pixels G and the sub-pixels B also have the same structure as that of the portion corresponding to the sub-pixels R.
  • a gate driver 2 and eight source drivers 3 are positioned around the liquid crystal panel 1.
  • Each source driver 3 comprises an amplifier 3 a, a digital-to-analog converter (DAC) 3b, and a latch 3c.
  • DAC digital-to-analog converter
  • a signal control unit and an power supply (hereinafter referred to as signal power supply) 4 are provided in the liquid crystal display device.
  • the signal power supply 4 supplies power supply voltage to the gate driver 2 and the source driver 3, and also supplies control signals to the gate driver 2 and the source driver 3.
  • Each of the source drivers 3 receives 6 bit sub-image data.
  • the liquid crystal display device further comprises a gamma-correction reference potential generation circuit (hereinafter, referred to simply as a potential generation circuit) 5 for supplying a reference potential to each of the source drivers 3.
  • the potential generation circuit 5 comprises a positive-side electric power supply 51 and a negative-side electric power supply 53. These electric power supplies 51 and 53 are connected to ladder resistances R1-R10 connected in series through amplifiers 55 and 56, respectively.
  • the potential generation circuit 5 comprises a signal generation part for correcting positive-side (hereinafter, referred to simply as a positive correction part) 52 and a signal generation part for correcting negative-side (hereinafter, referred to simply as a negative correction part) 54.
  • the positive correction part 52 generates a rectangular signal for correcting a potential supplied from the positive-side electric power supply 51 on the basis of a coupling capacitance (described later) formed between the sub-pixels adjacent to each other.
  • the negative correction part 54 generates a rectangular signal for correcting a potential supplied from the negative- side electric power supply 53 on the basis of a coupling capacitance described later.
  • the potential supplied from the positive-side electrode 51 is corrected with the addition of the rectangular signal generated from the positive correction part 52.
  • the corrected potential becomes a reference potential VI through the amplifier 55.
  • the potential supplied from the negative-side electric power supply 53 is corrected with the addition of the rectangular signal generated from the negative correction part 54.
  • the corrected potential becomes a reference potential V10 through the amplifier 56.
  • the potentials passing through their respective amplifiers 55, 56 are resistance- divided by the ladder resistances Rl to RIO, resulting in the generation of reference potentials V2 to N9, respectively. Consequently, ten reference potentials VI to VI 0 are generated.
  • the reference potentials VI to V10 are larger than the alternating central potential.
  • the reference potentials V6 to V10 are smaller than the alternating central potential.
  • the reference potentials VI to V5 may be referred to as positive reference potentials
  • the reference potentials V6 to VI 0 may be referred to as negative reference potentials.
  • Each of generated reference potentials VI to VI 0 is introduced into the DAC 3b of each source bus 3.
  • the DAC 3b generates many potentials by resistance-dividing the potential generated from the potential generation circuit 5, and selects a potential to be supplied to each sub-pixel electrode from the above-mentioned many potentials.
  • Control signals are supplied from the control electric power supply 4 to the gate driver 2 and the source drivers 8, respectively.
  • the gate driver 2 transfers signals for turning on the TFT to each of the gate buses (see Fig. 2) on the basis of the control signals.
  • a latch 3 c of each source driver 3 latches 6-bit sub-pixel data. Then the sub-pixel data being latched in the latch 3 c is successively sent to the DAC 3b.
  • the control power supply 4 generates a polarity control signal for controlling whether DAC3b selects the potential from many potentials generated by resistance-dividing the positive reference potentials VI -V5 or selects the potential from many potentials generated by resistance-dividing the negative reference potentials V6-V10. The polarity control signal is supplied to the DAC 3b.
  • the DAC 3b selects a potential corresponding to the sub-pixel data from many potentials obtained by resistance-dividing the potential generated from the potential generation circuit 5, on the basis of the polarity control signal and the sub-pixel data. If the potential is selected by the DAC 3b, the current corresponding to the selected potential is amplified by the amplifier 3a and then transferred to the corresponding source bus S (see Fig. 2). When the TFT turns on by the signal transferred to the gate bus, the signal representing the potential transferred to the source bas S is transferred to each sub-pixel electrode through the TFT. By this, the potential corresponding to each of the sub-pixel data is applied to each of the sub pixel electrodes. Consequently, a voltage is applied to liquid crystal layer sandwiched between the common electrode and each sub-pixel electrode. The liquid crystal layer can be driven in response to the potential supplied on each sub-pixel electrode, the image is displayed on the liquid crystal panel 1.
  • the conventional liquid crystal display device does not comprise the positive correction part 52 and the negative correction part 54.
  • the conventional liquid crystal display does not comprise the positive correction part 52 and the negative correction part 54.
  • Fig. 3 is a timing chart showing the timing when the potentials are applied to the respective sub-pixel electrodes En, En + 1 , and En + 2.
  • Each of the gate buses Gn-1, Gn, Gn+1, and Gn + 2 receives a signal containing pulses PI, P2 (having a potential Vg) which alternately occurring every one vertical period.
  • Each of the pulses PI, P2 generated at each of the gate buses generates at the timing delayed only one horizontal period, compared with the preceding gate bus.
  • the corresponding TFT enters its ON state.
  • the source bus S receives a signal in which rectangular waves of periodicity T occur repeatedly.
  • the rectangular wave of periodicity T is represented by both a potential
  • the source bus, the gate bus, the electrode, and the like are formed in each of portion corresponding to each sub-pixel.
  • These bus and electrode form capacitance such as parasitic capacitance Cgd caused by the gate and drain electrodes of the
  • sub-pixel capacitance (hereinafter, the total capacitance is referred to as the sub-pixel capacitance) is represented by the following equation.
  • Ct (i) Cgd (i) + Cs (i) + Clc (i) + Cdd (i) + Cdd (i + 1) (1)
  • Cgd ⁇ takes the same value for each of the sub-pixels when the sub- pixels are equal to each other with respect to the lightness. Therefore, in the following description, Cgd(i) is constant regardless of the value of "i". Thus, Cgd(i) may be simply denoted by Cgd, except for the case that there must be a need to clarify which sub-pixels does Cgd exist in.
  • each of Cs(i), Clc(i), and Cdd(i) takes the same value for each of the sub-pixels when the sub-pixels are equal to each other with respect to the lightness. Therefore, regarding Cs (i), Clc (i), and Cdd (i), they may be simply denoted by Cs, Clc, and Cdd, respectively, except for the case that there must be a need to clarify which sub-pixels dose each of Cs, Clc, and Cdd exist in.
  • the potential Vsp is temporarily written in the sub-pixel electrode En (at the time t2).
  • the potential of the sub-pixel electrode En is eventually kept the value represented by the following equation (2).
  • V(+) Vsp - ⁇ Vc... (2)
  • the potential eventually kept in the sub-pixel electrode when the positive potential is applied on the sub-pixel electrode is referred to as a positive writing potential.
  • a potential with the amplitude of "A” which is correspond to the pulse P2 occurring after one vertical period from the Pulse PI of the gate bus Gn-1, is generated through the accumulated capacitance Cs (n).
  • the pulse P2 of the gate bus Gn is generated during the period of t5 to t6, and then the TFT (n) becomes the ON state during the only time corresponding to a pulse width of the pulse P2.
  • a potential Vsn (hereinafter, the potential Vsn may be referred to as a negative potential) is supplied to the sub-pixel electrode En from the souse bus S via the TFT (n).
  • the potential Vsn instead of the potential V (+) is temporarily written in the sub-pixel electrode En (at the time t6).
  • the potential Vn (n) of sub-pixel electrode En reduces by the kickbag amount ⁇ Vc (at the time t6) because of the influence of storage capacitance Cgd (n) (at the time t6).
  • the potential of the sub-pixel electrode En is eventually kept the value represented by the following equation (3).
  • V (-) Vsn - ⁇ Vc .... (3)
  • the potential eventually kept in the sub-pixel electrode when the negative potential is applied on the sub-pixel electrode is referred to as a negative writing potential.
  • Vcom (Vsp + Vsn) / 2 - ⁇ Vc (4)
  • Va Vsp - Vsn ....(5)
  • the potential difference between the positive writing potential and the negative writing potential of each sub-pixel potential is referred to as a writing potential difference.
  • Pulses PI, P2 are appeared in the gate bus Gn + 1 after a delay of one horizontal period from those of the gate bus Gn.
  • the potential of the source bus S is a positive potential Vsp during the period K3 where the pulse PI is generated in the gate bus Gn+1
  • the potential of the source bus S is a negative potential Vsn during the period K4 where the pulse P2 is generated in the gate bus Gn+1.
  • the positive potential Vsp is written in the sub-pixel electrode En+1 with a timing corresponding to a delay of one horizontal period with respect to the preceding electrode En (at the time t3).
  • the negative potential Vsn is written in the sub-pixel electrode En+1 with a timing corresponding to a delay of one horizontal period with respect to the preceding electrode En (at the time t7). Consequently, the potential waveform (2) of the sub-pixel electrode En+1 has the same form as the potential waveform (1) of the sub-pixel electrode En, in addition to, the potential waveform (2) is shifted by just one horizontal period with respect to the potential waveform (1) in the direction of causing a time delay.
  • Pulses P 1 , P2 are appeared in the gate bus Gn+2 after a delay of one horizontal period from those of the gate bus Gn+1.
  • the potential of the source bus S is a negative potential Vsn during the period K5 where the pulse PI is generated in the gate bus Gn+2
  • the potential of the source bus S is a positive potential Vsp during the period K6 where the pulse P2 is generated in the gate bus Gn+2.
  • the negative potential Vsn which is opposite to that of the preceding sub-pixel electrode En+1, is written in the sub-pixel electrode En+2 (at the time 4).
  • the positive potential Vsp which is opposite to that of the preceding sub-pixel electrode En+1, is written in the sub-pixel electrode En+2 (at the time t8). Consequently, in the potential waveform (3) of the sub-pixel electrode En+2, its positive and negative writing potentials appear contrarily in comparison with the potential waveforms (1), (2) of their respective sub-pixel electrodes En, En+1.
  • the potential waveforms of the sub-pixel electrode En+3 can be considered just as in the case of the potential waveform (3) of the sub-pixel electrode En+2. That is, the potential waveform of the sub-pixel electrode En+3 has the same form as the potential waveform (3), in addition to, the potential waveform of the sub-pixel electrode En+3 is shifted by just one horizontal period with respect to the potential waveform (3) in the direction of causing a time delay.
  • Fig. 4 shows a potential waveform of the sub-pixel electrode En in consideration of the coupling capacitance Cdd.
  • the potential waveforms (1), (2) which are selected from the potential waveforms (1), (2), and (3) of Fig. 3 obtained in the absence of the coupling capacitance, are shown for the purpose of facilitating the understanding the difference between the potential waveforms in the presence or absence of the coupling capacitance Cdd.
  • Ct (i) Cgd (i) + Cs (i) + Clc (i) + Cdd (i) + Cdd (i + 1)
  • Ct (i) is substantially constant in spite of the variations in the value of "i " (i.e., even though any sub-pixel is considered), so that Ct(i) can be simply referred to as Ct.
  • the potential waveform of the sub-pixel electrode En can be represented as (1)'. That is, the sub-pixel electrode En receives the influence of the coupling capacitance Cdd (n + 1) (see Fig.
  • the potential waveform (1)' in consideration of the coupling capacitance can be explained just as in the case of disregarding the coupling capacitance as described above up to the time t2. Now, attention must be directed toward the potential waveform (2) of the sub-pixel electrode En+1 which is subsequent to the sub-pixel electrode En.
  • the potential V (n+1) of the sub-pixel electrode En+1 is a negative writing potential V(-).
  • the potential of the sub- pixel electrode En+1 changes from the negative writing potential V (-) to the positive writing potential V (+) since the sub-pixel R (n) and the sub-pixel R (n+1) are driven with the same polarity.
  • the coupling capacitance Cdd is present between the sub-pixel electrode En and the sub-pixel electrode En+1. Therefore, when the potential of the sub- pixel electrode En+1 changes from the negative writing potential V (-) to the positive writing potential V (+), the positive writing potential Vp (n) of the sub-pixel electrode En can be expressed by the following equation in consideration of the law of conservation of charge with respect to the sub-pixel R (n).
  • Vp (n) V (+) + ⁇ (V (+) - V (-) ⁇ x Cdd/Ct
  • Vp (n) V (+) + ⁇ Vdd (7)
  • the positive writing potential Vp (n) of the sub-pixel electrode En is V (+) without consideration of the coupling capacitance (see the potential waveform (1)), while it is ⁇ Vdd larger than V(+) in consideration of the coupling capacitance. Furthermore, if the pulse P2 is generated in the gate bus Gn-1, a potential with an amplitude of "A" that corresponds to the pulse P2 is appeared in the potential waveform (1)' of the sub-pixel electrode En. Subsequently, if the pulse P2 is generated in the gate bus Gn, the TFT (n) becomes the ON state during the only time corresponding to a pulse width of the pulse P2.
  • Vsn a negative potential supplied from the source bus S to the sub-pixel electrode En via the TFT (n).
  • the potential Vsn is written in the sub-pixel electrode En (at the time t6).
  • attention must be directed toward the potential waveform (2) of the sub-pixel electrode En+1 which is subsequent to the sub-pixel electrode En.
  • the potential V (n+1) of the sub-pixel electrode En+1 is a positive writing potential V(+).
  • the potential of the sub-pixel electrode En+1 changes from the positive writing potential V(+) to the negative writing potential V(-) since the sub-pixel R(n) and the sub-pixel R(n+1) are driven with the same polarity.
  • the coupling capacitance Cdd is present between the sub-pixel electrode En and the sub-pixel electrode En+1.
  • the negative writing potential Vn(n) of the sub-pixel electrode En can be expressed by the following equation in consideration of the law of conservation of charge with respect to the sub-pixel R(n).
  • Vn(n) cannot be expressed simply as V(-) because it is influenced by the potential changes in the subsequent sub-pixel electrode En+1. That is to say, Vn(n) changes by the amount corresponding to the second term on the right side of the equation, i.e, (Vsp - Vsn) x Cdd/Ct. If this second term of the equation is replaced just as in the case of the equation (7), we obtain the equation (8) as follows.
  • Vn (n) V (-) - ⁇ Vdd (8)
  • Fig. 5 shows a potential waveform of the sub-pixel electrode En+1 in consideration of the coupling capacitance Cdd.
  • the potential waveforms (2), (3) which are selected from the potential waveforms (1), (2), and (3) of Fig. 3 obtained in the absence of the coupling capacitance, are shown for the purpose of facilitating the understanding the difference between the potential waveforms in the presence or absence of the coupling capacitance Cdd.
  • the potential waveform of the sub-pixel electrode En+1 can be represented as (2)'. That is, the sub-pixel electrode En+1 receives the influence of the coupling capacitance Cdd (n+2) (see Fig. 2), so that the positive writing potential does not become V(+) but it becomes V(+) - ⁇ Vdd and the negative writing potential does not become V(-) but it becomes V(-) + ⁇ Vdd. In the following description, we will give reasons why such changes are occurred.
  • the coupling capacitance Cdd (n+1) of the coupling capacitance Cdd(i) is present and that the other coupling capacitances Cdd are disregarded.
  • the coupling capacitance Cdd (n+2) is the coupling capacitance between the sub-pixel electrode En+1 and the sub-pixel electrode En+2.
  • the potential waveform (2)' in consideration of the coupling capacitance can be explained just as in the case of disregarding the coupling capacitance as described above up to the time t3. Now, attention must be directed toward the potential waveform (3) of the sub-pixel electrode En+2 which is subsequent to the sub-pixel electrode En+1.
  • the potential V (n+2) of the sub-pixel electrode En+2 is a positive writing potential V(+).
  • the potential of the sub- pixel electrode En+2 changes from the positive writing potential V (+) to the negative writing potential V (-) since the sub-pixel R (n+1) and the sub-pixel R (n+2) are driven with the opposite polarities.
  • the coupling capacitance Cdd is present between the sub- pixel electrode En+1 and the sub-pixel electrode En+2.
  • the positive writing potential Vp (n+1) of the sub-pixel electrode En+1 can be expressed by the following equation in consideration of the law of conservation of charge with respect to the sub-pixel R (n+1).
  • Vp (n+1) cannot be expressed simply as V (+) because it is influenced by the potential changes in the subsequent sub-pixel electrode En+2. That is to say, Vp(n+1) changes by the amount corresponding to the second term on the right side of the equation, i.e, (Vsp - Vsn) x Cdd/Ct. If this second term of the equation is replaced with ⁇ Vdd just as in the case of the equations (7) and (8), we obtain the equation (9) as follows.
  • Vp (n+1) V (+) - ⁇ Vdd (9)
  • the positive writing potential of the sub-pixel electrode En+1 is V (+) without consideration of the coupling capacitance (see the potential waveform (2)), while it is ⁇ Vdd smaller than V(+) in consideration of the coupling capacitance. Furthermore, if the pulse P2 is generated in the gate bus Gn, a potential with an amplitude of "A" that corresponds to the pulse P2 is appeared in the potential waveform (2)' of the sub-pixel electrode En+1. Subsequently, if the pulse P2 is generated in the gate bus Gn+1, the TFT (n+1) becomes the ON state during the only time corresponding to a pulse width of the pulse P2.
  • the potential V (n+2) of the sub-pixel electrode En+2 is a negative writing potential V(-).
  • the potential of the sub-pixel electrode En+2 changes from the negative writing potential V (-) to the positive writing potential V (+) since the sub-pixel R (n+1) and the sub-pixel R (n+2) are driven with the opposite polarity.
  • the coupling capacitance Cdd (see Fig.2)is present between the sub-pixel electrode En+1 and the sub-pixel electrode En+2.
  • Vn(n+1) cannot be expressed simply as V(-) because it is influenced by the potential changes in the subsequent sub-pixel electrode En+2. That is to say, Vn(n+1) changes by the amount corresponding to the second term on the right side of the equation, i.e, (Vsp - Vsn) x Cdd/Ct. If this second term of the equation is replaced just as in the case of the equation (7), we obtain the equation (10) as follows.
  • Vn (n+1) V (-) + ⁇ Vdd (10)
  • the negative writing potential Vn(n+1) of the sub-pixel electrode En+1 is V(-) without consideration of the coupling capacitance (see the potential waveform (2)), while it is ⁇ Vdd larger than V(-) in consideration of the coupling capacitance.
  • the positive writing potential of the sub-pixel electrode R(n+2) in consideration of the coupling capacitance is ⁇ Vdd smaller than the positive writing potential of the same sub-pixel electrode R(n+2) without consideration of the coupling capacitance, since the sub- pixel electrode R(n+3) subsequent to the sub-pixel electrode R(n+2) is changed from the positive writing potential to the negative writing potential immediately after a potential is written into the sub-pixel electrode R(n+2).
  • the negative writing potential of the sub-pixel electrode R(n+2) in consideration of the coupling capacitance is ⁇ Vdd larger than the positive writing potential of the same sub-pixel electrode R(n+2) without consideration of the coupling capacitance, since the sub-pixel electrode R(n+3) subsequent to the sub-pixel electrode R(n+2) is changed from the negative writing potential to the positive writing potential.
  • Fig. 6 shows a potential waveform of the sub-pixel electrode En, En+1 and
  • i n ⁇ l, n ⁇ 3
  • the coupling capacitance is considered, on the other hand, we can find it from the above equations (11) to (14) that there are two different writing potential differences, one is 2 ⁇ Vdd larger than Va and the other is 2 ⁇ Vdd smaller than Va, are generated alternately. In the above description, only one source bus is considered.
  • a potential generation circuit 5 comprises a positive correction part 52 and a negative correction part 54. If an image to be represented by the uniform lightness (i.e, an image of blue sky) is displayed by using the liquid crystal display device shown in Fig. 1 comprising the correction parts 52 and 54, the blue sky can be displayed by uniform lightness without light and dark patterns on the whole screen.
  • Fig. 7 is a timing chart showing the timing when the potentials are applied to the respective sub-pixel electrodes En, En + 1, and En + 2.
  • the cause of horizontal stripes where light column and dark column occur alternately may be considered as follows. That is, one of sub-pixel electrodes adjacent to each other has a writing potential difference which is 2 ⁇ Vdd larger than Va and the other has a writing potential difference which is 2 ⁇ Vdd smaller than Va, so that different voltages are applied on the sub-pixel electrodes, respectively. Therefore, the horizontal stripes can be prevented by equally applying voltages on the respective sub-pixels if the difference between the potential Vcom of the common electrode and the positive writing potential becomes equal regardless of the sub-pixels and the difference between the potential Vcom of the common electrode and the negative writing potential also becomes equal regardless of the sub-pixels.
  • the conventional liquid crystal display as described above with reference to Fig.
  • potentials Vsp are evenly written on the respective sub-pixels in order to equalize positive writing potentials of the respective sub-pixel electrodes
  • potentials Vsn are evenly written on the respective sub-pixels in order to equalize negative writing potentials of the respective sub-pixel electrode.
  • the positive and negative writing potentials of each sub-pixel electrode are influenced by the coupling capacitance, so that these potentials are varied with an amount of ⁇ Vdd in comparison with those of each sub- pixel electrode without consideration of the coupling capacitance.
  • the difference between the positive or negative writing potential and the potential Vcom of the common electrodes is varied among the sub-pixels.
  • the potential of the sub-pixel electrode where the potential V(+) + ⁇ Vdd is appeared can be decreased by an amount of ⁇ Vdd, and further, if the potential of the sub- pixel electrode where the potential V(+) - ⁇ Vdd is appeared can be increased by an amount of ⁇ Vdd, the positive writing potentials of all sub-pixel electrode becomes V(+), so that, the differences between the potential Vcom of the common electrode and each of the positive writing potentials of all sub-pixels become equal each other.
  • the potential of the sub-pixel electrode where the potential V(-) + ⁇ Vdd is appeared can be decreased by an amount of ⁇ Vdd, and further, if the potential of the sub-pixel electrode where the potential V(-) - ⁇ Vdd is appeared can be increased by an amount of ⁇ Vdd, the negative writing potentials of all sub-pixel electrode becomes V(-), so that, the differences between the potential Vcom of the common electrode and each of the negative writing potential of all sub pixel electrodes become equal each other. That is, the potential of each sub-pixel electrode is decreased or increased by the amount of ⁇ Vdd. Therefore, the correction may be performed by the amount ⁇ Vdd.
  • a potential generation circuit 5 in order to correct a signal waveform of the source bus S to a waveform shown in Fig. 7, a potential generation circuit 5 has a positive correction part 52 and a negative correction part 54 as shown in Fig. 1.
  • the correction of the potential waveform is performed as follows;
  • the positive correction part 52 In order to correct the potentials of the source bus S to each of the potentials Vsp(-) and Vsp(+) during the period where the positive potential is written on each of the first and second sub-pixel electrodes, the positive correction part 52 generates rectangular signals to be required to correct the potentials of the source bus S from Vsp to each of the Vsp (-) and Vsp (+). Furthermore, in order to correct the potentials of the source bus S to each of the Vsn(+) and Vsn(-) during the period where the negative potential is written on each of the first and second sub-pixel electrodes, the negative correction part 54 generates rectangular signals to be required to correct the potential of the source bus S from Vsn to each ofVsn(+) and Vsn(-).
  • an image to be represented by the uniform lightness i.e, an image of blue sky
  • the blue sky can be displayed by uniform lightness without light and dark patterns on the whole screen.
  • the correction amount ⁇ Vdd of the potential of the source bus S can be defined to a predetermined constant value calculated by using equation (6).
  • the lightness of each sub-pixel is varied in multiple levels (e.g., 64 levels). Therefore, Vs and Vn in the equation (6) is inherently varied. That is, ⁇ Vdd in the equation (6) is also varied. For example, if the liquid crystal display device of a normally white mode is considered, the writing potential deference is more enlarged while the sub-pixel is more darkened, resulting in the increase in ⁇ Vdd.
  • ⁇ Vdd in the equation (6) is a variation amount of the positive and negative writing potentials of each sub-pixel electrode, which variation amount is caused by the writing potential difference of the subsequent (next line) sub-pixel electrode. Therefore, the correction amount ⁇ Vdd corresponding to each sub- pixel may be varied in response to the brightness of the subsequent sub-pixels.
  • two different correction parts i.e., positive and negative correction parts 52, 54
  • ⁇ Vdd is several tens of mV.
  • the center voltages at alternation driving about the sub-pixels adjacent to each other in the direction of extending the source bus S (see Fig. 2) are deviated from each other.
  • such a deviation can be neglected because of considering the deviation of the potential Vcom of the common electrode in a panel surface.
  • the extent of variations in the light transmission with respect to the extent of variations in voltage is large at a region corresponding to a halftone.
  • the liquid crystal display device comprises both the positive and negative correction parts 52, 54.
  • These correction parts 52, 54 are responsible for preventing the generation of horizontal stripes by correcting the potential of the source bus S with a predetermined amount of the correction on the basis of the coupling capacity.
  • data correction means for correcting a plurality of sub- pixel on the basis of the coupling capacitance may be provided instead of the correction parts described above.
  • the generation of horizontal stripes may be prevented by selecting each of potentials corresponding to a plurality of pixel data which had already corrected by the data correction means and supplying the selected potential to the source bus S.
  • the liquid crystal display device of the present embodiment adopts 2 column- 1 row method as a driving method. According to the present invention, it is not limited to such a method, it is also possible to adopt other driving methods. One of such methods is 3 column- 1 row method. The variations in the voltage of each sub-pixel by the coupling capacitance formed between the adjacent sub-pixels is prevented by the present invention.
  • the liquid crystal display device is in the type of displaying a color image.
  • the liquid crystal display device according to the present invention can be applied to a black-and-white display device, in order to effectively prevent the generation of horizontal stripes in the black-and-white display device.
  • the reference potentials VI to V 10 are directly introduced into the DAC 3b.
  • a buffer of an amplifier may be provided between the ladder resistances and each DAC 3b.
  • the potential Vcom of the common electrode is maintained at constant. According to the present invention, it is also possible to provide the potential Vcom as a variable. According to the present invention, horizontal stripes are prevented even though the liquid crystal display device displays an image represented by a substantially constant lightness.
  • Fig. 1 is a block diagram that illustrates the configuration of a liquid crystal display device as one mode for carrying out the invention.
  • Fig. 2 is an enlarged view of a part of the TFT substrate of the liquid crystal panel 1 shown in Fig. 1.
  • Fig. 3 is a timing chart showing the timing when the potentials are applied to the respective sub-pixel electrodes En, En + 1, and En + 2.
  • Fig. 4 shows a potential waveform of the sub-pixel electrode En in consideration of the coupling capacitance Cdd.
  • Fig. 5 shows a potential waveform of the sub-pixel electrode En+1 in consideration of the coupling capacitance Cdd.
  • Fig. 6 shows a potential waveform of the sub-pixel electrode En, En+1 and En+2 in consideration of the coupling capacitance Cdd.
  • Fig. 7 is a timing chart showing the timing when the potentials are applied to the respective sub-pixel electrodes En, En + 1, and En + 2.
  • Fig.8 shows a conceptual rendering of 2 column- 1 row method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention porte sur un dispositif d'affichage à cristaux liquides à matrice active comportant des sous-pixels et sur lequel est appliqué, toutes les deux rangées et sur chaque colonne, un schéma d'inversion de polarité. Des dispositifs de commande de colonne reçoivent des signaux d'entrée d'image numérique et comprennent un dénumériseur qui fait une sélection dans les tensions générées par un générateur de potentiels de référence pourvu d'alimentations électriques côté positif et côté négatif et d'une échelle de résistance. Le problème qui se pose concerne les capacités parasites entre des sous-pixels voisins qui ont un effet de couplage qui modifie les tensions appliquées, ce qui donne lieu à l'apparition de bandes dans des sections de l'image qui devraient être uniformes. Selon cette invention, le problème est résolu par l'ajout de tensions de correction côté positif et côté négatif aux tensions d'alimentation électrique côté positif et côté négatif du générateur de potentiels de référence. Ces tensions de correction sont sélectionnées de façon à compenser les modifications intervenues dans les tensions appliquées aux pixels et imputables aux capacités parasites.
PCT/EP2000/009674 1999-09-30 2000-09-29 Dispositif d'affichage a cristaux liquides avec commande de correction de tension pour reduire les effets negatifs du couplage capacitif entre des electrodes de pixels adjacentes WO2001024154A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP99/279281 1999-09-30
JP27928199A JP4521903B2 (ja) 1999-09-30 1999-09-30 液晶表示装置

Publications (1)

Publication Number Publication Date
WO2001024154A1 true WO2001024154A1 (fr) 2001-04-05

Family

ID=17608990

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2000/009674 WO2001024154A1 (fr) 1999-09-30 2000-09-29 Dispositif d'affichage a cristaux liquides avec commande de correction de tension pour reduire les effets negatifs du couplage capacitif entre des electrodes de pixels adjacentes

Country Status (2)

Country Link
JP (1) JP4521903B2 (fr)
WO (1) WO2001024154A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1293957A2 (fr) 2001-09-07 2003-03-19 Samsung Electronics Co., Ltd. Dispositif d'affichage à cristaux liquides, circuit d'excitation d'un dispositif d'affichage à cristaux liquides et méthode de génération de tensions de niveaux de gris
WO2004023448A1 (fr) * 2002-09-04 2004-03-18 Koninklijke Philips Electronics N.V. Dispositif d'affichage d'image avec circuits de compensation de chute de tension dans l'electrode commune pour affichages a cristaux liquides a matrice active
WO2005081216A1 (fr) * 2004-02-19 2005-09-01 Koninklijke Philips Electronics N.V. Generateur de tensions et dispositif d'affichage d'images
WO2006033079A2 (fr) * 2004-09-24 2006-03-30 Tpo Hong Kong Holding Limited Dispositif d'affichage a cristaux liquides a matrice active et procede de commande de ce dernier
US7522127B2 (en) 2003-12-17 2009-04-21 Sharp Kabushiki Kaisha Driving method for driving a display device including display pixels, each of which includes a switching element and a pixel electrode, display device, and medium
US9111475B2 (en) 2011-02-18 2015-08-18 Sharp Kabushiki Kaisha Method of driving display device, program, and display device
EP3285251A4 (fr) * 2015-04-17 2018-11-07 BOE Technology Group Co., Ltd. Circuit de génération de tension gamma, unité de pilotage, dispositif d'affichage et procédé de réglage de coordonnée de couleur
CN109741705A (zh) * 2018-06-29 2019-05-10 厦门天马微电子有限公司 一种显示面板的像素补偿方法及装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4761681B2 (ja) * 2000-10-05 2011-08-31 株式会社半導体エネルギー研究所 液晶表示装置
JP2003075869A (ja) * 2001-09-05 2003-03-12 Toshiba Corp 平面表示素子
KR100890026B1 (ko) * 2002-11-20 2009-03-25 삼성전자주식회사 액정 표시 장치의 구동 장치 및 그 방법
JP4939958B2 (ja) * 2007-01-31 2012-05-30 東芝モバイルディスプレイ株式会社 液晶表示装置
JP6646392B2 (ja) * 2015-09-18 2020-02-14 ラピスセミコンダクタ株式会社 表示ドライバ

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4714921A (en) * 1985-02-06 1987-12-22 Canon Kabushiki Kaisha Display panel and method of driving the same
US5250937A (en) * 1990-03-08 1993-10-05 Hitachi, Ltd. Half tone liquid crystal display circuit with an A.C. voltage divider for drivers
JPH0981089A (ja) * 1995-09-19 1997-03-28 Fujitsu Ltd アクティブマトリクス型液晶表示装置及びその駆動方法
JPH10171412A (ja) * 1996-12-09 1998-06-26 Nec Corp アクティブマトリクス型液晶表示装置
JPH10301538A (ja) * 1997-04-25 1998-11-13 Sharp Corp データ線駆動回路およびこれを備えたアクティブマトリクス型液晶表示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69411223T2 (de) * 1993-04-30 1999-02-18 Ibm Verfahren und Vorrichtung zum Eliminieren des Übersprechens in einer Flüssigkristall-Anzeigeeinrichtung mit aktiver Matrix
JPH08263011A (ja) * 1995-03-20 1996-10-11 Sony Corp アクティブマトリックス型液晶表示パネルの駆動方法および液晶表示装置
JP3688786B2 (ja) * 1995-07-24 2005-08-31 富士通ディスプレイテクノロジーズ株式会社 トランジスタマトリクス装置
JP3658932B2 (ja) * 1997-08-07 2005-06-15 セイコーエプソン株式会社 液晶素子の駆動方法及び液晶表示装置及び電子機器
KR100478577B1 (ko) * 1998-10-16 2005-03-28 세이코 엡슨 가부시키가이샤 전기 광학 장치의 구동회로 및 그 구동방법, ｄ/ａ컨버터, 신호선 구동회로, 전기 광학 패널, 투사형표시장치, 및 전자기기

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4714921A (en) * 1985-02-06 1987-12-22 Canon Kabushiki Kaisha Display panel and method of driving the same
US5250937A (en) * 1990-03-08 1993-10-05 Hitachi, Ltd. Half tone liquid crystal display circuit with an A.C. voltage divider for drivers
JPH0981089A (ja) * 1995-09-19 1997-03-28 Fujitsu Ltd アクティブマトリクス型液晶表示装置及びその駆動方法
US6040814A (en) * 1995-09-19 2000-03-21 Fujitsu Limited Active-matrix liquid crystal display and method of driving same
JPH10171412A (ja) * 1996-12-09 1998-06-26 Nec Corp アクティブマトリクス型液晶表示装置
US6075507A (en) * 1996-12-09 2000-06-13 Nec Corporation Active-matrix display system with less signal line drive circuits
JPH10301538A (ja) * 1997-04-25 1998-11-13 Sharp Corp データ線駆動回路およびこれを備えたアクティブマトリクス型液晶表示装置

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 07 31 July 1997 (1997-07-31) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 11 30 September 1998 (1998-09-30) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 02 26 February 1999 (1999-02-26) *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8031148B2 (en) 2001-09-07 2011-10-04 Samsung Electronics Co., Ltd. Liquid crystal display, apparatus for driving a liquid crystal display, and method of generating gray voltages
US7339569B2 (en) 2001-09-07 2008-03-04 Samsung Electronics Co., Ltd. Liquid crystal display, apparatus for driving a liquid crystal display, and method of generating gray voltages
EP1293957A3 (fr) * 2001-09-07 2008-04-30 Samsung Electronics Co., Ltd. Dispositif d'affichage à cristaux liquides, circuit d'excitation d'un dispositif d'affichage à cristaux liquides et méthode de génération de tensions de niveaux de gris
EP1293957A2 (fr) 2001-09-07 2003-03-19 Samsung Electronics Co., Ltd. Dispositif d'affichage à cristaux liquides, circuit d'excitation d'un dispositif d'affichage à cristaux liquides et méthode de génération de tensions de niveaux de gris
WO2004023448A1 (fr) * 2002-09-04 2004-03-18 Koninklijke Philips Electronics N.V. Dispositif d'affichage d'image avec circuits de compensation de chute de tension dans l'electrode commune pour affichages a cristaux liquides a matrice active
US7522127B2 (en) 2003-12-17 2009-04-21 Sharp Kabushiki Kaisha Driving method for driving a display device including display pixels, each of which includes a switching element and a pixel electrode, display device, and medium
WO2005081216A1 (fr) * 2004-02-19 2005-09-01 Koninklijke Philips Electronics N.V. Generateur de tensions et dispositif d'affichage d'images
WO2006033079A3 (fr) * 2004-09-24 2008-06-26 Tpo Hong Kong Holding Ltd Dispositif d'affichage a cristaux liquides a matrice active et procede de commande de ce dernier
WO2006033079A2 (fr) * 2004-09-24 2006-03-30 Tpo Hong Kong Holding Limited Dispositif d'affichage a cristaux liquides a matrice active et procede de commande de ce dernier
US9111475B2 (en) 2011-02-18 2015-08-18 Sharp Kabushiki Kaisha Method of driving display device, program, and display device
EP3285251A4 (fr) * 2015-04-17 2018-11-07 BOE Technology Group Co., Ltd. Circuit de génération de tension gamma, unité de pilotage, dispositif d'affichage et procédé de réglage de coordonnée de couleur
CN109741705A (zh) * 2018-06-29 2019-05-10 厦门天马微电子有限公司 一种显示面板的像素补偿方法及装置
CN109741705B (zh) * 2018-06-29 2022-04-08 厦门天马微电子有限公司 一种显示面板的像素补偿方法及装置

Also Published As

Publication number Publication date
JP2001108964A (ja) 2001-04-20
JP4521903B2 (ja) 2010-08-11

Similar Documents

Publication Publication Date Title
KR100777705B1 (ko) 액정 표시 장치 및 그 구동 방법
US20050253829A1 (en) Display device and display device driving method
US20040017344A1 (en) Liquid-crystal display device and driving method thereof
US20100002021A1 (en) Display panel driving method and display apparatus
US20030222840A1 (en) Liquid crystal display device and driving method for liquid crystal display device
JPH05216429A (ja) 表示装置
JPH0968689A (ja) 液晶表示装置の駆動方法
JPH1062748A (ja) アクティブマトリクス型表示装置の調整方法
US8605019B2 (en) Display device and display device driving method, and display driving control method
JP4536190B2 (ja) 液晶表示装置
WO2001024154A1 (fr) Dispositif d'affichage a cristaux liquides avec commande de correction de tension pour reduire les effets negatifs du couplage capacitif entre des electrodes de pixels adjacentes
US20080088615A1 (en) Driving method for liquid crystal display using block cycle inversion
US20040239605A1 (en) Device and method for driving polarity inversion of electrodes of LCD panel
JP3426723B2 (ja) 液晶表示装置及びその駆動方式
US7760196B2 (en) Impulsive driving liquid crystal display and driving method thereof
US20050168570A1 (en) Flat panel display and driving method thereof
KR101030535B1 (ko) 액정표시장치의 구동방법
KR101113997B1 (ko) 액정 표시 장치 및 그의 구동 방법
KR100965587B1 (ko) 액정표시장치 및 이의 구동방법
KR20030083310A (ko) 액정표시장치
KR100977224B1 (ko) 액정표시장치
KR100928210B1 (ko) 액정표시장치 및 그 구동방법
JP3627354B2 (ja) 液晶表示装置の駆動方法
KR100971390B1 (ko) 감마 기준 전압 발생 회로
KR20070002311A (ko) 액정 표시 장치 및 그의 구동 방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase